CD74AC257SM [TI]
Quad 2-Input Multiplexer with Three-State Outputs; 四2输入多路复用器具有三态输出
| 型号： | CD74AC257SM |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Quad 2-Input Multiplexer with Three-State Outputs |
| 文件： | 总14页 (文件大小：288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54/74AC257, CD54/74ACT257,
CD74ACT258
Data sheet acquired from Harris Semiconductor
SCHS248A
Quad 2-Input Multiplexer
with Three-State Outputs
August 1998 - Revised May 2000
Features
Description
• ’AC257, ’ACT257. . . . . . . . . . . . . Non-Inverting Outputs The ’AC257, ’ACT257 and CD74ACT258 are quad 2-input
multiplexers with three-state outputs that utilize Advanced
CMOS Logic technology. Each of these devices selects four
• CD74ACT258 . . . . . . . . . . . . . . . . . . . Inverting Outputs
bits of data from two sources under the control of a common
Select input (S). The Output Enable (OE) is active LOW.
When OE is HIGH, all of the outputs (Y or Y) are in the high-
impedance state regardless of all other input conditions.
• Buffered Inputs
• Typical Propagation Delay
o
- 4.4ns at V
CC
= 5V, T = 25 C, C = 50pF
A L
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
Moving data from two groups of registers to four common
output buses is a common use of the ’AC257, ’ACT257, and
CD74ACT258. The state of the Select input determines the
particular register from which the data comes. The ’AC257,
’ACT257 and CD74ACT258 can also be used as function
generators.
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
• Balanced Propagation Delays
Ordering Information
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
PART
NUMBER
TEMP.
RANGE ( C)
o
PACKAGE
• ±24mA Output Drive Current
CD54AC257F3A
CD74AC257E
-55 to 125
o
16 Ld CERDIP
- Fanout to 15 FAST™ ICs
0 to 70 C, -40 to 85, 16 Ld PDIP
-55 to 125
Drives 50Ω Transmission Lines
o
CD74AC257M
0 to 70 C, -40 to 85, 16 Ld SOIC
-55 to 125
Pinout
CD54ACT257F3A
CD74ACT257E
-55 to 125
o
16 Ld CERDIP
CD54AC257, CD54ACT257
(CERDIP)
0 to 70 C, -40 to 85, 16 Ld PDIP
-55 to 125
CD74AC257, CD74ACT257, CD74ACT258
(PDIP, SOIC)
o
CD74ACT257M
CD74ACT258E
CD74ACT258M
NOTES:
0 to 70 C, -40 to 85, 16 Ld SOIC
-55 to 125
TOP VIEW
o
0 to 70 C, -40 to 85, 16 Ld PDIP
ACT258
S
AC/ACT257
S
AC/ACT257 ACT258
16 V
-55 to 125
1
2
3
4
5
6
7
8
V
CC
15 OE
CC
o
0 to 70 C, -40 to 85, 16 Ld SOIC
1I
1I
1I
1I
OE
0
1
0
1
-55 to 125
14 4I
13 4I
4I
4I
0
1
0
1
1Y
1Y
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2I
0
2I
0
12 4Y
4Y
2I
1
2I
1
11 3I
0
3I
0
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local TI sales office or
customer service for ordering information.
10 3I
1
3I
1
2Y
2Y
9
3Y
3Y
GND
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
1
Copyright © 2000, Texas Instruments Incorporated
CD54/74AC257, CD54/74ACT257, CD74ACT258
Functional Diagram
AC/ACT AC/ACT
257
258
2
5
1I
2I
3I
4I
1I
2I
3I
4I
0
0
0
0
1
1
1
1
4
1Y
1Y
11
14
3
7
2Y
3Y
4Y
2Y
3Y
4Y
9
6
10
13
12
1
15
S
OE
TRUTH TABLE
DATA INPUTS
OUTPUT
ENABLE
SELECT
INPUT
257
OUTPUTS
258
OUTPUTS
OE
H
L
S
X
L
I
I
Y
Z
L
Y
Z
H
L
0
1
X
L
X
X
X
L
L
L
H
X
X
H
L
L
H
H
H
L
L
H
H
H = High level voltage, L = Low level voltage, Z = High impedance (off) state, X = Don’t Care
2
CD54/74AC257, CD54/74ACT257, CD74ACT258
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
Thermal Resistance (Typical, Note 5)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
___
___
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
DC V
or Ground Current, I
I
(Note 3) . . . . . . . . .±100mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
(Note 4)
CC
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
25 C
o
o
85 C
125 C
V
CC
PARAMETER
AC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
MAX
MIN
MAX
MIN
MAX UNITS
O
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
-
-
-
1.5
3
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
V
V
V
V
V
V
V
V
V
V
V
V
IH
-
-
-
5.5
1.5
3
-
-
-
V
-
0.3
0.3
0.3
IL
-
0.9
-
0.9
-
0.9
5.5
1.5
3
-
1.65
-
1.65
-
1.65
V
V
or V
IH IL
-0.05
1.4
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
1.4
2.9
4.4
2.48
3.8
3.85
-
-
-
-
-
-
1.4
2.9
4.4
2.4
3.7
-
-
-
-
-
-
-
OH
-0.05
-0.05
-4
4.5
3
-24
4.5
5.5
-75
(Note 6, 7)
-50
5.5
-
-
-
-
3.85
-
V
(Note 6, 7)
3
CD54/74AC257, CD54/74ACT257, CD74ACT258
DC Electrical Specifications (Continued)
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
o
o
25 C
MIN
85 C
125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
(V)
1.5
3
MAX
0.1
0.1
0.1
0.36
0.36
-
MIN
MAX
MIN
MAX UNITS
I
O
Low Level Output Voltage
V
V
or V
IH IL
0.05
0.05
0.05
12
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.5
0.5
-
V
V
V
V
V
V
OL
4.5
3
0.1
0.44
0.44
1.65
24
4.5
5.5
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
±0.1
±0.5
±1
±5
µA
µA
I
CC
GND
Three-State Leakage
Current
I
V
V
or V
-
±10
OZ
IH
IL
= V
O
CC
or GND
Quiescent Supply Current
MSI
I
V
GND
or
0
5.5
-
8
-
80
-
160
µA
CC
CC
ACT TYPES
High Level Input Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
2
-
-
2
-
-
V
V
IH
Low Level Input Voltage
High Level Output Voltage
V
4.5 to
5.5
0.8
0.8
0.8
IL
V
V
or V
IH IL
-0.05
-24
4.5
4.5
5.5
4.4
3.94
-
-
-
-
4.4
3.8
-
-
-
4.4
3.7
-
-
-
-
V
V
V
OH
-75
3.85
(Note 6, 7)
-50
5.5
-
-
-
-
3.85
-
V
(Note 6, 7)
Low Level Output Voltage
V
V
or V
IH IL
0.05
24
4.5
4.5
5.5
-
-
-
0.1
0.36
-
-
-
-
0.1
-
-
-
0.1
0.5
-
V
V
V
OL
0.44
1.65
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
±0.1
±0.5
±1
±5
µA
µA
I
CC
GND
Three-State or Leakage
Current
I
V
V
or V
-
±10
OZ
IH
IL
= V
O
CC
or GND
Quiescent Supply Current
MSI
I
V
or
0
-
5.5
-
-
8
-
-
80
-
-
160
3
µA
CC
CC
GND
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
∆I
CC
V
4.5 to
5.5
2.4
2.8
mA
CC
-2.1
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
o
o
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85 C, 75Ω at 125 C.
4
CD54/74AC257, CD54/74ACT257, CD74ACT258
ACT Input Load Table
INPUT
Data
S
UNIT LOAD
0.83
1.27
OE
1.27
NOTE: Unit load is ∆I
CC
Table, e.g., 2.4mA max at 25 C.
limit specified in DC Electrical Specifications
o
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case)
r
f
L
o
o
o
o
-40 C TO 85 C
TYP
-55 C TO 125 C
PARAMETER
AC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
TYP
MAX
UNITS
CC
Propagation Delay,
In to Y
AC/ACT257
t , t
PLH PHL
1.5
3.3
-
-
-
106
-
-
-
117
13
ns
ns
3.3
11.8
3.3
(Note 9)
5
2.4
-
8.5
2.3
-
9.3
ns
(Note 10)
Propagation Delay,
S to Y
AC/ACT257
t
, t
PLH PHL
1.5
3.3
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
153
17.1
12.2
167
18.7
13.4
91
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
168
18.8
13.4
184
20.6
14.7
100
11.2
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
4.8
3.5
-
4.7
3.4
-
Propagation Delay,
OE to Y
AC/ACT257
t
, t
,
1.5
3.3
5
PLZ PHZ
t
, t
PZL PZH
5.3
3.8
-
5.2
3.7
-
Propagation Delay,
In to Y
’AC/CD74ACT258
t , t
PLH PHL
1.5
3.3
5
2.9
2.1
-
10.2
7.3
2.8
2
Propagation Delay,
S to Y
’AC/CD74ACT258
t , t
PLH PHL
1.5
3.3
5
153
17.1
12.2
167
18.7
13.4
15
-
168
18.8
13.4
184
20.6
14.7
15
4.8
3.5
-
4.7
3.4
-
Propagation Delay,
OE to Y
’AC/CD74ACT258
t
, t
,
1.5
3.3
5
PLZ PHZ
t
, t
PZL PZH
5.3
3.8
-
5.2
3.7
-
Three-State Output
Capacitance
C
-
O
Input Capacitance
C
-
-
-
-
-
10
-
-
-
-
10
-
pF
pF
I
Power Dissipation Capacitance
C
130
130
PD
(Note 11)
ACT TYPES
Propagation Delay,
In to Y
AC/ACT257
t
, t
5
2.8
4
-
-
9.7
14
2.7
3.9
-
-
10.7
15.4
ns
ns
PLH PHL
(Note 10)
Propagation Delay,
S to Y
t
, t
5
PLH PHL
AC/ACT257
5
CD54/74AC257, CD54/74ACT257, CD74ACT258
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case) (Continued)
r
f
L
o
o
o
o
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
Propagation Delay,
OE to Y
AC/ACT257
SYMBOL
V
(V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
CC
t
, t
,
5
4.1
-
14.6
4
2.3
3.9
4
-
16.1
9.3
ns
PLZ PHZ
t , t
PZL PZH
Propagation Delay,
In to Y
’AC/CD74ACT258
t , t
PLH PHL
5
5
5
-
2.4
4
-
-
-
-
8.5
14
-
-
-
-
ns
ns
ns
pF
Propagation Delay,
S to Y
’AC/CD74ACT258
t , t
PLH PHL
15.4
16.1
15
Propagation Delay,
OE to Y
’AC/CD74ACT258
t
, t
,
4.1
-
14.6
15
PLZ PHZ
t
, t
PZL PZH
Three-State Output
Capacitance
C
-
O
Input Capacitance
C
-
-
-
-
-
10
-
-
-
-
10
-
pF
pF
I
Power Dissipation Capacitance
C
130
130
PD
(Note 11)
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. C
is used to determine the dynamic power consumption per multiplexer.
PD
AC: P = C
2
2
V
f + ∑ (C
V
f )
D
PD CC
i
L
CC
o
2
2
ACT: P = C
V
f + ∑ (C
V
f ) + V
∆I
where f = input frequency, f = output frequency, C = output load capacitance,
D
PD CC
i
L
CC
o
CC CC
i
o
L
V
= supply voltage.
CC
t = 3ns
t = 3ns
f
r
INPUT LEVEL
90%
OUTPUT
DISABLE
V
S
10%
GND
t
t
PZL
PLZ
V
0.2V
OUTPUT: LOW
TO OFF TO LOW
S
CC
V
(≠GND)
OL
t
t
PHZ
PZH
V
(≠V )
CC
OH
0.8 V
OUTPUT: HIGH
TO OFF TO HIGH
CC
V
S
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
GND (t )
t
PHZ, PZH
OPEN (t )
t
PHL, PLH
2 V
(t )
t
OTHER
CC PLZ, PZL
500 †
L
DUT
WITH
THREE-
STATE
OUTPUT
Ω
INPUTS
(TIED HIGH
OR LOW)
(OPEN DRAIN)
R
OUT
500 †
R
C
Ω
L
50pF
L
OUTPUT
DISABLE
†FOR AC SERIES ONLY: WHEN V
= 1.5V, R = 1kΩ
L
CC
FIGURE 1. THREE-STATE PROPAGATION DELAY TIMES AND TEST CIRCUIT
6
CD54/74AC257, CD54/74ACT257, CD74ACT258
t = 3ns
r
t = 3ns
f
INPUT
LEVEL
INPUT LEVEL
90%
10%
S
V
S
nI , nI , S
V
0
1
S
t
PLH
t
t
PHL
PLH
t
GND
PHL
Y
V
S
V
S
Y
FIGURE 2. INPUTS OR SELECT TO OUTPUT PROPAGATION
DELAYS (AC/ACT257)
FIGURE 3. SELECT TO OUTPUT PROPAGATION DELAYS
(CD74ACT258)
OUTPUT
R
C
(NOTE)
500Ω
L
DUT
OUTPUT
LOAD
L
50pF
NOTE: For AC Series Only: When V
= 1.5V, R = 1kΩ.
CC
L
AC
ACT
3V
Input Level
V
CC
Input Switching Voltage, V
0.5 V
0.5 V
1.5V
S
CC
CC
Output Switching Voltage, V
0.5 V
CC
S
FIGURE 4. PROPAGATION DELAY TIMES
7
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
PDIP
Drawing
CD54AC257F3A
CD54ACT257F3A
CD74AC257E
ACTIVE
ACTIVE
ACTIVE
J
J
16
16
16
1
1
TBD
TBD
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74AC257EE4
CD74AC257M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SSOP
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SSOP
SOIC
SOIC
SOIC
SOIC
N
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74AC257M96
CD74AC257M96E4
CD74AC257ME4
CD74AC257SM
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DB
N
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74ACT257E
25
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74ACT257EE4
CD74ACT257M
N
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74ACT257M96
CD74ACT257M96E4
CD74ACT257ME4
CD74ACT257SM
CD74ACT258M
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DB
D
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
CD74ACT258M96
CD74ACT258M96E4
CD74ACT258ME4
D
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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