CD74AC86M-LF [TI]
AC SERIES, QUAD 2-INPUT XOR GATE, PDSO14;
| 型号： | CD74AC86M-LF |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AC SERIES, QUAD 2-INPUT XOR GATE, PDSO14 栅 |
| 文件： | 总5页 (文件大小：36K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74AC86,
CD54/74ACT86
Data sheet acquired from Harris Semiconductor
SCHS232A
Quad 2-Input Exclusive-OR Gate
September 1998 - Revised May 2000
Features
Description
[ /Title
(CD74
AC86,
CD74
ACT86
)
• Buffered Inputs
The CD74AC86 and ’ACT86 are quad 2-input Exclusive-OR
gates that utilize Advanced CMOS Logic technology
• Typical Propagation Delay
o
- 3.2ns at V
= 5V, T = 25 C, C = 50pF
A L
CC
Ordering Information
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
PART
NUMBER
o
TEMP. RANGE ( C)
PACKAGE
/Sub-
ject
(Quad
2-Input
Exclu-
sive-
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
o
CD74AC86E
0 to 70 C, -40 to 85,
14 Ld PDIP
-55 to 125
o
CD74AC86M
0 to 70 C, -40 to 85,
14 Ld SOIC
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
-55 to 125
-55 to 125
CD54ACT86F3A
CD74ACT86E
14 Ld CERDIP
14 Ld PDIP
• Balanced Propagation Delays
o
0 to 70 C, -40 to 85,
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
-55 to 125
OR
o
CD74ACT86M
0 to 70 C, -40 to 85,
14 Ld SOIC
Gate)
/Autho
r ()
/Key-
words
(Har-
ris
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
-55 to 125
NOTES:
- Drives 50Ω Transmission Lines
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local TI sales office or
customer service for ordering information.
Semi-
con-
ductor,
Advan
ced
CMOS
,Harris
Semi-
con-
ductor,
Advan
ced
TTL)
/Cre-
ator ()
/DOCI
NFO
pdf-
Pinout
Functional Diagram
CD54ACT86
(CERDIP)
CD74AC86, CD74ACT86
(PDIP, SOIC)
14
13
12
11
10
9
1
2
3
4
5
6
7
V
1A
1B
CC
4B
4A
4Y
3B
3A
3Y
TOP VIEW
1Y
1A
1B
1
2
3
4
5
6
7
14 V
CC
2A
13 4B
12 4A
11 4Y
10 3B
1Y
2B
2A
2Y
2B
8
GND
2Y
9
8
3A
3Y
GND
TRUTH TABLE
INPUTS
OUTPUT
nA
L
nB
L
nY
L
H
H
L
H
L
L
H
H
H
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
1
Copyright © 2000, Texas Instruments Incorporated
CD74AC86, CD54/74ACT86
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
Thermal Resistance (Typical, Note 5)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
175
o
DC Output Diode Current, I
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
DC V
or Ground Current, I
I
(Note 3) . . . . . . . . .±100mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
(Note 4). . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
CC
CC
I
O
Input Rise and Fall Slew Rate, dt/dv
4.5V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
25 C
o
o
85 C
125 C
V
CC
PARAMETER
AC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
MAX
MIN
MAX
MIN
MAX UNITS
O
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
-
-
-
1.5
3
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
V
V
V
V
V
V
V
V
V
V
V
V
IH
-
-
-
5.5
1.5
3
-
-
-
V
-
0.3
0.3
0.3
IL
-
0.9
-
0.9
-
0.9
5.5
1.5
3
-
1.65
-
1.65
-
1.65
V
V
or V
IH IL
-0.05
1.4
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
1.4
2.9
4.4
2.48
3.8
3.85
-
-
-
-
-
-
1.4
2.9
4.4
2.4
3.7
-
-
-
-
-
-
-
OH
-0.05
-0.05
-4
4.5
3
-24
4.5
5.5
-75
(Note 6, 7)
-50
5.5
-
-
-
-
3.85
-
V
(Note 6, 7)
Low Level Output Voltage
V
V
or V
IH IL
0.05
0.05
0.05
12
1.5
3
-
-
-
-
-
-
0.1
0.1
0.1
0.36
0.36
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.5
0.5
-
V
V
V
V
V
V
OL
4.5
3
0.1
0.44
0.44
1.65
24
4.5
5.5
75
(Note 6, 7)
50
5.5
-
-
-
-
-
1.65
V
(Note 6, 7)
2
CD74AC86, CD54/74ACT86
DC Electrical Specifications (Continued)
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
O
(V)
MIN
MAX
MIN
MAX
±1
MIN
MAX UNITS
I
Input Leakage Current
I
V
or
-
5.5
-
±0.1
-
-
±1
µA
I
CC
GND
Quiescent Supply Current,
FF
I
V
GND
or
0
5.5
-
4
-
40
-
80
µA
CC
CC
ACT TYPES
High Level Input Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
2
-
-
2
-
-
V
V
IH
Low Level Input Voltage
High Level Output Voltage
V
4.5 to
5.5
0.8
0.8
0.8
IL
V
V
V
or V
IH IL
-0.05
4.5
4.5
5.5
4.4
3.94
-
-
-
-
4.4
3.8
-
-
-
4.4
3.7
-
-
-
-
V
V
V
OH
-24
-75
3.85
(Note 6, 7)
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
Low Level Output Voltage
V
or V
IH IL
0.05
24
4.5
4.5
5.5
-
-
-
0.1
0.36
-
-
-
-
0.1
-
-
-
0.1
0.5
-
V
V
V
OL
0.44
1.65
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
80
3
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
0
-
±0.1
4
±1
40
2.8
µA
µA
mA
I
CC
GND
Quiescent Supply Current,
FF
I
V
GND
or
CC
CC
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
∆I
CC
V
4.5 to
5.5
2.4
CC
-2.1
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
o
o
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85 C, 75Ω at 125 C.
ACT Input Load Table
INPUT
UNIT LOAD
All
0.48
NOTE: Unit load is ∆I limit specified in DC Electrical Specifications
CC
o
Table, e.g., 2.4mA max at 25 C.
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case)
r
f
L
o
o
o
o
-40 C TO 85 C
TYP
-55 C TO 125 C
PARAMETER
AC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
TYP
MAX
UNITS
CC
Propagation Delay, Input to
Output
t
, t
1.5
3.3
-
-
-
123
-
-
-
135
ns
ns
PHL PLH
3.9
13.7
3.8
15.1
(Note 9)
5
2.8
-
9.8
2.7
-
10.8
ns
(Note 10)
3
CD74AC86, CD54/74ACT86
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case) (Continued)
r
f
L
o
o
o
o
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
Input Capacitance
SYMBOL
V
(V)
MIN
TYP
-
MAX
10
-
MIN
TYP
-
MAX
UNITS
pF
CC
C
-
-
-
-
-
10
-
I
Power Dissipation Capacitance
C
-
57
57
pF
PD
(Note 11)
ACT TYPES
Propagation Delay, Input to
Output
t
, t
5
3.8
-
13.3
3.7
-
14.6
ns
PHL PLH
(Note 10)
Input Capacitance
C
-
-
-
-
-
10
-
-
-
-
10
-
pF
pF
I
Power Dissipation Capacitance
C
57
57
PD
(Note 11)
NOTES:
8. Limits tested at 100%.
9. 3.3V Min at 3.6V, Max at 3V.
10. 5V Min at 5.5V, Max at 4.5V.
11. C
is used to determine the dynamic power consumption per gate.
PD
AC: P = V
2
f (C
+ C )
D
CC
i
PD
L
2
ACT: P = V
f (C
PD
+ C ) + V
∆I
CC CC
where f = input frequency, C = output load capacitance, V
= supply voltage.
CC
D
CC
i
L
i
L
OUTPUT
R
(NOTE)
L
500Ω
DUT
OUTPUT
LOAD
C
L
50pF
t = 3ns
t = 3ns
f
r
90%
V
10%
S
nA OR nB
NOTE: For AC Series Only: When V
= 1.5V, R = 1kΩ.
CC
L
AC
ACT
3V
t
t
PLH
PHL
Input Level
V
CC
V
S
OUTPUT nY
Input Switching Voltage, V
0.5 V
0.5 V
1.5V
S
CC
CC
Output Switching Voltage, V
0.5 V
CC
S
FIGURE 1.
FIGURE 2. PROPAGATION DELAY TIMES
4
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
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semiconductor products or services might be or are used. TI’s publication of information regarding any third
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Copyright 2000, Texas Instruments Incorporated
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