CD74ACT08MG4 [TI]
QUADRUPLE 2-INPUT POSITIVE-AND GATES;
| 型号： | CD74ACT08MG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE 2-INPUT POSITIVE-AND GATES 栅 输入元件 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总9页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54ACT08, CD74ACT08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCHS312B – JANUARY 2001 – REVISED JUNE 2002
CD54ACT08 . . . F PACKAGE
CD74ACT08 . . . E OR M PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
1A
1B
V
CC
Balanced Propagation Delays
Buffered Inputs
1
2
3
4
5
6
7
14
13
12
11
4B
4A
4Y
1Y
±24-mA Output Drive Current
– Fanout to 15 F Devices
2A
2B
10 3B
SCR-Latchup-Resistant CMOS Process and
Circuit Design
9
8
2Y
3A
3Y
GND
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description
The ’ACT08 devices are quadruple 2-input positive-AND gates. These devices perform the Boolean function
A • B or Y B in positive logic.
Y
A
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – E
Tube
Tube
CD74ACT08E
CD74ACT08E
CD74ACT08M
CD74ACT08M96
CD54ACT08F3A
–55°C to 125°C
SOIC – M
CDIP – F
ACT08M
Tape and reel
Tube
CD54ACT08F3A
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
B
H
X
L
H
L
H
L
L
X
logic diagram, each gate (positive logic)
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54ACT08, CD74ACT08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCHS312B – JANUARY 2001 – REVISED JUNE 2002
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
JA
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
–40°C TO
85°C
–55°C TO
125°C
T
A
= 25°C
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
MIN
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
4.5
2
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
0.8
V
0
0
V
V
0
0
V
V
0
0
V
V
V
I
CC
CC
CC
Output voltage
V
O
CC
CC
CC
I
I
High-level output current
Low-level output current
–24
24
–24
24
–24
24
mA
mA
ns/V
OH
OL
∆t/∆v Input transition rise or fall rate
10
10
10
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
–40°C TO
85°C
–55°C TO
125°C
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
CC
UNIT
MIN
4.4
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
I
I
I
I
= –50 µA
= –24 mA
= –50 mA
= –75 mA
= 50 µA
4.5 V
4.5 V
OH
OH
OH
OH
OL
OL
OL
OL
3.94
3.8
3.7
V
V
V = V or V
IH
V
OH
I
IL
IL
‡
‡
5.5 V
3.85
5.5 V
3.85
4.5 V
0.1
0.1
0.1
0.5
= 24 mA
4.5 V
0.36
0.44
V = V or V
V
OL
I
IH
‡
= 50 mA
= 75 mA
5.5 V
1.65
‡
5.5 V
1.65
±1
I
I
V = V
or GND
or GND,
– 2.1 V
5.5 V
±0.1
4
±1
80
3
µA
µA
mA
pF
I
I
CC
CC
CC
V = V
I
I
O
= 0
5.5 V
40
CC
∆I
CC
V = V
I
4.5 V to 5.5 V
2.4
10
2.8
10
C
10
i
‡
Testoneoutputatatime, notexceeding1-secondduration. Measurementismadebyforcingindicatedcurrentandmeasuringvoltagetominimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54ACT08, CD74ACT08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCHS312B – JANUARY 2001 – REVISED JUNE 2002
ACT INPUT LOAD TABLE
INPUT
A or B
UNIT LOAD
0.3
Unit load is ∆I
in electrical characteristics
limit specified
CC
table (e.g., 2.4 mA at 25°C).
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V, C = 50 pF (unless otherwise noted) (see Figure 1)
CC
L
–40°C TO
85°C
–55°C TO
125°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
3.3
MAX
MIN
3.2
MAX
t
t
11.7
11.7
12.9
12.9
PLH
A or B
Y
ns
3.3
3.2
PHL
operating characteristics, V
= 5 V, T = 25°C
CC
A
PARAMETER
TYP
UNIT
C
Power dissipation capacitance
50
pF
pd
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54ACT08, CD74ACT08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCHS312B – JANUARY 2001 – REVISED JUNE 2002
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
TEST
S1
S1
t
t
/t
Open
R1 = 500 Ω
R2 = 500 Ω
PLH PHL
From Output
Under Test
t
/t
2 × V
CC
GND
PLZ PZL
/t
PHZ PZH
C
= 50 pF
L
(see Note A)
t
w
3 V
0 V
1.5 V
1.5 V
Input
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATION
3 V
Reference
Input
3 V
0 V
1.5 V
CLR
Input
1.5 V
0 V
t
t
h
su
t
rec
3 V
0 V
Data
Input
90%
t
90%
3 V
0 V
1.5 V
10%
1.5 V
10%
1.5 V
CLK
t
r
f
VOLTAGE WAVEFORMS
RECOVERY TIME
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
3 V
0 V
3 V
Input
1.5 V
1.5 V
Output
Control
1.5 V
1.5 V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
OH
Output
Waveform 1
In-Phase
Output
90%
t
≈V
CC
50%
10%
50% V
10%
CC
V
20% V
20% V
CC
S1 at 2 × V
(see Note B)
CC
OL
CC
t
f
r
V
OL
t
t
PLH
PHL
90%
t
t
PHZ
PZH
V
V
OH
90%
Output
Waveform 2
S1 at GND
Out-of-Phase
Output
50% V
10%
50%
10%
CC
V
OH
80% V
80% V
CC
CC
OL
t
t
r
f
≈0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
Phase relationships between waveforms are arbitrary.
D. For clock inputs, f is measured with the input duty cycle at 50%.
max
E. The outputs are measured one at a time with one input transition per measurement.
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
.
pd
PLH
PZL
PLZ
PHL
PZH
PHZ
are the same as t
are the same as t
.
en
dis
.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
PDIP
Drawing
CD54ACT08F3A
CD74ACT08E
ACTIVE
ACTIVE
J
14
14
1
TBD
A42 SNPB
N / A for Pkg Type
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74ACT08EE4
CD74ACT08M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
N
D
D
D
D
14
14
14
14
14
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74ACT08M96
CD74ACT08M96E4
CD74ACT08ME4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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