CD74ACT251M [TI]
8-Input Multiplexer, Three-State; 8输入多路复用器，三态
| 型号： | CD74ACT251M |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-Input Multiplexer, Three-State |
| 文件： | 总8页 (文件大小：41K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74AC251,
CD74ACT251
Data sheet acquired from Harris Semiconductor
SCHS246
August 1998
8-Input Multiplexer, Three-State
Features
Description
• Buffered Inputs
The CD74AC251 and CD74ACT251 8-input multiplexers that
utilize the Harris Advanced CMOS Logic technology. This
multiplexer features both true (Y) and complement (Y) outputs
as well as an Output Enable (OE) input. The OE must be at a
LOW logic level to enable this device. When the OE input is
HIGH, both outputs are in the high-impedance state. When
enabled, address information on the data select inputs deter-
mines which data input is routed to the Y and Y outputs.
• Typical Propagation Delay
o
- 6ns at V
= 5V, T = 25 C, C = 50pF
A L
CC
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
Ordering Information
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
PART
NUMBER
TEMP.
RANGE ( C)
PKG.
NO.
o
PACKAGE
• Balanced Propagation Delays
o
CD74AC251E
CD74ACT251E
CD74AC251M
0 to 70 C, -40 to 85, 16 Ld PDIP
-55 to 125
E16.3
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
o
0 to 70 C, -40 to 85, 16 Ld PDIP
E16.3
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
-55 to 125
o
0 to 70 C, -40 to 85, 16 Ld SOIC
M16.15
M16.15
-55 to 125
- Drives 50Ω Transmission Lines
o
CD74ACT251M 0 to 70 C, -40 to 85, 16 Ld SOIC
-55 to 125
Pinout
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
CD74AC251, CD74ACT251
(PDIP, SOIC)
TOP VIEW
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or Harris
customer service for ordering information.
I
I
I
I
1
2
3
4
5
6
7
8
16 V
CC
3
2
1
0
15 I
14 I
13 I
12 I
4
5
6
7
Y
Y
11 S0
10 S1
OE
9
S2
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1998
File Number 1981.1
1
CD74AC251, CD74ACT251
Functional Diagram
THREE-STATE
DISABLE OE
7
4
I
I
I
I
I
I
I
I
0
1
2
3
4
5
6
7
3
2
1
15
14
13
12
CHANNEL
INPUTS
5
6
Y
Y
OUTPUTS
11
10
9
S
S
S
0
1
2
DATA
SELECT
TRUTH TABLE
INPUTS
OUTPUTS
SELECT
S2
X
L
S1
X
L
S0
X
L
OUTPUT ENABLE OE
Y
Y
H
L
L
L
L
L
L
L
L
Z
Z
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
H = High logic level, L = Low logic level, Z = High impedance (off),
X = Irrelevant, I , I ...I = The level of the respective input
0
1
7
2
CD74AC251, CD74ACT251
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V Thermal Resistance (Typical, Note 5)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
___
___
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
DC V
or Ground Current, I
I
(Note 3) . . . . . . . . .±100mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
(Note 4)
CC
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
25 C
o
o
85 C
125 C
V
CC
PARAMETER
AC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
MAX
MIN
MAX
MIN
MAX UNITS
O
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
-
-
-
1.5
3
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
V
V
V
V
V
V
V
V
V
V
V
V
IH
-
-
-
5.5
1.5
3
-
-
-
V
-
0.3
0.3
0.3
IL
-
0.9
-
0.9
-
0.9
5.5
1.5
3
-
1.65
-
1.65
-
1.65
V
V
or V
IH IL
-0.05
1.4
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
1.4
2.9
4.4
2.48
3.8
3.85
-
-
-
-
-
-
1.4
2.9
4.4
2.4
3.7
-
-
-
-
-
-
-
OH
-0.05
-0.05
-4
4.5
3
-24
4.5
5.5
-75
(Note 6, 7)
-50
5.5
-
-
-
-
3.85
-
V
(Note 6, 7)
3
CD74AC251, CD74ACT251
DC Electrical Specifications (Continued)
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
o
o
25 C
MIN
85 C
125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
(V)
1.5
3
MAX
0.1
0.1
0.1
0.36
0.36
-
MIN
MAX
MIN
MAX UNITS
I
O
Low Level Output Voltage
V
V
or V
IH IL
0.05
0.05
0.05
12
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.5
0.5
-
V
V
V
V
V
V
OL
4.5
3
0.1
0.44
0.44
1.65
24
4.5
5.5
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
±0.1
±0.5
±1
±5
µA
µA
I
CC
GND
Three-State Leakage
Current
I
V
V
or V
-
±10
OZ
IH
IL
= V
O
CC
or GND
Quiescent Supply Current
MSI
I
V
GND
or
0
5.5
-
8
-
80
-
160
µA
CC
CC
ACT TYPES
High Level Input Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
2
-
-
2
-
-
V
V
IH
Low Level Input Voltage
High Level Output Voltage
V
4.5 to
5.5
0.8
0.8
0.8
IL
V
V
V
or V
IH IL
-0.05
-24
4.5
4.5
5.5
4.4
3.94
-
-
-
-
4.4
3.8
-
-
-
4.4
3.7
-
-
-
-
V
V
V
OH
-75
(Note 6, 7)
3.85
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
Low Level Output Voltage
V
or V
IH IL
0.05
24
4.5
4.5
5.5
-
-
-
0.1
0.36
-
-
-
-
0.1
-
-
-
0.1
0.5
-
V
V
V
OL
0.44
1.65
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
±0.1
±0.5
±1
±5
µA
µA
I
CC
GND
Three-State or Leakage
Current
I
V
V
or V
-
±10
OZ
IH
IL
= V
O
CC
or GND
Quiescent Supply Current
MSI
I
V
or
0
-
5.5
-
-
8
-
-
80
-
-
160
3
µA
CC
CC
GND
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
∆I
V
4.5 to
5.5
2.4
2.8
mA
CC
CC
-2.1
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
o
o
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85 C, 75Ω at 125 C.
4
CD74AC251, CD74ACT251
ACT Input Load Table
INPUT
S0, S1, S3
OE
UNIT LOAD
1
1
1
I
- I
7
0
NOTE: Unit load is ∆I limit specified in DC Electrical Specifications
CC
o
Table, e.g., 2.4mA max at 25 C.
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case)
r
f
L
o
o
o
o
-40 C TO 85 C
TYP
-55 C TO 125 C
PARAMETER
AC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
TYP
MAX
UNITS
CC
Propagation Delay,
Data to Y Output
t
, t
PLH PHL
1.5
3.3
-
-
-
153
-
-
-
169
ns
ns
4.9
17.2
4.7
18.9
(Note 9)
5
3.5
-
12.3
3.4
-
13.5
ns
(Note 10)
Propagation Delay,
Data to Y Output
t
t
t
, t
1.5
3.3
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
169
19
-
-
-
-
-
-
-
-
-
-
-
-
-
-
186
20.9
14.9
228
25.5
18.2
245
27.4
19.6
169
20.3
13.5
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
PLH PHL
5.4
3.8
-
5.2
3.7
-
13.5
207
23.2
16.5
223
24.9
17.8
155
18.7
12.3
15
Propagation Delay,
Select to Y Output
, t
PLH PHL
1.5
3.3
5
6.6
4.7
-
6.4
4.6
-
Propagation Delay,
Select to Y Output
, t
PLH PHL
1.5
3.3
5
7.1
5.1
-
6.9
4.9
-
Propagation Delay,
Output Enable and Output
Disable to Output
t
, t
PZH PZL
,
1.5
3.3
5
t
, t
PHZ PLZ
5.2
3.5
-
5.1
3.4
-
Three-State Output
Capacitance
C
-
O
Input Capacitance
C
-
-
-
-
-
10
-
-
-
-
10
-
pF
pF
I
Power Dissipation Capacitance
C
120
120
PD
(Note 11)
ACT TYPES
Propagation Delay,
Data to Y Output
t
, t
PLH PHL
5
3.5
3.8
4.7
5.1
3.5
-
-
-
-
-
12.3
13.5
16.5
17.8
12.3
3.4
3.7
4.6
4.9
3.4
-
-
-
-
-
13.5
14.9
18.2
19.6
13.5
ns
ns
ns
ns
ns
(Note 10)
Propagation Delay,
Data to Y Output
t
t
t
, t
5
5
5
5
PLH PHL
Propagation Delay,
Select to Y Output
, t
PLH PHL
Propagation Delay,
Select to Y Output
, t
PLH PHL
Propagation Delay,
Output Enable and Output
Disable to Output
t
, t ,
PZH PZL
t
, t
PHZ PLZ
5
CD74AC251, CD74ACT251
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case) (Continued)
r
f
L
o
o
o
o
-40 C TO 85 C
TYP
-55 C TO 125 C
PARAMETER
Three-State Output
SYMBOL
V
(V)
MIN
MAX
MIN
TYP
MAX
UNITS
CC
C
O
Capacitance
Input Capacitance
C
-
-
-
-
-
10
-
-
-
-
10
-
pF
pF
I
Power Dissipation Capacitance
C
45
45
PD
(Note 11)
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. C
P
is used to determine the dynamic power consumption per device.
PD
= V
2
f (C
PD
+ C ) where f = input frequency, C = output load capacitance, V
= supply voltage.
D
CC
i
L
i
L
CC
t = 3ns
t = 3ns
f
r
INPUT LEVEL
90%
OUTPUT
DISABLE
V
S
10%
GND
t
t
t
t
PZL
PLZ
V
S
OUTPUT: LOW
TO OFF TO LOW
0.2V
CC
V
(≠ GND)
OL
PHZ
PZH
V
(≠ V
)
CC
OH
0.8 V
OUTPUT: HIGH
TO OFF TO HIGH
CC
V
S
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
GND (t
t
)
PHZ, PZH
OPEN (t
t
)
PHL, PLH
2 V
(t )
t
OTHER
CC PLZ, PZL
500Ω†
L
DUT
WITH
THREE-
STATE
OUTPUT
INPUTS
(TIED HIGH
OR LOW)
(OPEN DRAIN)
R
OUT
500Ω†
C
L
R
50pF
L
OUTPUT
DISABLE
†FOR AC SERIES ONLY: WHEN V
= 1.5V, R = 1kΩ
L
CC
FIGURE 1. THREE-STATE PROPAGATION DELAY WAVEFORMS AND TEST CIRCUIT
t = 3ns
t = 3ns
f
r
90%
S
10%
INPUT LEVEL
I
N
V
V
S
INVERTING
OUTPUT Y
t
t
PLH
PHL
NON-INVERTING
OUTPUT Y
V
S
t
PLH
t
PHL
FIGURE 2. PROPAGATION DELAY TIMES
6
CD74AC251, CD74ACT251
OUTPUT
R
(NOTE)
L
500Ω
DUT
OUTPUT
LOAD
C
L
50pF
NOTE: For AC Series Only: When V
Input Level
= 1.5V, R = 1kΩ.
CC
L
CD74AC
CD74ACT
3V
V
CC
Input Switching Voltage, V
0.5 V
0.5 V
1.5V
S
CC
CC
Output Switching Voltage, V
0.5 V
CC
S
FIGURE 3. PROPAGATION DELAY TIMES
7
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
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Copyright 1999, Texas Instruments Incorporated
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