CD74FCT373AT [TI]

FCT Interface Logic Octal Transparent Latch, Three-State; FCT接口逻辑八路透明锁存器，三态


型号：	CD74FCT373AT
厂家：	TEXAS INSTRUMENTS
描述：	FCT Interface Logic Octal Transparent Latch, Three-State FCT接口逻辑八路透明锁存器，三态锁存器
文件：	总2页 (文件大小：19K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CD54/74FCT373,

CD54/74FCT373AT,

Data sheet acquired from Harris Semiconductor

SCHS272

CD54/74FCT533

FCT Interface Logic

Octal Transparent Latch, Three-State

February 1996

Features

Description

• CD54/74FCT373, CD54/74FCT373AT - Non-Inverting

The CD54/74FCT373, 373AT, and 533 octal transparent

latches use a small-geometry BiCMOS technology. The output

stage is a combination of bipolar and CMOS transistors that

limits the output-HIGH level to two diode drops below VCC. This

resultant lowering of output swing (0V to 3.7V) reduces power

bus ringing (a source of EMI) and minimizes VCC bounce and

ground bounce and their effects during simultaneous output

switching. The output configuration also enhances switching

speed and is capable of sinking 32mA to 48mA.

• CD54/74FCT533 - Inverting

• Buffered inputs

• Typical Propagation Delay: 3.9ns at VCC = 5V,

TA = +25 C, CL = 50pF (FCT373AT)

• SCR-Latchup-Resistant BiCMOS Process and Circuit

Design

The CD54/74FCT373, 373AT, and 533 outputs are transpar-

ent to the inputs when the Latch Enable (LE) is HIGH. When

the Latch Enable (LE) goes LOW, the data is latched. The

Output Enable (OE) controls the three-state outputs. When

the Output Enable (OE) is HIGH, the outputs are in the high-

impedance state. The latch operation is independent of the

state of the Output Enable.

• FCTXXX Types - Speed of Bipolar FAST®/AS/S;

FCTXXXAT Types - 30% Faster than FAST/AS/S with

Signiﬁcantly Reduced Power Consumption

• 48mA to 32mA Output Sink Current (Commercial/

Extended Industrial)

• Output Voltage Swing Limited to 3.7V at VCC = 5V

• Controlled Output-Edge Rates

Ordering Information

PART NUMBER

CD54/74FCT373E

CD54/74FCT373ATE

CD54/74FCT533E

CD54/74FCT373M

CD54/74FCT373ATM

CD54/74FCT533M

CD54/74FCT373SM

CD54/74FCT533SM

CD54FCT373H

TEMP. RANGE ( C)

PACKAGE

• Input/Output Isolation to VCC

-55 to 125, 0 to 70 20 Ld PDIP

-55 to 125, 0 to 70 20 Ld SOIC

-55 to 125, 0 to 70 20 Ld SSOP

-55 to 125

• BiCMOS Technology with Low Quiescent Power

CD54FCT533H

-55 to 125

Functional Diagram

TRUTH TABLE

373

533

OUTPUT

ENABLE

LATCH

ENABLE

373,373AT

OUTPUT

533

OUTPUT

DATA

H = HIGH voltage level.

L = LOW voltage level.

X = Irrelevant.

I = LOW voltage level one setup time

prior to the high-to-low latch enable

transition.

Z = HIGH Impedance.

h = HIGH voltage level one setup time

prior to the high-to-low latch enable

transition.

FAST® is a registered trademark of Fairchild Semiconductor Corporation.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 2230.2

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

相关型号：