CD74FCT543M96 [TI]
BiCMOS FCT Interface Logic Octal Non-Inverting Registers/Transceivers with 3-State Outputs 24-SOIC 0 to 70;
| 型号： | CD74FCT543M96 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | BiCMOS FCT Interface Logic Octal Non-Inverting Registers/Transceivers with 3-State Outputs 24-SOIC 0 to 70 |
| 文件： | 总11页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74FCT543
BiCMOS OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS742 – JULY 2000
EN, M, OR SM PACKAGE
(TOP VIEW)
BiCMOS Technology With Low Quiescent
Power
Buffered Inputs
Inverted Outputs
LEBA
OEBA
A1
1
2
3
4
5
6
7
8
9
24
V
CC
23 CEBA
22 B1
Input/Output Isolation From V
CC
A2
A3
A4
A5
A6
A7
21 B2
Controlled Output Edge Rates
64-mA Output Sink Current
20 B3
19 B4
Output Voltage Swing Limited to 3.7 V
18 B5
17 B6
SCR Latch-Up-Resistant BiCMOS Process
and Circuit Design
16 B7
A8 10
CEAB 11
GND 12
15 B8
14 LEAB
13 OEAB
Package Options Include Plastic
Small-Outline (M) and Shrink Small-Outline
(SM) Packages and Standard Plastic (EN)
DIP
description
The CD74FCT543 is an octal register/transceiver with 3-state outputs that uses a small-geometry BiCMOS
technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level
to two diode drops below V . This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing
CC
[a source of electromagnetic interference (EMI)] and minimizes V
bounce and ground bounce and their
CC
effects during simultaneous output switching. The output configuration also enhances switching speed and is
capable of sinking 64 mA.
This device contains two sets of eight D-type latches with separate input and output controls for each set. For
data flow from A to B, for example, the A-to-B enable (CEAB) input must be low to enter data from A1 to A8 or
to take data from B1 to B8. When CEAB is low, a low signal on the A-to-B latch enable (LEAB) input makes the
A-to-B latches transparent; a subsequent low-to-high transition of the LEAB signal puts the A latches in the
storage mode and their outputs no longer change with the A inputs. With CEABandOEAB both low, the B output
buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar,
but uses the CEBA, LEBA, and OEBA inputs.
The CD74FCT543 contains two sets of D-type latches for temporary storage of data flowing in either direction.
Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each
register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches
inthestoragemode. WithCEABandOEABbothlow, the3-stateBoutputsareactiveandreflectthedatapresent
at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA
inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The CD74FCT543 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD74FCT543
BiCMOS OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS742 – JULY 2000
†
FUNCTION TABLE
INPUTS
LATCH
OUTPUT
B
STATUS
CEAB
LEAB
OEAB
A
X
X
X
L
H
X
L
L
L
X
X
H
L
X
H
L
Storing
–
Z
Z
‡
B
0
Storing
L
Transparent
Transparent
L
L
L
H
H
†
‡
A-to-Bdataflowisshown;B-to-Aflowcontrolisthesameexceptthat
it uses CEBA, LEBA, and OEBA.
Output level before the indicated steady-state input conditions were
established
§
logic symbol
2
1EN3
G1
OEBA
CEBA
LEBA
OEAB
CEAB
LEAB
23
1
1C5
2EN4
G2
13
11
14
2C6
3
22
A1
5D
4
B1
3
1
1
6D
21
20
19
4
B2
B3
B4
A2
5
6
7
A3
A4
A5
18
17
16
B5
B6
B7
8
A6
9
A7
A8
15
10
B8
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD74FCT543
BiCMOS OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS742 – JULY 2000
logic diagram (positive logic)
2
OEBA
23
CEBA
1
LEBA
13
OEAB
11
CEAB
14
LEAB
C1
1D
3
A1
22
B1
C1
1D
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
DC supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
CC
I
DC input clamp current, I (V < –0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
DC output clamp current, I
(V < –0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
DC output sink current per output pin, I
DC output source current per output pin, I
Continuous current through V , I
Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
OL
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA
OH
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 mA
CC CC
Package thermal impedance, θ (see Note 1): EN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
JA
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
SM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD74FCT543
BiCMOS OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS742 – JULY 2000
recommended operating conditions (see Note 2)
MIN
4.75
2
MAX
UNIT
V
V
V
V
V
V
Supply voltage
5.25
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
V
0.8
V
0
0
V
V
V
I
CC
Output voltage
V
O
CC
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–15
64
mA
mA
ns/V
°C
OH
OL
I
∆t/∆v
0
0
10
T
70
A
NOTE 2: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
A
PARAMETER
TEST CONDITIONS
V
CC
MIN
MAX
UNIT
MIN
MAX
V
V
V
I = –18 mA
4.75 V
4.75 V
4.75 V
5.25 V
5.25 V
5.25 V
5.25 V
–1.2
–1.2
V
V
IK
I
I
I
= –15 mA
= 64 mA
2.4
2.4
OH
OL
OH
OL
0.55
±0.1
±0.5
0.55
±1
V
I
I
I
I
V = V
I
or GND
A
I
CC
V
O
= V or GND
CC
±10
A
OZ
OS
CC
†
V = V
or GND,
or GND,
V = 0
O
–60
–60
mA
A
I
CC
CC
V = V
I
I
O
= 0
8
80
One input at 3.4 V,
Other inputs at V
‡
5.25 V
1.6
1.6
mA
∆I
CC
or GND
CC
or GND
C
C
V = V
10
15
10
15
pF
pF
i
I
CC
= V or GND
CC
V
o
O
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 100 ms.
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or V
.
CC
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
MIN
9
MAX
UNIT
t
Pulse duration
Setup time
LEAB or LEBA low
ns
w
Data high
Data low
Data high
Data low
3
A or B before LEAB or LEBA↑
3
t
su
ns
ns
3
A or B before CEAB or CEBA↑
3
A or B after LEAB or LEBA↑
A or B after CEAB or CEBA↑
2
t
h
Hold time
2
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD74FCT543
BiCMOS OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS742 – JULY 2000
switching characteristics over recommended operating conditions (unless otherwise noted) (see
Figure 1)
T
A
= 25°C
TYP
6.4
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
A or B
2.5
2.5
2
8.5
12.5
12
B or A
A or B
A or B
A or B
t
pd
ns
LEBA or LEAB
LEBA or LEAB
LEBA or LEAB
9.4
t
t
9
ns
ns
en
6.8
2
9
dis
noise characteristics, V
= 5 V, C = 50 pF, T = 25°C
CC
L
A
PARAMETER
MIN
TYP
1
MAX
UNIT
V
V
V
V
Quiet output, maximum dynamic V
V
V
V
V
OL(P)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
0.5
OH
2
0.8
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
No load, f = 1 MHz
TYP
UNIT
C
Power dissipation capacitance
49
pF
pd
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD74FCT543
BiCMOS OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS742 – JULY 2000
PARAMETER MEASUREMENT INFORMATION
7 V
Open
GND
S1
500 Ω
TEST
/t
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
Open
7 V
PLH PHL
t
/t
PLZ PZL
C
= 50 pF
C
= 50 pF
L
L
500 Ω
500 Ω
t
/t
Open
7 V
(see Note A)
PHZ PZH
(see Note A)
Open Drain
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
90%
90%
1.5 V
10%
1.5 V
10%
0 V
t
t
f
r
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
3 V
1.5 V
Timing Input
0 V
t
w
t
h
t
3 V
0 V
su
3 V
0 V
1.5 V
1.5 V
Input
Input
1.5 V
1.5 V
Data Input
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
t
t
t
t
t
t
PLZ
PLH
PHL
PZL
PZH
≈3.5 V
V
Output
Waveform 1
(see Note B)
OH
In-Phase
Output
1.5 V
1.5 V
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
OL
V
OL
t
t
PHL
PLH
PHZ
V
V
V
OH
OH
Output
Waveform 2
(see Note B)
– 0.3 V
Out-of-Phase
Output
OH
1.5 V
1.5 V
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t and t = 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PHL
PHZ
PZH
PLH
.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
PDIP
SOIC
SOIC
SSOP
Drawing
CD74FCT543EN
CD74FCT543M
CD74FCT543M96
CD74FCT543SM
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
NT
24
24
24
24
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
DW
DW
DB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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