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CD74FCT543_14 [TI]

BiCMOS OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS;
CD74FCT543_14
型号： CD74FCT543_14
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

BiCMOS OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

输出元件
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CD74FCT543  
Data sheet acquired from Harris Semiconductor  
SCHS258  
BiCMOS FCT Interface Logic,  
Octal Register/Transceiver, Three-State  
January 1997  
Circuit Design  
Features  
- Speed of Bipolar FAST™/AS/S  
- 64mA Output Sink Current  
• Buffered Inputs  
• Typical Propagation Delay: 6.4ns at V  
o
= 5V,  
CC  
- Output Voltage Swing Limited to 3.7V at V  
- Controlled Output Edge Rates  
= 5V  
CC  
T = 25 C, C = 50pF  
A
L
• Noninverting  
- Input/Output Isolation to V  
CC  
- BiCMOS Technology with Low Quiescent Power  
• Family Features  
- SCR Latchup Resistant BiCMOS Process and  
Ordering Information  
TEMP.  
RANGE ( C)  
0 to 70  
PKG.  
NO.  
E24.3  
o
PART NUMBER  
CD74FCT543EN  
CD74FCT543M  
PACKAGE  
24 Ld PDIP  
24 Ld SOIC  
24 Ld SSOP  
0 to 70  
M24.3  
CD74FCT543SM  
0 to 70  
M24.209  
NOTE: When ordering the suffix M and SM packages, use the entire  
part number. Add the suffix 96 to obtain the variant in the tape and reel.  
Pinout  
CD74FCT543  
(PDIP, SOIC, SSOP)  
TOP VIEW  
LEBA  
OEBA  
A0  
1
24  
VCC  
2
3
23 CEBA  
22 B0  
B1  
21  
A1  
4
A2  
5
20 B2  
A3  
6
19 B3  
A4  
18 B4  
7
A5  
17 B5  
8
A6  
16 B6  
9
A7  
10  
11  
15 B7  
CEAB  
14 LEAB  
13 OEAB  
GND 12  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
FAST™ is a trademark of Fairchild Semiconductor.  
Copyright © Harris Corporation 1997  
File Number 2399.2  
8-1  
CD74FCT543  
Functional Diagram  
DETAIL A  
D
Q
B0  
LE  
D
LE  
A0  
A1  
Q
B1  
B7  
DETAIL A x 7  
A7  
OEBA  
OEAB  
CEBA  
LEBA  
CEAB  
LEAB  
TRUTH TABLE For A to B (Symmetric with B to A)  
INPUTS  
LEAB  
LATCH STATUS  
OUTPUT BUFFERS  
CEAB  
OEAB  
A TO B  
Storing  
Storing  
-
B0 THRU B7  
H
X
X
L
X
H
-
X
−
H
L
High Z  
-
High Z  
L
H
Transparent  
Storing  
Current A Inputs  
Previous A Inputs (Note 1)  
L
L
NOTE:  
1. Before LEAB LOW to HIGH Transition  
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
A to B data flow shown; B to A flow control is the same, except using CEBA, LEBA, and OEBA.  
IEC Logic Symbol  
CD74FCT543  
≥1  
11  
EN1  
14  
13  
≥1  
23  
1
EN2  
2
2
3
4
5
6
7
8
9
10  
22  
21  
20  
19  
18  
17  
16  
15  
1
8-2  
CD74FCT543  
Absolute Maximum Ratings  
Thermal Information  
o
DC Supply Voltage (V ). . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V  
CC  
Thermal Resistance (Typical, Note 2)  
θ
( C/W)  
JA  
DC Input Diode Current, I (For V < -0.5V) . . . . . . . . . . . . . -20mA  
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75  
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75  
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125  
IK  
I
DC Output Diode Current, I  
(for V < -0.5V) . . . . . . . . . . . -50mA  
OK  
O
DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . .70mA  
o
DC Output Source Current per Output Pin, IO . . . . . . . . . . . . -30mA  
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C  
o
o
DC V  
CC  
Current (I ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140mA Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
CC  
o
DC Ground Current (I  
). . . . . . . . . . . . . . . . . . . . . . . . . . .528mA  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
GND  
(SOIC and SSOP-Lead Tips Only)  
Operating Conditions  
o
o
Operating Temperature Range (T ) . . . . . . . . . . . . . . . .0 C to 70 C  
A
Supply Voltage Range, V . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V  
CC  
DC Input Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V  
I
CC  
CC  
DC Output Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ V  
O
Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
2. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
o
o
Electrical Specifications Commercial Temperature Range 0 C to 70 C, V  
Max = 5.25V, V Min = 4.75V  
CC  
CC  
AMBIENT TEMPERATURE (T )  
A
o
o
o
TEST CONDITIONS  
25 C  
0 C TO 70 C  
PARAMETER  
SYMBOL  
V (V)  
I
(mA)  
V (V)  
CC  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
High Level Input Voltage  
V
4.75 to  
5.25  
2
-
2
-
V
IH  
Low Level Input Voltage  
V
4.75 to  
5.25  
-
0.8  
-
0.8  
V
IL  
High Level Output Voltage  
Low Level Output Voltage  
High Level Input Current  
Low Level Input Current  
Three-State Leakage Current  
V
V
V
or V  
or V  
-15  
64  
Min  
Min  
2.4  
-
2.4  
-
V
V
OH  
IH  
IH  
IL  
V
-
-
-
-
-
-
0.55  
0.1  
-
-
-
-
-
-
0.55  
1
OL  
IL  
I
V
Max  
Max  
Max  
Max  
Min  
µA  
µA  
µA  
µA  
V
IH  
CC  
I
GND  
-0.1  
0.5  
-1  
IL  
I
V
10  
OZH  
CC  
I
GND  
-0.5  
-1.2  
-10  
-1.2  
OZL  
Input Clamp Voltage  
V
V
or  
-18  
IK  
CC  
GND  
Short Circuit Output Current  
(Note 3)  
I
V
= 0  
or  
Max  
-60  
-
-60  
-
mA  
OS  
O
V
CC  
GND  
Quiescent Supply Current,  
MSI  
I
V
GND  
or  
0
Max  
Max  
-
-
8
-
-
80  
µA  
CC  
CC  
Additional Quiescent Supply  
Current per Input Pin  
∆I  
CC  
3.4V  
(Note 4)  
1.6  
1.6  
mA  
TTL Inputs High, 1 Unit Load  
NOTES:  
3. Not more than one output should be shorted at one time. Test duration should not exceed 100ms.  
4. Inputs that are not measured are at V or GND.  
CC  
5. FCT Input Loading: All inputs are 1 unit load. Unit load is ∆I  
o
limit specified in Electrical Specifications table, e.g., 1.6mA Max. at 70 C.  
CC  
8-3  
CD74FCT543  
Switching Specifications Over Operating Range FCT Series t , t = 2.5ns, C = 50pF, R (Figure 4)  
r
f
L
L
o
o
o
25 C  
TYP  
0 C TO 70 C  
TYP  
PARAMETER  
SYMBOL  
V
(V)  
MIN  
MAX  
UNITS  
CC  
Propagation Delays  
An ↔ Bn  
t
, t  
PLH PHL  
5
5
5
5
-
6.4  
9.4  
6.8  
9
2.5  
2.5  
2
-
-
8.5  
12.5  
9
ns  
ns  
ns  
ns  
pF  
LEBA to An or LEAB to Bn  
CEBA or CEAB to An or Bn  
t , t  
PLH PHL  
t
, t  
PLZ PHZ  
-
t
, t  
PZL PZH  
2
-
12  
-
Power Dissipation Capacitance  
C
49  
-
49  
PD  
(Note 6)  
Minimum (Valley) V  
OHV  
Other Outputs (Output Under Test Not Switching)  
During Switching of  
V
5
5
0.5  
1
-
-
-
-
-
-
V
V
OHV  
Maximum (Peak) V During Switching of  
V
OLP  
OLP  
Other Outputs (Output Under Test Not Switching)  
Input Capacitance  
C
-
-
-
-
-
-
-
-
10  
15  
pF  
pF  
I
Input/Output Capacitance  
NOTE:  
C
I/O  
6. C , measured per flip-flop, is used to determine the dynamic power consumption.  
PD  
2
2
P
(per package) = V  
I
+ Σ(V  
f C  
+ V  
f
C + V D) where:  
∆I  
D
CC CC  
= supply voltage  
CC  
I
PD  
O
O
L
CC CC  
V
∆I  
CC  
CC  
= flow through current x unit load  
= output load capacitance  
C
L
D = duty cycle of input high  
f
= output frequency  
O
f = input frequency  
I
Prerequisite for Switching  
o
o
o
25 C  
0 C TO 70 C  
MIN MAX  
PARAMETER  
SYMBOL  
V
(V)  
TYP  
UNITS  
CC  
Data to Latch Enable Setup Time  
t
5
-
3
-
ns  
SU  
(Note 7)  
Data to Latch Enable Hold Time  
Latch Enable Pulse Width  
t
5
5
-
-
2
9
-
-
ns  
ns  
H
t
W
NOTE:  
7. 5V: Minimum is at 4.75V for 0 C to 70 C, Typical is at 5V.  
o
o
8-4  
CD74FCT543  
Test Circuits and Waveforms  
V
CC  
SWITCH POSITION  
t , t = 2.5ns  
r
f
7V  
TEST  
, Open Drain  
SWITCH  
Closed  
Open  
V
3V  
0
I
(NOTE 8)  
500Ω  
V
0
t
, t  
PLZ PZL  
R
L
PULSE Z  
GEN  
O
DUT  
t
, t  
, t  
, t  
PHZ PZH PLH PHL  
C
L
500Ω  
R
T
R
DEFINITIONS:  
50pF  
L
R
= Z  
T
O
C
= Load capacitance, includes jig and probe  
capacitance.  
L
R = Termination resistance, should be equal to Z  
of  
NOTE:  
8. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; Z  
T
OUT  
the Pulse Generator.  
≤ 50Ω;  
OUT  
V
= 0V to 3V.  
IN  
Input: t = t = 2.5ns (10% to 90%), unless otherwise specified  
t , t ≤ 2.5ns.  
f
r
r
f
FIGURE 1. TEST CIRCUIT  
3V  
1.5V  
0V  
DATA  
INPUT  
t
SH  
t
H
3V  
1.5V  
0V  
TIMING  
INPUT  
t
REM  
ASYNCHRONOUS CONTROL  
3V  
1.5V  
0V  
LOW-HIGH-LOW  
PULSE  
1.5V  
1.5V  
t
SYNCHRONOUS CONTROL  
W
PRESET CLEAR  
CLOCK ENABLE  
ETC.  
3V  
1.5V  
0V  
HIGH-LOW-HIGH  
PULSE  
t
SH  
t
H
FIGURE 2. SETUP, HOLD, AND RELEASE TIMING  
FIGURE 3. PULSE WIDTH  
ENABLE  
DISABLE  
3V  
3V  
SAME PHASE  
INPUT TRANSITION  
1.5V  
0V  
CONTROL INPUT  
1.5V  
0V  
t
t
PHL  
PLH  
t
t
PLZ  
PZL  
3.5V  
1.5V  
3.5V  
V
OH  
SWITCH  
CLOSED  
OUTPUT  
NORMALLY LOW  
1.5V  
OUTPUT  
0.3V  
0.3V  
V
V
OL  
OL  
t
t
PHL  
t
t
PLH  
PZH  
PHZ  
V
OH  
3V  
OUTPUT  
NORMALLY HIGH  
SWITCH  
OPEN  
OPPOSITE PHASE  
INPUT TRANSITION  
1.5V  
0V  
1.5V  
0V  
0V  
FIGURE 4. ENABLE AND DISABLE TIMING  
FIGURE 5. PROPAGATION DELAY  
V
OH  
OTHER  
OUTPUTS  
V
OL  
V
OH  
OUTPUT  
UNDER  
TEST  
V
OHV  
V
OLP  
V
OL  
NOTES:  
9. V  
is measured with respect to a ground reference near the output under test. V  
OHV  
is measured with respect to V .  
OH  
OLP  
10. Input pulses have the following characteristics:  
≤ 1MHz, t = 2.5ns, t = 2.5ns, skew 1ns.  
P
RR  
r
f
11. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1µF capacitor. Scope and  
probes require 700MHz bandwidth.  
FIGURE 6. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS  
8-5  
IMPORTANT NOTICE  
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue  
any product or service without notice, and advise customers to obtain the latest version of relevant information  
to verify, before placing orders, that information being relied on is current and complete. All products are sold  
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those  
pertaining to warranty, patent infringement, and limitation of liability.  
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent  
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily  
performed, except those mandated by government requirements.  
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF  
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL  
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR  
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER  
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO  
BE FULLY AT THE CUSTOMER’S RISK.  
In order to minimize risks associated with the customer’s applications, adequate design and operating  
safeguards must be provided by the customer to minimize inherent or procedural hazards.  
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent  
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other  
intellectual property right of TI covering or relating to any combination, machine, or process in which such  
semiconductor products or services might be or are used. TI’s publication of information regarding any third  
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.  
Copyright 1998, Texas Instruments Incorporated  

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