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CD74HC08PWRE4 [TI]

HC/UH SERIES, QUAD 2-INPUT AND GATE, PDSO14, GREEN, PLASTIC. TSSOP-14;
CD74HC08PWRE4
型号： CD74HC08PWRE4
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

HC/UH SERIES, QUAD 2-INPUT AND GATE, PDSO14, GREEN, PLASTIC. TSSOP-14

栅 输入元件 光电二极管 逻辑集成电路 触发器
文件： 总18页 (文件大小：691K)
中文：  中文翻译
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CD54HC08, CD74HC08,  
CD54HCT08, CD74HCT08  
Data sheet acquired from Harris Semiconductor  
SCHS118C  
High-Speed CMOS Logic  
Quad 2-Input AND Gate  
August 1997 - Revised July 2004  
Features  
Description  
• Buffered Inputs  
The  
CD54HC08,  
CD54HCT08,  
CD74HC08,  
and  
CD74HCT08 logic gates utilize silicon gate CMOS  
technology to achieve operating speeds similar to LSTTL  
gates with the low power consumption of standard CMOS  
integrated circuits. All devices have the ability to drive 10  
LSTTL loads. The 74HCT logic family is functionally pin  
compatible with the standard 74LS logic family.  
• Typical Propagation Delay: 7ns at V  
o
= 5V,  
[ /Title  
(CD54H  
C08,  
CD54H  
CT08,  
CD74H  
C08,  
CD74H  
CT08)  
/Sub-  
CC  
C = 15pF, T = 25 C  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
TEMP. RANGE  
o
PART NUMBER  
CD54HC08F3A  
CD54HCT08F3A  
CD74HC08E  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld CERDIP  
14 Ld PDIP  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• HC Types  
ject  
(High  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
CD74HC08M  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld TSSOP  
14 Ld TSSOP  
14 Ld PDIP  
• HCT Types  
CD74HC08MT  
CD74HC08M96  
CD74HC08PW  
CD74HC08PWR  
CD74HCT08E  
CD74HCT08M  
CD74HCT08MT  
CD74HCT08M96  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
• CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel  
of 250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2004, Texas Instruments Incorporated  
1
CD54HC08, CD74HC08, CD54HCT08, CD74HCT08  
Pinout  
CD54HC08, CD54HCT08,  
(CERDIP)  
CD74HC08  
(PDIP, SOIC, TSSOP)  
CD74HCT08  
(PDIP, SOIC)  
TOP VIEW  
1A  
1B  
1
2
3
4
5
6
7
14 V  
CC  
13 4B  
12 4A  
11 4Y  
10 3B  
1Y  
2A  
2B  
2Y  
9
8
3A  
3Y  
GND  
Functional Diagram  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
V
1A  
1B  
1Y  
2A  
2B  
2Y  
CC  
4B  
4A  
4Y  
3B  
3A  
3Y  
8
GND  
TRUTH TABLE  
INPUTS  
OUTPUT  
nA  
L
nB  
L
nY  
L
L
H
L
L
H
H
L
H
H
H = High Voltage Level, L = Low Voltage Level  
2
CD54HC08, CD74HC08, CD54HCT08, CD74HCT08  
HCT Logic Symbol  
HC Logic Symbol  
nA  
nA  
nB  
nY  
nY  
nB  
3
CD54HC08, CD74HC08, CD54HCT08, CD74HCT08  
Absolute Maximum Ratings  
Thermal Information  
o
DC Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
Thermal Resistance (Typical, Note 1)  
θ
( C/W)  
JA  
CC  
DC Input Diode Current, I  
For V < -0.5V or V > V  
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80  
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86  
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113  
Maximum Junction Temperature (Hermetic Package or Die) . . . 175 C  
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C  
IK  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
OK  
For V < -0.5V or V > V  
I
I
CC  
DC Output Diode Current, I  
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
O
O
CC  
o
DC Output Source or Sink Current per Output Pin, I  
O
o
o
For V > -0.5V or V < V  
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
O
O
CC  
o
DC V  
or Ground Current, I  
I
. . . . . . . . . . . . . . . . . .±50mA  
CC  
CC or GND  
(SOIC - Lead Tips Only)  
Operating Conditions  
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range, V  
CC  
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
I
O
CC  
Input Rise and Fall Time  
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)  
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)  
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. The package thermal impedance is calculated in accordance with JESD 51-7.  
DC Electrical Specifications  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
PARAMETER  
HC TYPES  
SYMBOL V (V)  
I
(mA)  
V
(V) MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
High Level Input  
Voltage  
V
-
-
-
2
1.5  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5  
-
1.5  
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA  
IH  
4.5  
3.15  
-
-
3.15  
-
-
3.15  
6
2
4.2  
4.2  
4.2  
-
Low Level Input  
Voltage  
V
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
IL  
4.5  
6
-
-
-
-
-
-
High Level Output  
Voltage  
CMOS Loads  
V
V
or  
-0.02  
2
1.9  
1.9  
1.9  
OH  
IH  
V
IL  
-0.02  
-0.02  
-
4.5  
6
4.4  
-
4.4  
-
4.4  
-
5.9  
-
5.9  
-
5.9  
-
High Level Output  
Voltage  
TTL Loads  
-
-
-
-
-
-
-
-4  
4.5  
6
3.98  
-
3.84  
-
3.7  
-
-5.2  
0.02  
0.02  
0.02  
-
5.48  
-
5.34  
-
5.2  
-
Low Level Output  
Voltage  
CMOS Loads  
V
V
or  
2
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
OL  
IH  
V
IL  
4.5  
6
Low Level Output  
Voltage  
TTL Loads  
-
4
4.5  
6
0.26  
0.26  
±0.1  
0.33  
0.33  
±1  
0.4  
0.4  
±1  
5.2  
-
Input Leakage  
Current  
I
V
or  
6
I
CC  
GND  
4
CD54HC08, CD74HC08, CD54HCT08, CD74HCT08  
DC Electrical Specifications (Continued)  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
PARAMETER  
SYMBOL V (V)  
I
(mA)  
V
(V) MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
Quiescent Device  
Current  
I
V
GND  
or  
0
6
-
-
2
-
20  
-
40  
µA  
CC  
CC  
HCT TYPES  
High Level Input  
Voltage  
V
-
-
-
-
4.5 to  
5.5  
2
-
-
-
-
-
0.8  
-
2
-
-
0.8  
-
2
-
-
0.8  
-
V
V
V
IH  
Low Level Input  
Voltage  
V
4.5 to  
5.5  
IL  
High Level Output  
Voltage  
CMOS Loads  
V
V
or  
IH  
-0.02  
4.5  
4.5  
4.5  
4.5  
5.5  
5.5  
4.4  
4.4  
4.4  
OH  
V
IL  
High Level Output  
Voltage  
TTL Loads  
-4  
3.98  
-
-
-
-
3.84  
-
3.7  
-
V
V
Low Level Output  
Voltage  
CMOS Loads  
V
V
or  
IH  
0.02  
4
-
-
-
0.1  
-
-
-
0.1  
0.33  
±1  
-
-
-
0.1  
0.4  
±1  
OL  
V
IL  
Low Level Output  
Voltage  
TTL Loads  
0.26  
±0.1  
V
Input Leakage  
Current  
I
V
0
µA  
I
CC  
and  
GND  
Quiescent Device  
Current  
I
V
or  
0
-
-
-
-
2
-
-
20  
-
-
40  
µA  
µA  
CC  
CC  
GND  
Additional Quiescent  
Device Current Per  
Input Pin: 1 Unit Load  
∆I  
CC  
(Note 2)  
V
4.5 to  
5.5  
100  
360  
450  
490  
CC  
- 2.1  
NOTE:  
2. For dual-supply systems theoretical worst case (V = 2.4V, V  
I
= 5.5V) specification is 1.8mA.  
CC  
HCT Input Loading Table  
INPUT  
All  
UNIT LOADS  
0.6  
NOTE: Unit Load is ∆I  
Specifications table, e.g. 360µA max at 25 C.  
limit specified in DC Electrical  
o
CC  
Switching Specifications Input t , t = 6ns  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
Propagation Delay,  
Input to Output (Figure 1)  
t
, t  
PLH PHL  
C = 50pF  
2
4.5  
6
-
-
-
-
-
-
90  
18  
15  
-
-
-
-
-
115  
23  
20  
-
-
-
-
-
135  
27  
23  
-
ns  
ns  
ns  
ns  
L
-
Propagation Delay, Data Input to  
Output Y  
t , t  
PLH PHL  
C = 15pF  
5
7
L
5
Switching Specifications Input t , t = 6ns (Continued)  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
95  
19  
16  
10  
-
MIN  
MAX  
110  
22  
UNITS  
ns  
Transition Times (Figure 1)  
t
, t  
TLH THL  
C = 50pF  
L
2
4.5  
6
-
-
-
-
-
-
-
75  
15  
13  
10  
-
-
-
-
-
-
-
-
-
-
-
ns  
-
19  
ns  
Input Capacitance  
C
-
-
-
-
10  
pF  
I
Power Dissipation Capacitance  
(Notes 3, 4)  
C
5
37  
-
pF  
PD  
HCT TYPES  
Propagation Delay, Input to  
Output Y (Figure 2)  
t
, t  
PLH PHL  
C = 50pF  
4.5  
5
-
-
-
25  
-
-
-
31  
-
-
-
38  
-
ns  
ns  
L
Propagation Delay, Data Input to  
Output Y  
t , t  
PLH PHL  
C = 15pF  
10  
L
Transition Times (Figure 2)  
Input Capacitance  
t
, t  
TLH THL  
C = 50pF  
4.5  
-
-
-
-
-
-
15  
10  
-
-
-
-
19  
10  
-
-
-
-
22  
10  
-
ns  
pF  
pF  
L
C
C = 50pF  
L
I
Power Dissipation Capacitance  
(Notes 3, 4)  
C
-
5
51  
PD  
NOTES:  
3. C  
is used to determine the dynamic power consumption, per gate.  
2
PD  
4. P = V  
f (C  
PD  
+ C ) where f = input frequency, C = output load capacitance, V = supply voltage.  
CC  
D
CC  
i
L
i
L
Test Circuits and Waveforms  
t = 6ns  
f
t = 6ns  
t = 6ns  
t = 6ns  
r
r
f
V
3V  
CC  
90%  
50%  
10%  
2.7V  
1.3V  
0.3V  
INPUT  
INPUT  
GND  
GND  
t
t
t
t
THL  
TLH  
THL  
TLH  
90%  
1.3V  
90%  
50%  
10%  
INVERTING  
OUTPUT  
INVERTING  
OUTPUT  
10%  
t
t
PLH  
PHL  
t
t
PLH  
PHL  
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-  
TION DELAY TIMES, COMBINATION LOGIC  
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
6
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Jun-2014  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(6)  
(3)  
(4/5)  
5962-8688301CA  
ACTIVE  
CDIP  
J
14  
1
TBD  
A42  
N / A for Pkg Type  
-55 to 125  
5962-8688301CA  
CD54HCT08F3A  
CD54HC08F  
ACTIVE  
ACTIVE  
CDIP  
CDIP  
J
J
14  
14  
1
1
TBD  
TBD  
A42  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
-55 to 125  
-55 to 125  
CD54HC08F  
CD54HC08F3A  
8404701CA  
CD54HC08F3A  
CD54HCT08F  
ACTIVE  
ACTIVE  
CDIP  
CDIP  
J
J
14  
14  
1
1
TBD  
TBD  
A42  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
-55 to 125  
-55 to 125  
CD54HCT08F  
CD54HCT08F3A  
5962-8688301CA  
CD54HCT08F3A  
CD74HC08E  
CD74HC08EE4  
CD74HC08M  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
PDIP  
PDIP  
N
N
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
25  
25  
Pb-Free  
(RoHS)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
N / A for Pkg Type  
N / A for Pkg Type  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
CD74HC08E  
CD74HC08E  
HC08M  
HC08M  
HC08M  
HC08M  
HC08M  
HC08M  
HC08M  
HJ08  
Pb-Free  
(RoHS)  
SOIC  
D
50  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
CD74HC08M96  
CD74HC08M96E4  
CD74HC08M96G4  
CD74HC08ME4  
CD74HC08MG4  
CD74HC08MT  
SOIC  
D
2500  
2500  
2500  
50  
Green (RoHS  
& no Sb/Br)  
SOIC  
D
Green (RoHS  
& no Sb/Br)  
SOIC  
D
Green (RoHS  
& no Sb/Br)  
SOIC  
D
Green (RoHS  
& no Sb/Br)  
SOIC  
D
50  
Green (RoHS  
& no Sb/Br)  
SOIC  
D
250  
90  
Green (RoHS  
& no Sb/Br)  
CD74HC08PW  
CD74HC08PWG4  
CD74HC08PWR  
TSSOP  
TSSOP  
TSSOP  
PW  
PW  
PW  
Green (RoHS  
& no Sb/Br)  
90  
Green (RoHS  
& no Sb/Br)  
HJ08  
2000  
Green (RoHS  
& no Sb/Br)  
HJ08  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Jun-2014  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(6)  
(3)  
(4/5)  
CD74HC08PWRG4  
CD74HCT08E  
ACTIVE  
TSSOP  
PDIP  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
PW  
14  
14  
14  
14  
14  
14  
14  
14  
2000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-1-260C-UNLIM  
HJ08  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
N
N
D
D
D
D
D
25  
25  
Pb-Free  
(RoHS)  
N / A for Pkg Type  
CD74HCT08E  
CD74HCT08E  
HCT08M  
CD74HCT08EE4  
CD74HCT08M  
Pb-Free  
(RoHS)  
N / A for Pkg Type  
50  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
CD74HCT08M96  
CD74HCT08M96G4  
CD74HCT08ME4  
CD74HCT08MT  
2500  
2500  
50  
Green (RoHS  
& no Sb/Br)  
HCT08M  
Green (RoHS  
& no Sb/Br)  
HCT08M  
Green (RoHS  
& no Sb/Br)  
HCT08M  
250  
Green (RoHS  
& no Sb/Br)  
HCT08M  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Jun-2014  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish  
value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF CD54HC08, CD54HCT08, CD74HC08, CD74HCT08 :  
Catalog: CD74HC08, CD74HCT08  
•
Automotive: CD74HC08-Q1, CD74HC08-Q1  
•
Enhanced Product: CD74HC08-EP, CD74HC08-EP  
•
Military: CD54HC08, CD54HCT08  
•
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects  
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications  
•
Military - QML certified for Military and Defense Applications  
•
Addendum-Page 3  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
CD74HC08M96  
CD74HC08MT  
SOIC  
SOIC  
D
D
14  
14  
14  
14  
14  
2500  
250  
330.0  
330.0  
330.0  
330.0  
330.0  
16.4  
16.4  
12.4  
16.4  
16.4  
6.5  
6.5  
6.9  
6.5  
6.5  
9.0  
9.0  
5.6  
9.0  
9.0  
2.1  
2.1  
1.6  
2.1  
2.1  
8.0  
8.0  
8.0  
8.0  
8.0  
16.0  
16.0  
12.0  
16.0  
16.0  
Q1  
Q1  
Q1  
Q1  
Q1  
CD74HC08PWR  
CD74HCT08M96  
CD74HCT08MT  
TSSOP  
SOIC  
PW  
D
2000  
2500  
250  
SOIC  
D
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
CD74HC08M96  
CD74HC08MT  
SOIC  
SOIC  
D
D
14  
14  
14  
14  
14  
2500  
250  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
38.0  
38.0  
35.0  
38.0  
38.0  
CD74HC08PWR  
CD74HCT08M96  
CD74HCT08MT  
TSSOP  
SOIC  
PW  
D
2000  
2500  
250  
SOIC  
D
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and  
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale  
supplied at the time of order acknowledgment.  
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily  
performed.  
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide  
adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or  
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information  
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or  
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the  
third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration  
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered  
documentation. Information of third parties may be subject to additional restrictions.  
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service  
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.  
TI is not responsible or liable for any such statements.  
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements  
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support  
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which  
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause  
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use  
of any TI components in safety-critical applications.  
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to  
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and  
requirements. Nonetheless, such components are subject to these terms.  
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties  
have executed a special agreement specifically governing such use.  
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in  
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components  
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and  
regulatory requirements in connection with such use.  
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of  
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.  
Products  
Applications  
Audio  
www.ti.com/audio  
amplifier.ti.com  
dataconverter.ti.com  
www.dlp.com  
Automotive and Transportation www.ti.com/automotive  
Communications and Telecom www.ti.com/communications  
Amplifiers  
Data Converters  
DLP® Products  
DSP  
Computers and Peripherals  
Consumer Electronics  
Energy and Lighting  
Industrial  
www.ti.com/computers  
www.ti.com/consumer-apps  
www.ti.com/energy  
dsp.ti.com  
Clocks and Timers  
Interface  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
www.ti.com/industrial  
www.ti.com/medical  
Medical  
Logic  
Security  
www.ti.com/security  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
Space, Avionics and Defense  
Video and Imaging  
www.ti.com/space-avionics-defense  
www.ti.com/video  
microcontroller.ti.com  
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www.ti.com/omap  
OMAP Applications Processors  
Wireless Connectivity  
TI E2E Community  
e2e.ti.com  
www.ti.com/wirelessconnectivity  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2014, Texas Instruments Incorporated  

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