CD74HC153EE4 [TI]
High-Speed CMOS Logic Dual 4- to 1-Line Selector/Multiplexer; 高速CMOS逻辑双路4〜 1线选择器/多路复用器
| 型号： | CD74HC153EE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic Dual 4- to 1-Line Selector/Multiplexer |
| 文件： | 总13页 (文件大小：439K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC153, CD74HC153,
CD54HCT153, CD74HCT153
Data sheet acquired from Harris Semiconductor
SCHS151C
High-Speed CMOS Logic
Dual 4- to 1-Line Selector/Multiplexer
September 1997 - Revised October 2003
Features
Description
• Common Select Inputs
• Separate Enable Inputs
• Buffered inputs and Outputs
The ’HC153 and ’HCT153 are dual 4- to 1-line
selector/multiplexers that select one of four sources for each
section by the common select inputs, S0 and S1. When the
enable inputs (1E, 2E) are HIGH, the outputs are in the LOW
state.
[ /Title
(CD74H
C153,
• Fanout (Over Temperature Range)
CD74H
CT153)
/Subject
(High
Speed
CMOS
Logic
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Ordering Information
TEMP. RANGE
o
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
PART NUMBER
CD54HC153F3A
CD54HCT153F3A
CD74HC153E
( C)
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
Dual 4-
Input
- 2V to 6V Operation
CD74HC153M
- High Noise Immunity: N = 30%, N = 30%of V
IL IH
at
CC
CD74HC153MT
CD74HC153M96
CD74HCT153E
CD74HCT153M
CD74HCT153MT
CD74HCT153M96
V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
Pinout
CD54HC153, CD54HCT153
(CERDIP)
CD74HC153, CD74HCT153
(PDIP, SOIC)
TOP VIEW
1E
S1
1
2
3
4
5
6
7
8
16 V
CC
15 2E
14 S0
1I
1I
1I
1I
3
2
1
0
13 2I
12 2I
11 2I
10 2I
3
2
1
0
1Y
9
2Y
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC153, CD74HC153, CD54HCT153, CD74HCT153
Functional Diagram
1
6
1E
1I
1I
1I
1I
0
1
2
3
5
7
SEL/MUX
1Y
4
3
14
2
S0
S1
10
11
12
13
15
2I
2I
2I
2I
0
1
2
3
9
SEL/MUX
2Y
GND = 8
= 16
2E
V
CC
TRUTH TABLE
DATA INPUTS
SELECT INPUTS
ENABLE OUTPUT
S1
X
L
S0
X
L
I0
X
L
I
I
I
3
E
H
L
L
L
L
L
L
L
L
Y
L
1
2
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
X
X
L
L
L
L
H
X
X
X
X
X
X
H
L
L
H
H
L
L
H
X
X
X
X
H
L
H
H
H
H
L
H
X
X
H
L
H
H
H
H
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
NOTE: Select inputs S1 and S0 are common to both sections.
2
CD54HC153, CD74HC153, CD54HCT153, CD74HCT153
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
CC
DC Input Diode Current, I
For V < -0.5V or V > V
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
3
CD54HC153, CD74HC153, CD54HCT153, CD74HCT153
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
Data
UNIT LOADS
0.45
0.6
Enable
Select
1.35
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.
CC
o
Switching Specifications Input t , t = 6ns
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
V
CC
(V)
PARAMETER
HC TYPES
MIN TYP MAX MIN
MAX
MIN
MAX UNITS
Propagation Delay (Figure 1)
S to Y
t
t
C = 50pF
2
4.5
5
-
-
-
-
-
-
160
32
-
-
-
-
-
200
40
-
-
-
-
-
240
48
-
ns
ns
ns
ns
PLH,
L
PHL
C =15pF
13
-
L
C = 50pF
6
27
34
41
L
4
CD54HC153, CD74HC153, CD54HCT153, CD74HCT153
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
V
CC
(V)
PARAMETER
SYMBOL CONDITIONS
MIN TYP MAX MIN
MAX
180
36
-
MIN
MAX UNITS
I to Y
t
t
C = 50pF
2
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
145
29
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
220
44
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
PLH,
L
PHL
C =15pF
12
-
L
C = 50pF
6
25
120
24
-
31
150
30
-
38
180
36
-
L
E to Y
t
C = 50pF
2
PLH,
L
t
PHL
4.5
5
C =15pF
9
-
L
C = 50pF
6
20
75
15
13
10
-
26
95
19
16
10
-
31
110
22
19
10
-
L
Output Transition Time
(Figure 1)
t
, t
C = 50pF
L
2
-
TLH THL
4.5
6
-
-
Input Capacitance
C
-
-
-
-
IN
Power Dissipation Capacitance
(Notes 3, 4)
C
5
45
PD
HCT TYPES
Propagation Delay (Figure 2)
S to Y
t
t
,
PLH
PHL
C = 50pF
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
14
-
34
-
-
-
-
-
-
-
-
-
-
-
-
43
-
-
-
-
-
-
-
-
-
-
-
51
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
L
C =15pF
L
I to Y
I to Y
E to Y
t
t
t
,
C = 50pF
4.5
5
24
-
30
-
36
-
PLH
L
t
PHL
C =15pF
9
L
,
C = 50pF
4.5
5
34
-
43
-
51
-
PLH
L
t
PHL
C =15pF
14
-
L
,
C = 50pF
4.5
5
27
-
34
41
-
PLH
L
t
PHL
C =15pF
11
-
L
Output Transition Time
Input Capacitance
t
, t
C = 50pF
L
4.5
-
15
10
-
19
10
-
22
10
-
TLH THL
C
-
-
-
IN
Power Dissipation Capacitance
(Notes 3, 4)
C
5
45
PD
NOTES:
3. C
is used to determine the dynamic power consumption, per multiplexer.
2
PD
4. P = V
f (C
PD
+ C ) where f = Input Frequency, C = Output Load Capacitance, V
= Supply Voltage.
D
CC
i
L
i
L
CC
Test Circuit and Waveform
t = 6ns
t = 6ns
f
r
E
90%
V
S
10%
I OR S
V
S
OUTPUT Y
t
t
PHL
PLH
FIGURE 1. PROPAGATION DELAY TIMES
5
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
CDIP
PDIP
Drawing
5962-9050501MEA
CD54HC153F3A
CD54HCT153F3A
CD74HC153E
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
J
16
16
16
16
1
1
TBD
TBD
TBD
A42 SNPB
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
J
1
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HC153EE4
CD74HC153M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
N
D
D
D
D
D
D
D
D
D
N
N
D
D
D
D
D
D
D
D
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC153M96
CD74HC153M96E4
CD74HC153M96G4
CD74HC153ME4
CD74HC153MG4
CD74HC153MT
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC153MTE4
CD74HC153MTG4
CD74HCT153E
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HCT153EE4
CD74HCT153M
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HCT153M96
CD74HCT153M96E4
CD74HCT153M96G4
CD74HCT153ME4
CD74HCT153MG4
CD74HCT153MT
CD74HCT153MTE4
CD74HCT153MTG4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CD74HC153M96
CD74HCT153M96
SOIC
SOIC
D
D
16
16
2500
2500
330.0
330.0
16.4
16.4
6.5
6.5
10.3
10.3
2.1
2.1
8.0
8.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CD74HC153M96
CD74HCT153M96
SOIC
SOIC
D
D
16
16
2500
2500
333.2
333.2
345.9
345.9
28.6
28.6
Pack Materials-Page 2
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