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CD74HC161MTG4 [TI]

High-Speed CMOS Logic Presettable Counters; 高速CMOS逻辑可预置计数器
CD74HC161MTG4
型号： CD74HC161MTG4
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

High-Speed CMOS Logic Presettable Counters
高速CMOS逻辑可预置计数器

计数器 触发器 逻辑集成电路 光电二极管 输出元件
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CD54/74HC161, CD54/74HCT161,  
CD54/74HC163, CD54/74HCT163  
The CD54HCT161 is obsolete  
and no longer is supplied.  
Data sheet acquired from Harris Semiconductor  
SCHS154D  
High-Speed CMOS Logic  
Presettable Counters  
February 1998 - Revised October 2003  
Two count enables, PE and TE, in each counter are  
provided for n-bit cascading. In all counters reset action  
occurs regardless of the level of the SPE, PE and TE inputs  
(and the clock input, CP, in the ’HC161 and ’HCT161  
types).  
Features  
• ’HC161, ’HCT161 4-Bit Binary Counter,  
Asynchronous Reset  
[ /Title  
(CD74  
HC161  
,
CD74  
HCT16  
1,  
CD74  
HC163  
,
CD74  
HCT16  
3)  
• ’HC163, ’HCT163 4-Bit Binary Counter,  
Synchronous Reset  
If a decade counter is preset to an illegal state or assumes  
an illegal state when power is applied, it will return to the  
normal sequence in one count as shown in state diagram.  
• Synchronous Counting and Loading  
• Two Count Enable Inputs for n-Bit Cascading  
• Look-Ahead Carry for High-Speed Counting  
The look-ahead carry feature simplifies serial cascading of  
the counters. Both count enable inputs (PE and TE) must  
be high to count. The TE input is gated with the Q outputs  
of all four stages so that at the maximum count the terminal  
count (TC) output goes high for one clock period. This TC  
pulse is used to enable the next cascaded stage.  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
TEMP. RANGE  
o
• HC Types  
PART NUMBER  
CD54HC161F3A  
CD54HC163F3A  
CD54HCT163F3A  
CD74HC161E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
/Sub-  
ject  
- 2V to 6V Operation  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
(High  
Speed  
CMOS  
Logic  
Preset-  
table  
Counte  
rs)  
/Autho  
r ()  
/Key-  
words  
(High  
Speed  
CMOS  
Logic  
Preset-  
table  
Counte  
rs,  
High  
Speed  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
CD74HC161M  
IL  
IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
CD74HC161MT  
CD74HC161M96  
CD74HC163E  
Description  
The ’HC161, ’HCT161, ’HC163, and ’HCT163 are  
presettable synchronous counters that feature look-ahead  
carry logic for use in high-speed counting applications. The  
’HC161 and ’HCT161 are asynchronous reset decade and  
binary counters, respectively; the ’HC163 and ’HCT163  
devices are decade and binary counters, respectively, that  
are reset synchronously with the clock. Counting and  
parallel presetting are both accomplished synchronously  
with the negative-to-positive transition of the clock.  
CD74HC163M  
CD74HC163MT  
CD74HC163M96  
CD74HCT161E  
CD74HCT161M  
CD74HCT161MT  
CD74HCT161M96  
CD74HCT163E  
CD74HCT163M  
CD74HCT163MT  
CD74HCT163M96  
A low level on the synchronous parallel enable input, SPE,  
disables counting operation and allows data at the P0 to P3  
inputs to be loaded into the counter (provided that the  
setup and hold requirements for SPE are met).  
All counters are reset with a low level on the Master Reset  
input, MR. In the ’HC163 and ’HCT163 counters  
(synchronous reset types), the requirements for setup and  
hold time with respect to the clock must be met.  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163  
Pinout  
CD54HC161, CD54HCT161, CD54HC163, CD54HCT163  
(CERDIP)  
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163  
(PDIP, SOIC)  
TOP VIEW  
MR  
CP  
P0  
1
2
3
4
5
6
7
8
16 V  
CC  
15 TC  
14 Q0  
13 Q1  
12 Q2  
11 Q3  
10 TE  
P1  
P2  
P3  
PE  
9
SPE  
GND  
Functional Diagram  
P0 P1 P2 P3  
3
4
5
6
9
2
14  
13  
12  
11  
15  
SPE  
CP  
MR  
PE  
Q0  
Q1  
Q2  
Q3  
TC  
1
7
10  
TE  
2
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163  
MODE SELECT - FUNCTION TABLE FOR ’HC161 AND ’HCT161  
INPUTS  
OUTPUTS  
OPERATING MODE  
Reset (Clear)  
MR  
L
CP  
X
↑
PE  
X
TE  
SPE  
P
Q
TC  
n
n
X
X
X
L
L
Parallel Load  
H
X
X
l
l
L
H
L
H
↑
X
X
l
h
X
X
X
(Note 1)  
(Note 1)  
(Note 1)  
L
Count  
Inhibit  
H
↑
h
h
X
h (Note 3)  
h (Note 3)  
h (Note 3)  
Count  
H
X
X
I (Note 2)  
X
q
q
n
n
H
I (Note 2)  
MODE SELECT - FUNCTION TABLE FOR ’HC163 AND ’HCT163  
INPUTS  
OUTPUTS  
OPERATING MODE  
MR  
CP  
↑
PE  
TE  
SPE  
P
Q
TC  
n
n
Reset (Clear)  
Parallel Load  
l
X
X
X
X
l
L
L
h (Note 3)  
h (Note 3)  
h (Note 3)  
h (Note 3)  
h (Note 3)  
↑
X
X
l
L
H
L
↑
X
X
l
h
X
X
X
(Note 1)  
(Note 1)  
(Note 1)  
L
Count  
Inhibit  
↑
h
I (Note 2)  
X
h
X
h (Note 3)  
h (Note 3)  
h (Note 3)  
Count  
X
X
q
q
n
n
I (Note 2)  
H = High voltage level steady state; L = Low voltage level steady state; h = High voltage level one setup time prior to the Low-to-High clock  
transition; l = Low voltage level one setup time prior to the Low-to-High clock transition; X = Don’t Care; q = Lower case letters indicate the  
state of the referenced output prior to the Low-to-High clock transition; ↑ = Low-to-High clock transition.  
NOTES:  
1. The TC output is High when TE is High and the counter is at Terminal Count (HHHH for HC/HCT161 and ’HC/HCT163).  
2. The High-to-Low transition of PE or TE on the ’HC/HCT161 and the ’HC/HCT163 should only occur while CP is HIGH for conventional  
operation.  
3. The Low-to-High transition of SPE on the ’HC/HCT161 and SPE or MR on the ’HC/HCT163 should only occur while CP is HIGH for  
conventional operation.  
3
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163  
Absolute Maximum Ratings  
Thermal Information  
o
DC Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
Thermal Resistance (Typical, Note 4)  
θ
( C/W)  
CC  
DC Input Diode Current, I  
For V < -0.5V or V > V  
JA  
IK  
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .  
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .  
67  
73  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
OK  
For V < -0.5V or V > V  
I
I
CC  
o
DC Output Diode Current, I  
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
O
O
CC  
o
DC Drain Current, per Output, I  
O
For -0.5V < V < V  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA  
O
CC  
(SOIC - Lead Tips Only)  
DC Output Source or Sink Current per Output Pin, I  
O
For V > -0.5V or V < V  
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
O
O
CC  
DC V  
or Ground Current, I  
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA  
CC  
CC  
Operating Conditions  
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range, V  
CC  
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
I
O
CC  
Input Rise and Fall Time  
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)  
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)  
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
4. The package thermal impedance is calculated in accordance with JESD 51-7.  
DC Electrical Specifications  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL  
V (V)  
I
I
(mA)  
(V)  
MIN  
TYP  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
O
High Level Input  
Voltage  
V
-
-
-
2
4.5  
6
1.5  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5  
-
1.5  
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA  
IH  
3.15  
-
-
3.15  
-
-
3.15  
4.2  
4.2  
4.2  
-
Low Level Input  
Voltage  
V
-
2
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
IL  
4.5  
6
-
-
-
-
-
-
High Level Output  
Voltage  
CMOS Loads  
V
V
or V  
IH IL  
-0.02  
2
1.9  
1.9  
1.9  
OH  
-0.02  
-0.02  
-
4.5  
6
4.4  
-
4.4  
-
4.4  
-
5.9  
-
5.9  
-
5.9  
-
High Level Output  
Voltage  
TTL Loads  
-
-
-
-
-
-
-
-4  
4.5  
6
3.98  
-
3.84  
-
3.7  
-
-5.2  
0.02  
0.02  
0.02  
-
5.48  
-
5.34  
-
5.2  
-
Low Level Output  
Voltage  
CMOS Loads  
V
V
or V  
IH IL  
2
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
OL  
4.5  
6
Low Level Output  
Voltage  
TTL Loads  
-
4
4.5  
6
0.26  
0.26  
±0.1  
0.33  
0.33  
±1  
0.4  
0.4  
±1  
5.2  
-
Input Leakage  
Current  
I
V
or  
6
I
CC  
GND  
4
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163  
DC Electrical Specifications (Continued)  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
V
CC  
PARAMETER  
SYMBOL  
V (V)  
I
(mA)  
O
(V)  
MIN  
TYP  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
Quiescent Device  
Current  
I
V
GND  
or  
0
6
-
-
8
-
80  
-
160  
µA  
CC  
CC  
HCT TYPES  
High Level Input  
Voltage  
V
-
-
-
-
4.5 to  
5.5  
2
-
-
-
-
-
0.8  
-
2
-
-
0.8  
-
2
-
-
0.8  
-
V
V
V
IH  
Low Level Input  
Voltage  
V
4.5 to  
5.5  
IL  
High Level Output  
Voltage  
CMOS Loads  
V
V
V
or V  
-0.02  
4.5  
4.5  
4.5  
4.5  
4.4  
4.4  
4.4  
OH  
IH  
IH  
IL  
High Level Output  
Voltage  
TTL Loads  
-4  
3.98  
-
-
-
-
3.84  
-
3.7  
-
V
V
V
Low Level Output  
Voltage  
CMOS Loads  
V
or V  
0.02  
4
-
-
0.1  
0.26  
-
-
0.1  
0.33  
-
-
0.1  
0.4  
OL  
IL  
Low Level Output  
Voltage  
TTL Loads  
Input Leakage  
Current  
I
V
and  
0
0
-
5.5  
5.5  
-
-
-
±0.1  
8
-
-
-
±1  
80  
-
-
-
±1  
µA  
µA  
µA  
I
CC  
GND  
Quiescent Device  
Current  
I
V
or  
-
160  
490  
CC  
CC  
GND  
Additional Quiescent  
Device Current Per  
Input Pin: 1 Unit Load  
∆I  
CC  
(Note 5)  
V
4.5 to  
5.5  
100  
360  
450  
CC  
-2.1  
NOTE:  
5. For dual-supply systems theoretical worst case (V = 2.4V, V  
I
= 5.5V) specification is 1.8mA.  
CC  
HCT Input Loading Table  
INPUT  
UNIT LOADS  
0.25  
P0 - P3  
PE  
0.65  
CP  
1.05  
MR  
0.8  
SPE  
TE  
0.5  
1.05  
NOTE: Unit Load is ∆I  
360µA max at 25 C.  
limit specified in DC Electrical Table, e.g.,  
CC  
o
5
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163  
Prerequisite For Switching Specifications  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
Maximum CP Frequency  
(Note 6)  
f
t
-
-
-
-
-
-
-
-
-
-
-
2
6
30  
35  
80  
16  
14  
100  
20  
17  
60  
12  
10  
50  
10  
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
24  
28  
100  
20  
17  
125  
25  
21  
75  
15  
13  
65  
13  
11  
75  
15  
13  
80  
16  
14  
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
20  
24  
120  
24  
20  
150  
30  
26  
90  
18  
15  
75  
15  
13  
90  
18  
15  
100  
20  
17  
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz  
MHz  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
MAX  
4.5  
6
CP Width (Low)  
2
W(L)  
4.5  
6
MR Pulse Width (161)  
Setup Time, Pn to CP  
t
2
W
4.5  
6
t
t
t
t
2
SU  
SU  
SU  
SU  
4.5  
6
Setup Time, PE or TE to CP  
Setup Time, SPE to CP  
Setup Time, MR to CP (163)  
Hold Time, PN to CP  
2
4.5  
6
2
60  
12  
10  
65  
13  
11  
3
4.5  
6
2
4.5  
6
t
t
t
2
H
H
H
4.5  
6
3
3
3
3
3
3
Hold Time, TE or PE to CP  
Hold Time, SPE to CP  
Recovery Time, MR to CP (161)  
2
0
0
0
4.5  
6
0
0
0
0
0
0
2
0
0
0
4.5  
6
0
0
0
0
0
0
t
2
75  
15  
13  
95  
19  
16  
110  
22  
19  
REC  
4.5  
6
6
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163  
Prerequisite For Switching Specifications (Continued)  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
HCT TYPES  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
Maximum CP Frequency  
CP Width (Low) (Note 6)  
MR Pulse Width (161)  
Setup Time, Pn to CP  
Setup Time, PE or TE to CP  
Setup Time, SPE to CP  
Setup Time, MR to CP (163)  
Hold Time, PN to CP  
f
t
-
-
-
-
-
-
-
-
-
-
-
4.5  
4.5  
4.5  
4.5  
4.5  
4.5  
4.5  
4.5  
4.5  
4.5  
4.5  
30  
16  
20  
10  
13  
12  
13  
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
24  
20  
25  
13  
16  
15  
16  
5
-
-
-
-
-
-
-
-
-
-
-
20  
24  
30  
15  
20  
18  
20  
5
-
-
-
-
-
-
-
-
-
-
-
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
MAX  
W(L)  
t
W
t
t
t
t
SU  
SU  
SU  
SU  
t
t
t
H
H
H
Hold Time, TE or PE to CP  
Hold Time, SPE to CP  
Recovery Time, MR to CP (161)  
NOTE:  
3
3
3
3
3
3
t
15  
19  
22  
REC  
6. Applies to non-cascaded operation only. With cascaded counters clock to terminal count propagation delays, count enables (PE or TE)-  
to-clock setup times, and count enables (PE or TE)-to-clock hold times determine maximum clock frequency. For example with these HC  
devices:  
1
1
----------------------------  
37 + 10 + 0  
f
(CP) = ----------------------------------------------------------------------------------------------------------------------------------------------------- =  
CP-to-TC prop. delay + TE-to-CP setup + TE-to-CP Hold  
≈ 21MHz(min)  
MAX  
Switching Specifications C = 50pF, Input t , t = 6ns  
L
r f  
o
o
-40 C TO  
-55 C TO  
o
o
o
25 C  
85 C  
125 C  
TEST  
SYMBOL CONDITIONS  
PARAMETER  
HC TYPES  
V
(V) MIN  
TYP MAX  
MIN  
MAX  
MIN  
MAX UNITS  
CC  
Propagation Delay  
CP to TC  
t
, t  
C
= 50pF  
PHL PLH  
L
2
4.5  
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
185  
37  
-
-
-
-
-
-
-
-
-
-
-
-
-
230  
46  
-
-
-
-
-
-
-
-
-
-
-
-
-
280  
56  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
C
C
C
= 15pF  
= 50pF  
= 50pF  
15  
-
L
L
L
6
31  
185  
37  
-
39  
230  
46  
-
48  
280  
56  
-
CP to Qn  
t
t
t
2
-
PHL, PLH  
4.5  
5
-
C
C
C
= 15pF  
= 50pF  
= 50pF  
15  
-
L
L
L
6
31  
120  
24  
-
39  
150  
30  
-
48  
180  
36  
-
TE to TC  
t
2
-
PHL, PLH  
4.5  
5
-
C
C
= 15pF  
= 50pF  
9
-
L
6
20  
26  
31  
L
7
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163  
Switching Specifications C = 50pF, Input t , t = 6ns (Continued)  
L
r f  
o
o
-40 C TO  
-55 C TO  
o
o
o
25 C  
85 C  
125 C  
TEST  
SYMBOL CONDITIONS  
PARAMETER  
MR to Qn (161)  
V
(V) MIN  
TYP MAX  
MIN  
MAX  
MIN  
MAX UNITS  
CC  
t
C
= 50pF  
2
-
-
-
210  
42  
-
-
-
-
-
-
-
-
-
-
-
-
265  
53  
-
-
-
-
-
-
-
-
-
-
-
-
315  
63  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
pF  
PHL  
PHL  
L
4.5  
5
-
-
-
-
-
-
-
-
-
-
C
C
C
= 15pF  
= 50pF  
= 50pF  
18  
-
L
L
L
6
36  
210  
42  
36  
75  
15  
13  
-
45  
265  
53  
45  
95  
19  
16  
-
54  
315  
63  
54  
110  
22  
19  
-
MR to TC (161)  
t
2
-
4.5  
6
-
C
C
= 50pF  
= 50pF  
-
L
Output Transition Time  
t
, t  
THL TLH  
2
-
L
4.5  
6
-
-
Power Dissipation Capacitance  
(Notes 7, 8)  
C
-
5
60  
PD  
Input Capacitance  
C
C
= 50pF  
-
10  
-
10  
-
10  
-
10  
pF  
IN  
L
HCT TYPES  
Propagation Delay  
CP to TC  
t
t
t
t
C
C
C
C
C
C
C
C
C
C
= 50pF  
= 15pF  
= 50pF  
= 15pF  
= 50pF  
= 15pF  
= 50pF  
= 15pF  
= 50pF  
= 50pF  
-
4.5  
5
-
-
-
-
-
-
-
-
-
-
-
-
18  
-
42  
-
-
-
-
-
-
-
-
-
-
-
-
53  
-
-
-
-
-
-
-
-
-
-
-
-
63  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
pF  
PHL, PLH  
L
L
L
L
L
L
L
L
L
L
CP to Qn  
t
4.5  
5
39  
-
49  
-
59  
-
PHL, PLH  
16  
-
TE to TC  
t
4.5  
5
32  
-
40  
-
48  
-
PHL, PLH  
13  
-
MR to Qn (161)  
t
t
4.5  
5
50  
-
63  
-
75  
-
PHL  
PHL  
21  
-
MR to TC (161)  
4.5  
4.5  
5
50  
15  
-
63  
19  
-
75  
22  
-
Output Transition Time  
t
, t  
THL TLH  
-
Power Dissipation Capacitance  
(Notes 7, 8)  
C
63  
PD  
Input Capacitance  
NOTES:  
C
C
= 50pF  
-
10  
-
10  
-
10  
-
10  
pF  
IN  
L
7. C  
is used to determine the dynamic power consumption, per package.  
PD  
2
2
8. P = C  
V
f + ∑(C V  
f ) where f = Input Frequency, f = Output Frequency, C = Output Load Capacitance, V = Supply  
CC  
D
PD CC  
i
L
CC  
O
i
O
L
Voltage.  
8
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163  
Timing Diagram  
MASTER RESET (161)  
(ASYNCHRONOUS)  
(SYNCHRONOUS)  
MASTER RESET (163)  
SPE  
P0  
PRESET  
DATA  
INPUTS  
P1  
P2  
P3  
CP (161)  
CP (163)  
PE  
COUNT  
ENABLES  
TE  
Q0  
Q1  
Q2  
OUTPUTS  
Q3  
TC  
12  
13  
14  
15  
0
1
2
COUNT  
INHIBIT  
RESET PRESET  
Sequence illustrated on waveforms:  
1. Reset outputs to zero.  
2. Preset to binary twelve.  
3. Count to thirteen, fourteen, fifteen, zero, one, and two.  
4. Inhibit.  
9
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163  
Test Circuits and Waveforms  
I
t
+ t =  
WH  
WL  
I
t C = 6ns  
fC  
r
L
t
+ t  
=
L
WL  
WH  
t C = 6ns  
t C  
f
L
fC  
t C  
f
L
L
r
L
3V  
V
CC  
90%  
10%  
2.7V  
0.3V  
CLOCK  
CLOCK  
50%  
10%  
1.3V  
0.3V  
50%  
t
50%  
1.3V  
t
1.3V  
GND  
GND  
t
t
WH  
WL  
WH  
WL  
NOTE: Outputs should be switching from 10% V  
to 90% V  
in  
NOTE: Outputs should be switching from 10% V  
to 90% V  
in  
CC  
CC  
CC  
CC  
accordance with device truth table. For f  
, input duty cycle = 50%.  
accordance with device truth table. For f  
, input duty cycle = 50%.  
MAX  
MAX  
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND  
PULSE WIDTH  
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND  
PULSE WIDTH  
t = 6ns  
t = 6ns  
f
t = 6ns  
f
t = 6ns  
r
r
V
3V  
CC  
90%  
50%  
10%  
2.7V  
1.3V  
0.3V  
INPUT  
INPUT  
GND  
GND  
t
t
t
t
THL  
TLH  
THL  
TLH  
90%  
50%  
10%  
90%  
1.3V  
INVERTING  
OUTPUT  
INVERTING  
OUTPUT  
10%  
t
t
PLH  
t
t
PHL  
PLH  
PHL  
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
t C  
t C  
t C  
t C  
r
L
f
L
f
L
r
L
V
3V  
CC  
90%  
10%  
2.7V  
0.3V  
CLOCK  
INPUT  
CLOCK  
INPUT  
50%  
1.3V  
GND  
GND  
t
t
t
t
H(L)  
H(H)  
H(H)  
H(L)  
V
3V  
CC  
DATA  
INPUT  
DATA  
INPUT  
50%  
1.3V  
t
SU(L)  
1.3V  
1.3V  
GND  
GND  
t
t
t
SU(H)  
SU(H)  
SU(L)  
t
t
90%  
50%  
t
t
THL  
TLH  
THL  
TLH  
90%  
1.3V  
90%  
90%  
1.3V  
OUTPUT  
OUTPUT  
10%  
10%  
t
t
t
PLH  
t
PHL  
PHL  
PLH  
t
REM  
t
REM  
V
3V  
CC  
SET, RESET  
OR PRESET  
SET, RESET  
OR PRESET  
50%  
1.3V  
GND  
GND  
IC  
IC  
C
C
L
L
50pF  
50pF  
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,  
AND PROPAGATION DELAY TIMES FOR EDGE  
TRIGGERED SEQUENTIAL LOGIC CIRCUITS  
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,  
AND PROPAGATION DELAY TIMES FOR EDGE  
TRIGGERED SEQUENTIAL LOGIC CIRCUITS  
10  
PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Oct-2007  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
CDIP  
CDIP  
CDIP  
CDIP  
CDIP  
CDIP  
PDIP  
Drawing  
CD54HC161F  
CD54HC161F3A  
CD54HC163F3A  
CD54HCT161F3A  
CD54HCT163F  
CD54HCT163F3A  
CD74HC161E  
ACTIVE  
ACTIVE  
J
J
J
J
J
J
N
16  
16  
16  
16  
16  
16  
16  
1
1
1
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
A42 SNPB  
A42 SNPB  
A42 SNPB  
Call TI  
N / A for Pkg Type  
N / A for Pkg Type  
N / A for Pkg Type  
Call TI  
ACTIVE  
OBSOLETE  
ACTIVE  
1
1
A42 SNPB  
A42 SNPB  
N / A for Pkg Type  
N / A for Pkg Type  
ACTIVE  
ACTIVE  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CD74HC161EE4  
CD74HC161M  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
N
D
D
D
D
D
D
D
D
D
N
N
D
D
D
D
D
D
D
D
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC161M96  
CD74HC161M96E4  
CD74HC161M96G4  
CD74HC161ME4  
CD74HC161MG4  
CD74HC161MT  
CD74HC161MTE4  
CD74HC161MTG4  
CD74HC163E  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CD74HC163EE4  
CD74HC163M  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC163M96  
CD74HC163M96E4  
CD74HC163M96G4  
CD74HC163ME4  
CD74HC163MG4  
CD74HC163MT  
CD74HC163MTE4  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Oct-2007  
Orderable Device  
CD74HC163MTG4  
CD74HCT161E  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SOIC  
D
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
PDIP  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
N
N
D
D
D
D
D
D
D
D
D
N
N
D
D
D
D
D
D
D
D
D
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CD74HCT161EE4  
CD74HCT161M  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HCT161M96  
CD74HCT161M96E4  
CD74HCT161M96G4  
CD74HCT161ME4  
CD74HCT161MG4  
CD74HCT161MT  
CD74HCT161MTE4  
CD74HCT161MTG4  
CD74HCT163E  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CD74HCT163EE4  
CD74HCT163M  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HCT163M96  
CD74HCT163M96E4  
CD74HCT163M96G4  
CD74HCT163ME4  
CD74HCT163MG4  
CD74HCT163MT  
CD74HCT163MTE4  
CD74HCT163MTG4  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Oct-2007  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 3  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
12-Feb-2008  
TAPE AND REEL BOX INFORMATION  
Device  
Package Pins  
Site  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) (mm) Quadrant  
(mm)  
330  
330  
330  
330  
(mm)  
16  
CD74HC161M96  
CD74HC163M96  
CD74HCT161M96  
CD74HCT163M96  
D
D
D
D
16  
16  
16  
16  
SITE 27  
SITE 27  
SITE 27  
SITE 27  
6.5  
6.5  
6.5  
6.5  
10.3  
10.3  
10.3  
10.3  
2.1  
2.1  
2.1  
2.1  
8
8
8
8
16  
16  
16  
16  
Q1  
Q1  
Q1  
Q1  
16  
16  
16  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
12-Feb-2008  
Device  
Package  
Pins  
Site  
Length (mm) Width (mm) Height (mm)  
CD74HC161M96  
CD74HC163M96  
CD74HCT161M96  
CD74HCT163M96  
D
D
D
D
16  
16  
16  
16  
SITE 27  
SITE 27  
SITE 27  
SITE 27  
342.9  
342.9  
342.9  
342.9  
345.9  
345.9  
345.9  
345.9  
28.58  
28.58  
28.58  
28.58  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,  
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should  
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are  
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard  
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where  
mandated by government requirements, testing of all parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and  
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acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products  
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be  
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such safety-critical applications.  
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are  
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specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at  
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.  
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are  
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated  
products in automotive applications, TI will not be responsible for any failure to meet such requirements.  
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:  
Products  
Applications  
Audio  
Automotive  
Broadband  
Digital Control  
Medical  
Amplifiers  
Data Converters  
DSP  
Clocks and Timers  
Interface  
amplifier.ti.com  
dataconverter.ti.com  
dsp.ti.com  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
www.ti.com/audio  
www.ti.com/automotive  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/medical  
www.ti.com/military  
Logic  
Military  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
microcontroller.ti.com  
www.ti-rfid.com  
Optical Networking  
Security  
Telephony  
Video & Imaging  
Wireless  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
RF/IF and ZigBee® Solutions www.ti.com/lprf  
www.ti.com/wireless  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2008, Texas Instruments Incorporated  

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