CD74HC173M [TI]
High Speed CMOS Logic Quad D-Type Flip-Flop, Three-State; 高速CMOS逻辑四路D型触发器，三态
| 型号： | CD74HC173M |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic Quad D-Type Flip-Flop, Three-State |
| 文件： | 总10页 (文件大小：59K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC173,
CD74HCT173
Data sheet acquired from Harris Semiconductor
SCHS158
High Speed CMOS Logic
February 1998
Quad D-Type Flip-Flop, Three-State
Features
Description
• Three-State Buffered Outputs
• Gated Input and Output Enables
The Harris CD74HC173 and CD74HCT173 high speed
three-state quad D-type flip-flops are fabricated with silicon
gate CMOS technology. They possess the low power con-
sumption of standard CMOS Integrated circuits, and can
operate at speeds comparable to the equivalent low power
Schottky devices. The buffered outputs can drive 15 LSTTL
loads. The large output drive capability and three-state fea-
ture make these parts ideally suited for interfacing with bus
lines in bus oriented systems.
[ /Title
(CD74H
C173,
CD74H
CT173)
/Subject
(High
Speed
CMOS
Logic
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
The four D-type flip-flops operate synchronously from a com-
mon clock. The outputs are in the three-state mode when
either of the two output disable pins are at the logic “1” level.
The input ENABLES allow the flip-flops to remain in their
present states without having to disrupt the clock If either of
the 2 input ENABLES are taken to a logic “1” level, the Q
outputs are fed back to the inputs, forcing the flip-flops to
remain in the same state. Reset is enabled by taking the
MASTER RESET (MR) input to a logic “1” level. The data
outputs change state on the positive going edge of the clock.
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
CC
IL
IH
at V
= 5V
CC
Quad D-
Type
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
The CD74HCT173 logic family is functionally, as well as pin
compatible with the standard 74LS logic family.
Pinout
Ordering Information
CD74HC173, CD74HC173
(PDIP, SOIC)
TEMP. RANGE
PKG.
NO.
o
TOP VIEW
PART NUMBER
CD74HC173E
CD74HCT173E
CD74HC173M
CD74HCT173M
NOTES:
( C)
PACKAGE
16 Ld PDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
-55 to 125
-55 to 125
-55 to 125
-55 to 125
E16.3
OE
1
2
3
4
5
6
7
8
16 V
CC
15 MR
14 D0
13 D1
12 D2
11 D3
10 E2
OE2
E16.3
Q
Q
Q
Q
0
1
2
3
M16.15
M16.15
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
CP
9
E1
GND
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1641.1
Copyright © Harris Corporation 1998
1
CD74HC173, CD74HCT173
Functional Diagram
E1
E2
10
9
14
13
12
11
7
3
D0
D1
D2
D3
CP
Q
Q
Q
Q
0
1
2
3
4
5
6
15
1
2
MR
OE1
OE2
TRUTH TABLE
INPUTS
DATA ENABLE
DATA
OUTPUT
MR
CP
X
L
E1
X
X
H
X
L
E2
X
X
X
H
L
D
X
X
X
X
L
Q
n
H
L
L
Q
Q
Q
0
0
0
L
↑
L
↑
L
L
↑
L
↑
L
L
H
H
NOTE:
When either OE1 or OE2 (or both) is (are) high the output is disabled
to the high-impedance state, however, sequential operation of the
flip-flops is not affected.
H = High Voltage Level
L
X
↑
= Low Voltage Level
= Irrelevant
= Transition from Low to High Level
Q = Level Before the Indicated Steady-State Input Conditions Were
0
Established
2
CD74HC173, CD74HCT173
Logic Diagram
9
E1
10
E2
V
CC
D
Q
14
P
D0
3
Q
0
7
CP
CP
Q
N
R
15
MR
1
OE1
2
OE2
13
D1
4
5
6
Q
Q
Q
1
2
3
12
3 CIRCUITS IDENTICAL TO ABOVE CIRCUIT
IN DASHED ENCLOSURE
D2
11
D3
3
CD74HC173, CD74HCT173
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
160
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±70mA
CC
CC
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-6
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-7.8
Low Level Output
Voltage
CMOS Loads
V
V
V
or
0.02
0.02
0.02
6
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
7.8
Input Leakage
Current
I
V
or
-
6
6
-
-
-
-
±0.1
-
-
±1
-
-
±1
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
0
8
80
160
CC
CC
GND
4
CD74HC173, CD74HCT173
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
Three-State Leakage
Current
I
V
V
or
-
6
-
-
±0.5
-
±0.5
-
±10
µA
OZ
IL
IH
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
V
IL
High Level Output
Voltage
TTL Loads
-6
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or
0.02
6
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IH
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆I
V
4.5 to
5.5
100
360
450
CC
CC
-2.1
Three-State Leakage
Current
I
V
V
or
-
5.5
-
-
±0.5
-
±5.0
-
±10
µA
OZ
IL
IH
NOTE:
4. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
D0-D3
UNIT LOADS
0.15
0.15
0.25
0.2
E1 and E2
CP
MR
OE1 and OE2
0.5
NOTE: Unit Load is ∆I
CC
Specifications table, e.g., 360µA max at 25 C.
limit specified in DC Electrical
o
5
CD74HC173, CD74HCT173
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
PARAMETER
HC TYPES
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
MAX
MAX
UNITS
CC
Propagation Delay, Clock to
Output
t
, t
C = 50pF
2
-
-
200
40
-
250
50
-
300
60
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
pF
pF
PLH PHL
L
4.5
C = 15pF
L
5
6
2
17
-
CL = 50pF
34
175
35
-
43
220
44
-
51
265
53
-
Propagation Delay, MR to
Output
t
C = 50pF
-
PHL
L
4.5
5
-
C = 15pF
L
12
-
CL = 50pF
CL = 50pF
6
30
150
30
-
37
190
38
-
45
225
45
-
Propagation Delay Output
Enable to Q (Figure 6)
t
t
, t
PLZ PHZ
2
, t
PZL PZH
C = 50pF
4.5
5
L
C = 15pF
L
12
CL = 50pF
6
26
60
12
10
-
33
75
15
13
-
38
90
18
15
-
Output Transition Times
t
, t
TLH THL
C = 50pF
2
-
-
L
4.5
6
-
Maximum Clock Frequency
Input Capacitance
f
C = 15pF
L
5
60
-
MAX
C
-
-
-
10
10
10
10
10
10
IN
Three-State Output
Capacitance
C
-
-
O
Power Dissipation
Capacitance
C
-
5
29
-
-
-
pF
PD
(Notes 5, 6)
HCT TYPES
Propagation Delay, Clock to
Output
t
, t
PLH PHL
C = 50pF
4.5
5
-
40
-
50
-
60
-
ns
ns
L
C = 15pF
17
-
L
Propagation Delay, MR to
Output
t
C = 50pF
4.5
5
44
-
55
-
66
-
ns
PHL
L
C = 15pF
L
18
ns
Propagation Delay Output
Enable to Q (Figure 6)
t , t
PZL PZH
CL = 50pF
2
150
30
-
190
38
-
225
45
-
ns
C = 50pF
4.5
5
ns
L
C = 15pF
L
14
ns
CL = 50pF
6
26
15
-
33
19
-
38
22
-
ns
Output Transition Times
Maximum Clock Frequency
Input Capacitance
t
, t
TLH THL
C = 50pF
4.5
5
-
ns
L
f
C = 15pF
L
60
-
MHz
pF
pF
MAX
C
-
-
-
10
-
10
-
10
-
IN
Power Dissipation
Capacitance
C
5
34
PD
(Notes 5, 6)
NOTES:
5. C
PD
is used to determine the dynamic power consumption, per package.
2
2
6. P = V
CC
f + ∑ (C V
+ f ) where f = Input Frequency, f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
i
L
CC
O
i
O
L
6
CD74HC173, CD74HCT173
Prerequisite For Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CC
Maximum Clock Frequency
f
2
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
24
28
100
20
17
100
20
17
75
15
13
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
20
24
120
24
20
120
24
20
90
18
15
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
ns
MAX
4.5
30
35
80
16
14
80
16
14
60
12
10
3
6
2
MR Pulse Width
t
t
w
w
4.5
6
ns
ns
Clock Pulse Width
2
ns
4.5
6
ns
ns
Set-up Time, Data to Clock
and E to Clock
t
2
ns
SU
4.5
6
ns
ns
Hold Time, Data to Clock
Hold Time, E to Clock
t
t
2
ns
H
H
4.5
6
3
3
3
ns
3
3
3
ns
2
0
0
0
ns
4.5
6
0
0
0
ns
0
0
0
ns
Removal Time, MR to Clock
t
2
60
12
10
75
15
13
90
18
15
ns
REM
4.5
6
ns
ns
HCT TYPES
Maximum Clock Frequency
f
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
20
15
25
12
18
0
-
-
-
-
-
-
-
-
16
19
31
15
23
0
-
-
-
-
-
-
-
-
13
22
38
18
27
0
-
-
-
-
-
-
-
-
MHz
ns
MAX
MR Pulse Width
t
w
w
Clock Pulse Width
t
ns
Set-up Time, E to Clock
Set-up Time, Data to Clock
Hold Time, Data to Clock
Hold Time, E to Clock
Removal Time, MR to Clock
t
t
ns
SU
ns
SU
t
t
ns
H
0
0
0
ns
H
t
12
15
18
ns
REM
7
CD74HC173, CD74HCT173
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
f
t C
f
L
CL
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%. accordance with device truth table. For f , input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
t
t
H(L)
H(H)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
8
Test Circuits and Waveforms (Continued)
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
t
t
t
PZL
PZL
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 7. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 8. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
PLZ
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
V
, C = 50pF.
CC
L
FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
9
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