CD74HC595E [TI]
8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS; 8位移位寄存器具有三态输出寄存器
| 型号： | CD74HC595E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS |
| 文件： | 总16页 (文件大小：466K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCHS353 − JANUARY 2004
DW, E, M, NS, OR SM PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
D
8-Bit Serial-In, Parallel-Out Shift
Wide Operating Voltage Range of 2 V to 6 V
High-Current 3-State Outputs Can Drive Up
To 15 LSTTL Loads
Q
Q
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
B
Q
C
D
A
Q
SER
OE
Low Power Consumption, 80-µA Max I
Typical t = 14 ns
pd
6-mA Output Drive at 5 V
CC
Q
E
Q
12 RCLK
F
11
10
9
Q
SRCLK
SRCLR
G
Low Input Current of 1 µA Max
Shift Register Has Direct Clear
Q
H
GND
Q
H′
description/ordering information
The CD74HC595 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and
storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial
output for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − E
Tube of 25
Tube of 40
Reel of 2000
Tube of 40
Reel of 2500
Reel of 250
Reel of 2000
Tube of 80
Reel of 2000
CD74HC595E
CD74HC595E
CD74HC595DW
CD74HC595DWR
CD74HC595M
SOIC − DW
HC595M
−55°C to 125°C
CD74HC595M96
CD74HC595MT
CD74HC595NSR
CD74HC595SM
CD74HC595SM96
SOIC − M
HC595M
SOP − NS
HC595M
HJ595
SSOP − SM
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢑꢊ ꢋ ꢄ ꢒ ꢈꢌꢋꢓꢋ ꢏ ꢔꢕꢋ ꢖꢕ ꢋ ꢎꢏ ꢐ ꢊꢌ ꢋꢏ ꢎꢌ
SCHS353 − JANUARY 2004
FUNCTION TABLE
INPUTS
SER SRCLK SRCLR RCLK
FUNCTION
Outputs Q −Q are disabled.
OE
H
X
X
X
X
X
X
X
X
L
X
X
X
A
H
L
Outputs Q −Q are enabled.
A H
X
Shift register is cleared.
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
L
↑
H
X
X
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
H
X
↑
H
X
X
X
X
X
↑
Shift-register data is stored in the storage register.
2
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SCHS353 − JANUARY 2004
logic diagram (positive logic)
13
OE
12
RCLK
10
SRCLR
11
SRCLK
14
SER
1D
C1
3R
C3
15
Q
A
R
3S
2S
2R
C2
3R
C3
1
Q
B
R
3S
2S
2R
C2
3R
C3
2
Q
Q
C
D
R
3S
2S
2R
3R
C3
3S
3
4
5
6
C2
R
2S
2R
3R
C3
3S
Q
Q
Q
C2
E
F
R
2S
2R
3R
C3
3S
C2
R
2S
2R
3R
C3
C2
G
R
3S
2S
2R
C2
3R
C3
3S
7
9
Q
Q
H
R
H′
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SCHS353 − JANUARY 2004
timing diagram
SRCLK
SER
RCLK
SRCLR
OE
Q
Q
A
B
Q
Q
C
D
Q
E
Q
F
Q
G
Q
H
Q
H’
NOTE:
implies that the output is in 3-State mode.
4
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SCHS353 − JANUARY 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
Package thermal impedance, θ (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
SM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN NOM
MAX
UNIT
V
Supply voltage
2
1.5
5
6
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
= 4.5 V
= 6 V
3.15
4.2
V
High-level input voltage
V
V
= 2 V
0.5
1.35
1.8
= 4.5 V
= 6 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
V
V
I
CC
Output voltage
O
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
‡
= 4.5 V
= 6 V
∆t/∆v
Input transition rise/fall time
ns
T
A
Operating free-air temperature
−55
°C
NOTE 3: All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
‡
If this device is used in the threshold region (from V max = 0.5 V to V min = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at t = 1000 ns and V
IL
IH
= 2 V does not damage the device; however, functionally,
t
CC
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
5
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SCHS353 − JANUARY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= -55°C TO
125°C
T
A
= -40°C TO
85°C
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
CC
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
1.9
4.4
5.9
3.7
3.7
5.2
5.2
1.9
4.4
5.9
I
= −20 µA
OH
Q
, I
H′ OH
= −4 mA
3.98
4.3
4.3
3.84
3.84
5.34
5.34
V
OH
V = V or V
I IH IL
V
4.5 V
6 V
Q −Q , I
= −6 mA
3.98
5.48
5.48
A
H
OH
Q
, I
H′ OH
= −5.2 mA
5.8
Q −Q , I
= −7.8 mA
5.8
A
H
OH
2 V
4.5 V
6 V
0.002
0.001
0.001
0.17
0.17
0.15
0.15
0.1
0.1
0.1
0.1
0.1
0.1
0.1
I
= 20 µA
OL
0.1
0.1
0.1
Q
, I
H′ OL
= 4 mA
= 6 mA
= 5.2 mA
0.26
0.26
0.26
0.26
100
0.5
0.4
0.33
0.33
0.33
0.33
1000
5
V
V = V or V
V
OL
I
IH
IL
4.5 V
6 V
Q −Q , I
OL
0.4
A
H
Q
, I
H′ OL
0.4
Q −Q , I
= 7.8 mA
0.4
A
H
H
OL
I
I
I
V = V
or 0
6 V
6 V
6 V
1000
10
nA
µA
µA
I
I
CC
V
O
= V
CC
or 0, Q −Q
0.01
OZ
CC
A
V = V
I CC
or 0,
I
O
= 0
8
160
80
2 V
to 6 V
C
3
10
10
10
pF
i
6
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SCHS353 − JANUARY 2004
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
A
= -55°C TO
125°C
T
A
= -40°C TO
85°C
T
A
= 25°C
V
CC
UNIT
MIN
MAX
6
MIN
MAX
4.2
21
MIN
MAX
5
2 V
4.5 V
6 V
31
25
f
Clock frequency
Pulse duration
MHz
clock
36
25
29
2 V
80
16
14
80
16
14
100
20
17
75
15
13
50
10
9
120
100
4.5 V
6 V
24
20
120
24
20
150
30
25
113
23
19
75
15
13
75
15
13
0
20
17
100
20
17
125
25
21
94
19
16
65
13
11
60
12
11
0
SRCLK or RCLK high or low
SRCLR low
t
w
ns
2 V
4.5 V
6 V
2 V
4.5 V
6 V
SER before SRCLK↑
2 V
†
4.5 V
6 V
SRCLK↑ before RCLK↑
t
su
Setup time
ns
2 V
4.5 V
6 V
SRCLR low before RCLK↑
2 V
50
10
9
4.5 V
6 V
SRCLR high (inactive) before SRCLK↑
2 V
0
t
h
Hold time, SER after SRCLK↑
4.5 V
6 V
0
0
0
ns
0
0
0
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
7
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SCHS353 − JANUARY 2004
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= -55°C TO
125°C
T
A
= -40°C TO
85°C
T
A
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
6
TYP
26
38
42
50
17
14
50
17
14
51
18
15
40
15
13
42
23
20
28
8
MAX
MIN
MAX
MIN
MAX
2 V
4.5 V
6 V
4.2
21
25
5
25
29
31
36
f
t
MHz
max
pd
2 V
160
32
240
48
200
40
4.5 V
6 V
SRCLK
RCLK
SRCLR
OE
Q
H′
27
41
34
ns
2 V
150
30
225
45
187
37
4.5 V
6 V
Q −Q
A
H
26
38
32
2 V
175
35
261
52
219
44
4.5 V
6 V
t
t
t
Q
ns
ns
ns
PHL
H′
30
44
37
2 V
150
30
225
45
187
37
4.5 V
6 V
Q −Q
A
en
H
H
H
26
38
32
2 V
200
40
300
60
250
50
4.5 V
6 V
OE
Q −Q
A
dis
34
51
43
2 V
60
90
75
4.5 V
6 V
12
18
15
Q −Q
A
6
10
15
13
t
t
ns
2 V
28
8
75
110
22
95
Q
4.5 V
6 V
15
19
H′
6
13
19
16
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= -55°C TO
125°C
T
A
= -40°C TO
85°C
T
A
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
ns
CC
MIN
TYP
60
22
19
70
23
19
45
17
13
MAX
200
40
MIN
MAX
300
60
MIN
MAX
250
50
2 V
4.5 V
6 V
t
pd
t
en
t
t
RCLK
OE
Q −Q
A
H
H
H
34
51
43
2 V
200
40
298
60
250
50
4.5 V
6 V
Q −Q
A
ns
34
51
43
2 V
210
42
315
63
265
53
Q −Q
A
4.5 V
6 V
ns
36
53
45
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀ
ꢅ
ꢆ
ꢅ
ꢌ
ꢌ
ꢑ
ꢊ
ꢋ
ꢄ
ꢒ
ꢈ
ꢌ
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ꢓ
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ꢔ
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SCHS353 − JANUARY 2004
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
400
pF
pd
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢅ
ꢇꢈ ꢉꢊ ꢋ ꢌꢄ ꢊ ꢍ ꢋ ꢎ ꢏꢐ ꢊꢌ ꢋꢏ ꢎꢌ
ꢑꢊ ꢋ ꢄ ꢒ ꢈꢌꢋꢓꢋ ꢏ ꢔꢕꢋ ꢖꢕ ꢋ ꢎꢏ ꢐ ꢊꢌ ꢋꢏ ꢎꢌ
SCHS353 − JANUARY 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
R
C
L
S1
S2
L
50 pF
or
150 pF
t
Open
Closed
Closed
Open
S1
S2
PZH
Test
Point
t
t
1 kΩ
1 kΩ
en
R
t
L
PZL
From Output
Under Test
C
(see Note A)
t
t
Open
Closed
Open
PHZ
PLZ
L
50 pF
dis
Closed
50 pF
or
150 pF
t
or t
−−
Open
Open
pd
t
LOAD CIRCUIT
V
CC
Reference
Input
50%
V
CC
0 V
High-Level
Pulse
50%
50%
t
t
h
su
0 V
V
CC
t
Data
Input
w
90%
90%
50%
10%
50%
10%
V
CC
Low-Level
Pulse
0 V
50%
50%
t
t
f
r
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
Output
V
CC
V
CC
Control
(Low-Level
Enabling)
Input
50%
50%
50%
50%
0 V
V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
OH
≈V
CC
50%
≈V
CC
Output
Waveform 1
(See Note B)
In-Phase
Output
90%
t
50%
10%
50%
10%
10%
t
V
OL
V
OL
t
r
f
f
t
t
t
PZH
PHZ
PHL
90%
PLH
V
V
OH
V
Output
Waveform 2
(See Note B)
OH
90%
t
90%
Out-of-
Phase
Output
50%
10%
50%
10%
50%
≈0 V
OL
t
r
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. For clock inputs, f
is measured when the input duty cycle is 50%.
E. The outputs are measured one at a time, with one input transition per measurement.
max
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
are the same as t
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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