CD74HC595NSRG4 [TI]

HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, GREEN, PLASTIC, SOP-16;


型号：	CD74HC595NSRG4
厂家：	TEXAS INSTRUMENTS
描述：	HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, GREEN, PLASTIC, SOP-16 光电二极管输出元件逻辑集成电路触发器
文件：	总23页 (文件大小：1058K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SCHS353 − JANUARY 2004

DW, E, M, NS, OR SM PACKAGE

(TOP VIEW)

8-Bit Serial-In, Parallel-Out Shift

Wide Operating Voltage Range of 2 V to 6 V

High-Current 3-State Outputs Can Drive Up

To 15 LSTTL Loads

SER

Low Power Consumption, 80-µA Max I

Typical t = 14 ns

6-mA Output Drive at 5 V

12 RCLK

SRCLK

SRCLR

Low Input Current of 1 µA Max

Shift Register Has Direct Clear

GND

H′

description/ordering information

The CD74HC595 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage

storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial

output for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.

Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both

clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

PDIP − E

Tube of 25

Tube of 40

Reel of 2000

Tube of 40

Reel of 2500

Reel of 250

Reel of 2000

Tube of 80

Reel of 2000

CD74HC595E

CD74HC595DW

CD74HC595DWR

CD74HC595M

SOIC − DW

HC595M

−55°C to 125°C

CD74HC595M96

CD74HC595MT

CD74HC595NSR

CD74HC595SM

CD74HC595SM96

SOIC − M

HC595M

SOP − NS

HC595M

HJ595

SSOP − SM

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢅ

ꢇꢈ ꢉꢊ ꢋ ꢌꢄ ꢊ ꢍ ꢋ ꢎ ꢏꢐ ꢊꢌ ꢋꢏ ꢎꢌ

ꢑꢊ ꢋ ꢄ ꢒ ꢈꢌꢋꢓꢋ ꢏ ꢔꢕꢋ ꢖꢕ ꢋ ꢎꢏ ꢐ ꢊꢌ ꢋꢏ ꢎꢌ

SCHS353 − JANUARY 2004

FUNCTION TABLE

INPUTS

SER SRCLK SRCLR RCLK

FUNCTION

Outputs Q −Q are disabled.

Outputs Q −Q are enabled.

A H

Shift register is cleared.

First stage of the shift register goes low.

Other stages store the data of previous stage, respectively.

↑

First stage of the shift register goes high.

Other stages store the data of previous stage, respectively.

↑

Shift-register data is stored in the storage register.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCHS353 − JANUARY 2004

logic diagram (positive logic)

RCLK

SRCLR

SRCLK

SER

H′

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢑꢊ ꢋ ꢄ ꢒ ꢈꢌꢋꢓꢋ ꢏ ꢔꢕꢋ ꢖꢕ ꢋ ꢎꢏ ꢐ ꢊꢌ ꢋꢏ ꢎꢌ

SCHS353 − JANUARY 2004

timing diagram

SRCLK

SER

RCLK

SRCLR

H’

NOTE:

implies that the output is in 3-State mode.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCHS353 − JANUARY 2004

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Output clamp current, I

(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

O O CC

Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA

Continuous current through V

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA

Package thermal impedance, θ (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W

DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W

M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W

NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W

SM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

MIN NOM

MAX

UNIT

Supply voltage

1.5

= 2 V

= 4.5 V

= 6 V

3.15

4.2

High-level input voltage

= 2 V

0.5

1.35

1.8

= 4.5 V

= 6 V

Low-level input voltage

Input voltage

Output voltage

= 2 V

1000

500

400

125

‡

= 4.5 V

= 6 V

∆t/∆v

Input transition rise/fall time

Operating free-air temperature

−55

°C

NOTE 3: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

‡

If this device is used in the threshold region (from V max = 0.5 V to V min = 1.5 V), there is a potential to go into the wrong state from induced

grounding, causing double clocking. Operating with the inputs at t = 1000 ns and V

= 2 V does not damage the device; however, functionally,

the CLK inputs are not ensured while in the shift, count, or toggle operating modes.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCHS353 − JANUARY 2004

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

= -55°C TO

125°C

= -40°C TO

85°C

= 25°C

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

MIN

MAX

MIN

MAX

2 V

4.5 V

6 V

1.9 1.998

4.4 4.499

5.9 5.999

1.9

4.4

5.9

3.7

5.2

1.9

4.4

5.9

= −20 µA

, I

H′ OH

= −4 mA

3.98

4.3

3.84

5.34

V = V or V

I IH IL

4.5 V

6 V

Q −Q , I

= −6 mA

3.98

5.48

, I

H′ OH

= −5.2 mA

5.8

Q −Q , I

= −7.8 mA

5.8

2 V

4.5 V

6 V

0.002

0.001

0.17

0.15

0.1

= 20 µA

0.1

, I

H′ OL

= 4 mA

= 6 mA

= 5.2 mA

0.26

100

0.5

0.4

0.33

1000

V = V or V

4.5 V

6 V

Q −Q , I

0.4

, I

H′ OL

0.4

Q −Q , I

= 7.8 mA

0.4

V = V

or 0

6 V

1000

µA

= V

or 0, Q −Q

0.01

V = V

I CC

or 0,

= 0

160

2 V

to 6 V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCHS353 − JANUARY 2004

timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

= -55°C TO

125°C

= -40°C TO

85°C

= 25°C

UNIT

MIN

MAX

MIN

MAX

4.2

MIN

MAX

2 V

4.5 V

6 V

Clock frequency

Pulse duration

MHz

clock

2 V

100

120

100

4.5 V

6 V

120

150

113

100

125

SRCLK or RCLK high or low

SRCLR low

2 V

4.5 V

6 V

2 V

4.5 V

6 V

SER before SRCLK↑

2 V

†

4.5 V

6 V

SRCLK↑ before RCLK↑

Setup time

2 V

4.5 V

6 V

SRCLR low before RCLK↑

2 V

4.5 V

6 V

SRCLR high (inactive) before SRCLK↑

2 V

Hold time, SER after SRCLK↑

4.5 V

6 V

†

This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢅ

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ꢑꢊ ꢋ ꢄ ꢒ ꢈꢌꢋꢓꢋ ꢏ ꢔꢕꢋ ꢖꢕ ꢋ ꢎꢏ ꢐ ꢊꢌ ꢋꢏ ꢎꢌ

SCHS353 − JANUARY 2004

switching characteristics over recommended operating free-air temperature range, C = 50 pF

(unless otherwise noted) (see Figure 1)

= -55°C TO

125°C

= -40°C TO

85°C

= 25°C

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN

TYP

MAX

MIN

MAX

MIN

MAX

2 V

4.5 V

6 V

4.2

MHz

max

2 V

160

240

200

4.5 V

6 V

SRCLK

RCLK

SRCLR

H′

2 V

150

225

187

4.5 V

6 V

Q −Q

2 V

175

261

219

4.5 V

6 V

PHL

H′

2 V

150

225

187

4.5 V

6 V

Q −Q

2 V

200

300

250

4.5 V

6 V

Q −Q

dis

2 V

4.5 V

6 V

Q −Q

2 V

110

4.5 V

6 V

H′

switching characteristics over recommended operating free-air temperature range, C = 150 pF

(unless otherwise noted) (see Figure 1)

= -55°C TO

125°C

= -40°C TO

85°C

= 25°C

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN

TYP

MAX

200

MIN

MAX

300

MIN

MAX

250

2 V

4.5 V

6 V

RCLK

Q −Q

2 V

200

298

250

4.5 V

6 V

Q −Q

2 V

210

315

265

Q −Q

4.5 V

6 V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCHS353 − JANUARY 2004

operating characteristics, T = 25°C

PARAMETER

TEST CONDITIONS

TYP

UNIT

Power dissipation capacitance

No load

400

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢑꢊ ꢋ ꢄ ꢒ ꢈꢌꢋꢓꢋ ꢏ ꢔꢕꢋ ꢖꢕ ꢋ ꢎꢏ ꢐ ꢊꢌ ꢋꢏ ꢎꢌ

SCHS353 − JANUARY 2004

PARAMETER MEASUREMENT INFORMATION

PARAMETER

50 pF

150 pF

Open

Closed

Open

PZH

Test

Point

1 kΩ

PZL

From Output

Under Test

(see Note A)

Open

Closed

Open

PHZ

PLZ

50 pF

dis

Closed

50 pF

150 pF

or t

−−

Open

LOAD CIRCUIT

Reference

Input

50%

0 V

High-Level

Pulse

50%

0 V

Data

Input

90%

50%

10%

50%

10%

Low-Level

Pulse

0 V

50%

0 V

VOLTAGE WAVEFORMS

SETUP AND HOLD AND INPUT RISE AND FALL TIMES

VOLTAGE WAVEFORMS

PULSE DURATIONS

Output

Control

(Low-Level

Enabling)

Input

50%

0 V

PLH

PHL

90%

PLZ

PZL

≈V

50%

≈V

Output

Waveform 1

(See Note B)

In-Phase

Output

90%

50%

10%

50%

10%

PZH

PHZ

PHL

90%

PLH

Output

Waveform 2

(See Note B)

90%

Out-of-

Phase

Output

50%

10%

50%

10%

50%

≈0 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS

VOLTAGE WAVEFORMS

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

NOTES: A.

C includes probe and test-fixture capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.

D. For clock inputs, f

is measured when the input duty cycle is 50%.

E. The outputs are measured one at a time, with one input transition per measurement.

max

and t

are the same as t

PLZ

PZL

PLH

PHZ

PZH

PHL

dis

are the same as t

are the same as t .

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device

CD74HC595DW

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-55 to 125

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

ACTIVE

SOIC

PDIP

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

HC595M

CD74HC595DWE4

CD74HC595DWG4

CD74HC595DWR

CD74HC595DWRE4

CD74HC595DWRG4

CD74HC595E

ACTIVE

Green (RoHS

& no Sb/Br)

HC595M

CD74HC595E

HC595M

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Pb-Free

(RoHS)

CD74HC595EE4

CD74HC595M

Pb-Free

(RoHS)

N / A for Pkg Type

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

CD74HC595M96

CD74HC595M96E4

CD74HC595M96G4

CD74HC595ME4

CD74HC595MG4

CD74HC595MT

2500

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

250

Green (RoHS

& no Sb/Br)

CD74HC595MTE4

CD74HC595MTG4

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-55 to 125

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

CD74HC595NSR

CD74HC595NSRE4

CD74HC595NSRG4

CD74HC595SM96

CD74HC595SM96E4

CD74HC595SM96G4

ACTIVE

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

HC595M

ACTIVE

2000

Green (RoHS

& no Sb/Br)

HC595M

HJ595

Green (RoHS

& no Sb/Br)

SSOP

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

HJ595

Green (RoHS

& no Sb/Br)

HJ595

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CD74HC595DWR

CD74HC595M96

CD74HC595NSR

CD74HC595SM96

SOIC

2000

2500

2000

330.0

16.4

10.75 10.7

2.7

2.1

2.5

12.0

8.0

16.0

6.5

8.2

10.3

10.5

6.6

12.0

SSOP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

CD74HC595DWR

CD74HC595M96

CD74HC595NSR

CD74HC595SM96

SOIC

2000

2500

2000

367.0

333.2

367.0

345.9

367.0

38.0

28.6

38.0

SSOP

Pack Materials-Page 2

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

0,15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

0,25

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

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CD74HC595NSRG4 [TI]

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