CD74HC7046AMTG4 [TI]
Phase-Locked Loop with VCO and Lock Detector; 带有VCO及锁定检测锁相环型号: | CD74HC7046AMTG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | Phase-Locked Loop with VCO and Lock Detector |
文件: | 总28页 (文件大小:446K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CD74HC7046A,
CD74HCT7046A
Data sheet acquired from Harris Semiconductor
SCHS218C
Phase-Locked Loop
with VCO and Lock Detector
February 1998 - Revised October 2003
Features
Description
• Center Frequency of 18MHz (Typ) at V
Minimum Center Frequency of 12MHz at V
= 5V,
The CD74HC7046A and CD74HCT7046A high-speed
silicon-gate CMOS devices, specified in compliance with
JEDEC Standard No. 7A, are phase-locked-loop (PLL)
circuits that contain a linear voltage-controlled oscillator
(VCO), two-phase comparators (PC1, PC2), and a lock
detector. A signal input and a comparator input are common
to each comparator. The lock detector gives a HIGH level at
pin 1 (LD) when the PLL is locked. The lock detector
CC
CC = 4.5V
[ /Title
(CD74
HC704
6A,
CD74
HCT70
46A)
• Choice of Two Phase Comparators
- Exclusive-OR
- Edge-Triggered JK Flip-Flop
• Excellent VCO Frequency Linearity
• VCO-Inhibit Control for ON/OFF Keying and for Low
Standby Power Consumption
capacitor must be connected between pin 15 (C ) and pin
LD
8 (Gnd). For a frequency range of 100kHz to 10MHz, the
lock detector capacitor should be 1000pF to 10pF,
respectively.
• Minimal Frequency Drift
/Sub-
• Zero Voltage Offset Due to Op-Amp Buffer
ject
The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to
small voltage signals. A self-bias input circuit keeps small
voltage signals within the linear region of the input amplifiers.
With a passive low-pass filter, the 7046A forms a second-
order loop PLL. The excellent VCO linearity is achieved by
the use of linear op-amp techniques.
• Operating Power-Supply Voltage Range
(Phase-
Locked
Loop
- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Ordering Information
TEMP. RANGE
o
• Significant Power Reduction Compared to LSTTL
Logic ICs
PART NUMBER
CD74HC7046AE
( C)
PACKAGE
16 Ld PDIP
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• HC Types
CD74HC7046AM
CD74HC7046AMT
CD74HC7046AM96
CD74HCT7046AE
CD74HCT7046AM
CD74HCT7046AMT
CD74HCT7046AM96
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
Applications
• FM Modulation and Demodulation
• Frequency Synthesis and Multiplication
• Frequency Discrimination
• Tone Decoding
• Data Synchronization and Conditioning
• Voltage-to-Frequency Conversion
• Motor-Speed Control
• Related Literature
- AN8823, CMOS Phase-Locked-Loop Application
Using the CD74HC/HCT7046A and
CD74HC/HCT7046A
0.1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD74HC7046A, CD74HCT7046A
Functional Diagram
Pinout
CD74HC7046A, CD74HCT7046A
(PDIP, SOIC)
TOP VIEW
2
PC1
3
OUT
OUT
COMP
SIG
15
13
1
IN
IN
C
LD
LD
1
2
3
4
5
6
7
8
16 V
15 C
φ
CC
14
PC2
LD
PC1
OUT
LD
COMP
VCO
14 SIG
IN
IN
13 PC2
OUT
INH
OUT
6
7
C1
C1
A
B
12 R
2
1
4
C1
A
11
R
11
12
9
VCO
DEM
OUT
R
1
2
C1
B
10 DEM
OUT
VCO
10
R
9
VCO
GND
IN
OUT
VCO
IN
5
INH
C1
6
7
4
3
14
SIG
COMP
C1
C1
B
IN
IN
A
PC1
OUT
2
V
REF
150Ω
R2
R1
12
-
1.5K
LOCK DETECTOR
VCO
R2
LOCK
DETECTOR
OUTPUT
1
11
15
C
R1
LD
LOCK
DETECTOR
CAPACITOR
V
-
+
CC
UP
Q
Q
D
p
10
CP
R
R3
C2
13
PC2
OUT
D
-
R5
+
n
Q
Q
V
CC
D
GND
DOWN
CP
R
D
INH
5
VCO
9
IN
FIGURE 1. LOGIC DIAGRAM
2
CD74HC7046A, CD74HCT7046A
Phase Comparator 1 (PC1)
This is an Exclusive-OR network. The signal and comparator
Pin Descriptions
PIN NO.
SYMBOL
NAME AND FUNCTION
Lock Detector Output (Active High)
Phase Comparator 1 Output
Comparator Input
input frequencies (f ) must have a 50% duty factor to obtain
i
1
2
LD
the maximum locking range. The transfer characteristic of
PC1, assuming ripple (f = 2f ) is suppressed, is:
r
i
PC1
OUT
V
= (V /π) (φ
CC
- φ ) where V
COMPIN
3
COMP
DEMOUT
SIGIN
DEMOUT
= V
IN
is the demodulator output at pin 10; V
DEMOUT
PC1OUT
4
VCO
VCO Output
OUT
(via low-pass filter).
5
INH
Inhibit Input
The average output voltage from PC1, fed to the VCO input
via the low-pass filter and seen at the demodulator output at
6
C1
C1
Capacitor C1 Connection A
Capacitor C1 Connection B
Ground (0V)
A
pin 10 (V
), is the resultant of the phase differences
DEMOUT
7
B
of signals (SIG ) and the comparator input (COMP ) as
IN
IN
8
Gnd
shown in Figure 2. The average of V
is equal to 1/2 V
DEM
CC
when there is no signal or noise at SIG , and with this input
the VCO oscillates at the center frequency (f ). Typical wave-
o
IN
9
VCO
DEM
VCO Input
IN
10
11
12
13
14
15
16
Demodulator Output
Resistor R1 Connection
Resistor R2 Connection
Phase Comparator 2 Output
Signal Input
forms for the PC1 loop locked at f shown in Figure 3.
OUT
1
o
R
R
The frequency capture range (2f ) is defined as the fre-
c
quency range of input signals on which the PLL will lock if it
2
was initially out-of-lock. The frequency lock range (2f ) is
L
PC2
OUT
defined as the frequency range of input signals on which the
loop will stay locked if it was initially in lock. The capture
range is smaller or equal to the lock range.
SIG
IN
C
Lock Detector Capacitor Input
Positive Supply Voltage
LD
With PC1, the capture range depends on the low-pass filter
characteristics and can be made as large as the lock range.
This configuration retains lock behavior even with very noisy
input signals. Typical of this type of phase comparator is that
it can lock to input frequencies close to the harmonics of the
VCO center frequency.
V
CC
General Description
VCO
The VCO requires one external capacitor C1 (between C1
A
Phase Comparator 2 (PC2)
and C1 ) and one external resistor R1 (between R1 and
B
Gnd) or two external resistors R1 and R2 (between R1 and
Gnd, and R2 and Gnd). Resistor R1 and capacitor C1 deter-
mine the frequency range of the VCO. Resistor R2 enables
the VCO to have a frequency offset if required. See logic dia-
gram, Figure 1.
This is a positive edge-triggered phase and frequency detec-
tor. When the PLL is using this comparator, the loop is con-
trolled by positive signal transitions and the duty factors of
SIGIN and COMP are not important. PC2 comprises two
IN
D-type flip-flops, control-gating and a three-state output
stage. The circuit functions as an up-down counter (Figure
The high input impedance of the VCO simplifies the design
of low-pass filters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is pro-
1) where SIG causes an up-count and COMP a down-
IN IN
count. The transfer function of PC2, assuming ripple (f = f )
r
i
is suppressed, is:
vided at pin 10 (DEM
niques where the DEM
lower than the VCO input voltage, here the DEM
). In contrast to conventional tech-
voltage is one threshold voltage
V
= (V /4π) (φ
- φ ) where V
COMPIN
OUT
OUT
DEMOUT
CC SIGN
DEMOUT
= V
is the demodulator output at pin 10; V
(via low-pass filter).
DEMOUT
PC2OUT
voltage
OUT
equals that of the VCO input. If DEM
is used, a load
OUT
resistor (R ) should be connected from DEM
The average output voltage from PC2, fed to the VCO via the
low-pass filter and seen at the demodulator output at pin 10
(V
SIG and COMP as shown in Figure 4. Typical waveforms
for the PC2 loop locked at f are shown in Figure 5.
to Gnd; if
S
OUT
should be left open. The VCO output
unused, DEM
OUT
), is the resultant of the phase differences of
DEMOUT
(VCO
) can be connected directly to the comparator
OUT
IN IN
input (COMP ), or connected via a frequency-divider. The
IN
o
VCO output signal has a specified duty factor of 50%. A
LOW level at the inhibit input (INH) enables the VCO, while a
HIGH level disables the VCO to minimize standby power
consumption.
When the frequencies of SIG and COMP are equal but
IN IN
the phase of SIG leads that of COMP , the p-type output
IN IN
is held “ON” for a time corresponding to
driver at PC2
OUT
the phase differences (φ
). When the phase of SIG
DEMOUT
lags that of COMP , the n-type driver is held “ON”.
IN
Phase Comparators
IN
The signal input (SIG ) can be directly coupled to the self-
IN
When the frequency of SIG is higher than that of COMP ,
the p-type output driver is held “ON” for most of the input sig-
nal cycle time, and for the remainder of the cycle both n-type
IN IN
biasing amplifier at pin 14, provided that the signal swing is
between the standard HC family input logic levels, Capaci-
tive coupling is required for signals with smaller swings.
and p-type drivers are “OFF” (three-state). If the SIG fre-
IN
3
CD74HC7046A, CD74HCT7046A
quency is lower than the COMP frequency, then it is the n- biased and the time constant in the path that charges the
IN
type driver that is held “ON” for most of the cycle. Subse- lock detector capacitor is T = (150Ω x C ).
LD
quently, the voltage at the capacitor (C2) of the low-pass filter
During the fall time of the pulse the capacitor discharges
through the 1.5kΩ and the 150Ω resistors and the channel
resistance of the n-device of the NOR gate to ground
connected to PC2
varies until the signal and comparator
OUT
inputs are equal in both phase and frequency. At this stable
point the voltage on C2 remains constant as the PC2 output is
in three-state and the VCO input at pin 9 is a high impedance.
(T = (1.5kΩ + 150Ω + Rn-channel) x C ).
LD
The waveform preset at the capacitor resembles a sawtooth
as shown in Figure 7. The lock detector capacitor value is
determined by the VCO center frequency. The typical range
of capacitor for a frequency of 10MHz is about 10pF and for
a frequency of 100kHz is about 1000pF. The chart in Figure
8 can be used to select the proper lock detector capacitor
value. As long as the loop remains locked and tracking, the
level of the sawtooth will not go below the switching thresh-
old of the Schmitt-trigger inverter. If the loop breaks lock, the
width of the error pulse will be wide enough to allow the saw-
tooth waveform to go below threshold and a level change at
the output of the Schmitt trigger will indicate a loss of lock,
as shown in Figure 9. The lock detector capacitor also acts
to filter out small glitches that can occur when the loop is
either seeking or losing lock.
Thus, for PC2, no phase difference exists between SIG
IN
and COMP over the full frequency range of the VCO.
IN
Moreover, the power dissipation due to the low-pass filter is
reduced because both p-type and n-type drivers are “OFF”
for most of the signal input cycle. It should be noted that the
PLL lock range for this type of phase comparator is equal to
the capture range and is independent of the low-pass filter.
With no signal present at SIG , the VCO adjusts, via PC2,
IN
to its lowest frequency.
Lock Detector Theory of Operation
Detection of a locked condition is accomplished by a NOR
gate and an envelope detector as shown in Figure 6. When
the PLL is in Lock, the output of the NOR gate is High and
the lock detector output (Pin 1) is at a constant high level. As
the loop tracks the signal on Pin 14 (signal in), the NOR gate
outputs pulses whose widths represent the phase differ-
ences between the VCO and the input signal. The time
between pulses will be approximately equal to the time con-
stant of the VCO center frequency. During the rise time of
the pulse, the diode across the 1.5kΩ resistor is forward
Note: When using phase comparator 1, the detector will only
indicate a lock condition on the fundamental frequency and
not on the harmonics, which PC1 will also lock on. If a detec-
tion of lock is needed over the harmonic locking range of
PC1, then the lock detector output must be OR-ed with the
output of PC1.
V
CC
SIG
IN
V
DEMOUT (AV)
COMP
IN
VCO
OUT
1/2 V
CC
PC1
OUT
V
CC
VCO
IN
0
GND
o
o
o
φDEMOUT
0
90
180
FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 1, LOOP LOCKED AT f
o
V
= V
= (V /π) (φSIGIN - φCOM-
DEMOUT
PC1OUT CC
); φDEMOUT = (φSIGIN - φCOMPIN
)
PIN
4
CD74HC7046A, CD74HCT7046A
V
CC
SIG
IN
V
COMP
DEMOUT (AV)
IN
VCO
OUT
V
CC
1/2 V
CC
PC2
OUT
GND
HIGH IMPEDANCE OFF - STATE
VCO
IN
0
PCP
OUT
o
o
o
φDEMOUT
-360
0
360
FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 2, LOOP LOCKED AT f
o
V
= V
= (V /π) (φSIGIN - φCOM-
DEMOUT
PC2OUT CC
); φDEMOUT = (φSIGIN - φCOMPIN
)
PIN
7046 LOCK DETECTOR CIRCUITRY
PHASE DIFFERENCE
SIG
IN
UP
FF
PIN 1
1.5kΩ
150Ω
LOCK DETECTOR
OUTPUT
DN
FF
COMP
IN
C
LD
PIN 15
LOCK DETECTOR
CAPACITOR
FIGURE 6. CD74HC/HCT7046A LOCK DETECTOR CIRCUIT
LOCK
PIN 1
DETECTOR
1.5kΩ
150Ω
OUTPUT
PIN 15
LOCK
C
LD
DETECTOR
CAPACITOR
V
V
CAP
TH
FIGURE 7. WAVEFORM PRESENT AT LOCK DETECTOR CAPACITOR WHEN IN LOCK
5
CD74HC7046A, CD74HCT7046A
10M
1M
100K
10K
1K
100
10
10
100
1K
10K
100K
1M
10M
100M
f, VCO CENTER FREQUENCY (HZ)
FIGURE 8. LOCK DETECTOR CAPACITOR SELECTION CHART
LOSS OF LOCK
PIN 1
LOCK
DETECTOR
OUTPUT
1.5kΩ
150Ω
PIN 15
LOCK
C
LD
DETECTOR
CAPACITOR
V
V
CAP
TH
FIGURE 9. WAVEFORM PRESENT AT LOCK DETECTOR CAPACITOR WHEN UNLOCKED
6
CD74HC7046A, CD74HCT7046A
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
67
73
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
VCO SECTION
INH High Level Input
Voltage
V
-
-
-
-
3
4.5
6
2.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.1
-
2.1
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
INH Low Level Input
Voltage
V
3
-
0.9
1.35
1.8
-
-
0.9
1.35
1.8
-
-
0.9
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
VCO
High Level
V
V
or V
IL
-0.02
3
2.9
2.9
2.9
OUT
OH
IH
Output Voltage
CMOS Loads
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
VCO
High Level
-
-
-
-
-
-
-
OUT
Output Voltage
TTL Loads
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
VCO
Low Level
V
V or V
IH IL
2
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OUT
OL
Output Voltage
CMOS Loads
4.5
6
VCO
Low Level
-
OUT
Output Voltage
TTL Loads
4
4.5
6
0.26
0.26
0.40
0.40
0.33
0.33
0.47
0.47
0.4
0.4
0.54
0.54
5.2
4
C1A, C1B Low Level
Output Voltage
(Test Purposes Only)
V
V
V
or
IL
4.5
6
OL
OL
5.2
7
CD74HC7046A, CD74HCT7046A
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
O
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
I
INH VCO Input
IN
I
V
GND
or
-
6
-
-
±0.1
-
±1
-
±1
µA
I
CC
Leakage Current
R1 Range (Note 2)
R2 Range (Note 2)
-
-
-
-
-
-
-
4.5
4.5
3
3
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
kΩ
kΩ
pF
pF
pF
V
-
-
C1 Capacitance
Range
-
No
Limit
4.5
6
40
-
VCO Operating
IN
Voltage Range
-
Over the range
specified for R1 for
LinearitySeeFigure
8, and 35 - 38
3
1.1
1.1
1.1
1.9
3.2
4.6
4.5
6
V
V
(Note 3)
PHASE COMPARATOR SECTION
SIG , COMP
IN
DC Coupled
High-Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
3.15
4.2
-
-
-
-
-
-
1.5
3.15
4.2
-
-
-
1.5
3.15
4.2
-
-
-
V
V
V
IN
IH
SIG , COMP
IN
DC Coupled
Low-Level Input
Voltage
V
-
2
4.5
6
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
V
V
V
IN
IL
LD, PCn
OUT
Level Output Voltage
CMOS Loads
High-
V
V
or V
-0.02
2
4.5
6
1.9
4.4
-
-
-
-
-
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
OH
IL
IH
5.9
5.9
LD, PCn
OUT
Level Output Voltage
TTL Loads
High-
V
V
V
or V
or V
-4
4.5
6
3.98
5.48
3.84
5.34
OH
IL
IL
IH
IH
-5.2
LD, PCn
OUT
Level Output Voltage
CMOS Loads
Low-
V
0.02
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
0.1
0.1
LD, PCn
OUT
Level Output Voltage
TTL Loads
Low-
V
V
or V
IH
4
4.5
6
0.26
0.26
0.33
0.33
OL
IL
5.2
SIG , COMP Input
IN IN
Leakage Current
I
V
or
-
2
3
-
-
-
-
-
-
-
-
-
-
±3
±7
-
-
-
-
-
±4
±9
-
-
-
-
-
±5
µA
µA
µA
µA
µA
I
CC
GND
±11
±29
±45
±10
4.5
6
±18
±30
±0.5
±23
±38
±5
PC2
Three-State
Off-State Current
I
V
or V
IH
-
6
OUT
OZ
IL
SIG , COMP Input
Resistance
R
V at Self-Bias
I
Operation Point:
3
4.5
6
-
-
-
800
250
150
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
kΩ
kΩ
kΩ
IN
IN
I
∆V = 0.5V,
I
See Figure 8
DEMODULATOR SECTION
Resistor Range
R
at R > 300kΩ
Leakage Current
Can Influence
3
4.5
6
10
10
10
-
-
-
300
300
300
-
-
-
-
-
-
-
-
-
-
-
-
kΩ
kΩ
kΩ
S
S
V
DEMOUT
8
CD74HC7046A, CD74HCT7046A
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
O
(V)
MIN
TYP
±30
±20
±10
MAX
MIN
MAX
MIN
MAX
UNITS
mV
I
Offset Voltage VCO
V
V = V
VCOIN
=
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IN
OFF
I
V
to V
CC
2
DEM
4.5
6
mV
mV
Values taken over
Range
R
S
See Figure 15
Dynamic Output
Resistance at
R
V
=
3
4.5
6
-
-
-
-
25
25
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Ω
Ω
O
DEMOUT
V
CC
-
-
2
DEM
OUT
-
-
Ω
Quiescent Device
Current
I
Pins 3, 5 and 14
at V Pin 9 at
6
8
80
160
µA
CC
CC
GND, I at Pins 3
I
and 14 to be
excluded
HCT TYPES
VCO SECTION
INH High Level Input
Voltage
V
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
INH Low Level Input
Voltage
V
-
4.5 to
5.5
IL
VCO
High Level
V
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.5
5.5
4.4
4.4
4.4
OUT
OH
IH
IH
IH
IL
IL
IL
Output Voltage
CMOS Loads
VCO
High Level
-4
0.02
4
3.98
-
-
-
-
-
3.84
-
3.7
-
V
V
OUT
Output Voltage
TTL Loads
VCO
Low Level
V
or V
-
-
-
-
0.1
-
-
-
-
0.1
0.33
0.47
±1
-
-
-
-
0.1
0.4
0.54
±1
OUT
OL
Output Voltage
CMOS Loads
VCO
Low Level
0.26
0.40
±0.1
V
OUT
Output Voltage
TTL Loads
C1A, C1B Low Level
Output Voltage
(Test Purposes Only)
V
or V
4
V
OL
INH VCO Input
IN
I
Any Voltage
µA
I
Leakage Current
Between V
and
CC
GND
R1 Range (Note 2)
R2 Range (Note 2)
-
-
-
-
-
-
-
4.5
4.5
4.5
3
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
kΩ
kΩ
pF
-
-
C1 Capacitance
Range
40
No
Limit
VCO Operating
IN
Voltage Range
-
Over the range
specified for R1 for
LinearitySeeFigure
8, and 35 - 38
4.5
1.1
-
3.2
-
-
-
-
V
(Note 3)
PHASE COMPARATOR SECTION
SIG , COMP
IN
DC Coupled
V
-
-
4.5 to
5.5
3.15
-
-
3.15
-
3.15
-
V
IN
IH
High-Level Input
Voltage
9
CD74HC7046A, CD74HCT7046A
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
SIG , COMP
V
IL
-
-
4.5 to
5.5
-
-
1.35
-
1.35
-
1.35
V
IN
DC Coupled
IN
Low-Level Input
Voltage
LD, PCn
OUT
Level Output Voltage
CMOS Loads
High-
V
V
V
V
V
or V
or V
or V
or V
-
-
-
-
-
4.5
4.5
4.5
4.5
5.5
4.4
-
-
-
-
-
-
4.4
-
4.4
3.7
-
-
V
V
OH
IL
IL
IL
IL
IH
IH
IH
IH
LD, PCn
OUT
Level Output Voltage
TTL Loads
High-
V
3.98
-
3.84
-
-
OH
LD, PCn
OUT
Level Output Voltage
CMOS Loads
Low-
V
-
-
-
0.1
0.26
±30
-
-
0.1
0.33
±38
0.1
0.4
±45
V
OL
LD, PCn
OUT
Level Output Voltage
TTL Loads
Low-
V
-
V
OL
SIG , COMP Input
IN IN
I
Any
µA
I
Leakage Current
Voltage
Between
V
and
CC
GND
PC2
Three-State
Off-State Current
I
V
or V
IH
-
5.5
4.5
-
-
-
±0.5
±5
-
-
-
-
±10
µA
kΩ
OUT
OZ
IL
SIG , COMP Input
R
V at Self-Bias
250
-
-
-
IN
IN
I
I
Resistance
Operation Point:
∆V, 0.5V,
See Figure 8
DEMODULATOR SECTION
Resistor Range
R
at R > 300kΩ
Leakage Current
Can Influence
4.5
4.5
10
-
-
300
-
-
-
-
-
-
-
-
-
kΩ
S
S
V
DEMOUT
V = V =
VCOIN
Offset Voltage VCO
V
±20
mV
IN
OFF
I
V
to V
CC
2
DEM
Values taken over
Range
R
S
See Figure 15
Dynamic Output
Resistance at
R
V
=
4.5
5.5
-
25
-
-
-
-
-
Ω
O
DEMOUT
V
CC
2
DEM
OUT
Quiescent Device
Current
I
V
or
-
-
-
-
-
8
-
-
80
-
-
160
490
µA
µA
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 4)
V
4.5 to
5.5
100
360
450
CC
-2.1
(Exclud-
ing Pin 5)
NOTES:
2. The value for R1 and R2 in parallel should exceed 2.7kΩ; R1 and R2 values above 300kΩ may contribute to frequency shift due to leakage
currents.
3. The maximum operating voltage can be as high as V
-0.9V, however, this may result in an increased offset voltage.
CC
4. For dual-supply systems theoretical worst case (V = 2.4V, V
= 5.5V) specification is 1.8mA.
CC
I
10
CD74HC7046A, CD74HCT7046A
HCT Input Loading Table
INPUT
UNIT LOADS
INH
1
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
Switching Specifications C = 50pF, Input t , t = 6ns
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
PHASE COMPARATOR SECTION
Propagation Delay
SIG , COMP to PC
V
(V) MIN
TYP MAX MIN MAX
MIN
MAX
UNITS
CC
t
, t
PLH PHL
2
-
-
-
200
40
34
75
15
13
280
56
48
325
65
55
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
250
50
43
95
19
16
350
70
60
405
81
69
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
300
60
51
110
22
19
420
84
71
490
98
83
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
mV
mV
mV
IN IN 1OUT
4.5
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Output Transition Time
Output Enable Time, SIG
t
, t
THL TLH
2
-
4.5
6
-
-
,
t
t
, t
PZH PZL
2
-
IN
COMP to PC2
IN OUT
4.5
6
-
-
Output Disable Time, SIG
,
, t
2
-
IN
PHZ PLZ
COMP to PC2
IN OUT
4.5
6
-
-
AC Coupled Input Sensitivity (
V
3
11
15
33
P-
I(P-P)
) at SIG or COMP
IN
P
IN
4.5
6
-
-
-
-
-
-
VCO SECTION
o
Frequency Stability with
Temperature Change
∆f
∆T
R
= 100kΩ,
3
4.5
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ 0.11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
%/ C
1
R = ∞
2
o
%/ C
o
-
-
%/ C
Maximum Frequency
f
C
R
= 50pF
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
MAX
1
= 3.5kΩ
1
4.5
6
-
24
-
R = ∞
2
-
C
= 0pF
3
-
-
1
R
= 9.1kΩ
1
4.5
6
-
38
-
R = ∞
2
-
Center Frequency
Frequency Linearity
f
C = 40pF
3
7
12
14
-
10
17
21
-
o
1
R = 3kΩ
1
4.5
6
R = ∞
2
VCO = V /2
IN
CC
∆f
R
= 100kΩ
1
3
VCO
R = ∞
2
4.5
6
-
0.4
-
%
C
= 100pF
1
-
%
11
CD74HC7046A, CD74HCT7046A
Switching Specifications C = 50pF, Input t , t = 6ns (Continued)
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
PARAMETER
Offset Frequency
V
(V) MIN
TYP MAX MIN MAX
MIN
MAX
UNITS
kHz
CC
R
C
= 220kΩ
3
-
-
400
-
-
-
-
-
-
-
-
-
-
-
-
2
= 1nF
1
4.5
6
-
-
-
-
-
-
kHz
kHz
DEMODULATOR SECTION
vs f
V
R = 100kΩ
1
3
4.5
6
-
-
-
-
330
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
mV/kHz
mV/kHz
mV/kHz
OUT
IN
R = ∞
2
C
= 100pF
1
R
= 10kΩ
5
R
= 100kΩ
3
C
= 100pF
2
HCT TYPES
PHASE COMPARATOR SECTION
Propagation Delay
t
, t
PLH PHL
SIG , COMP to PC
4.5
4.5
4.5
-
-
-
-
-
-
45
15
60
-
-
-
56
19
75
-
-
-
68
22
90
ns
ns
ns
IN IN 1OUT
Output Transition Time
t
, t
THL TLH
Output Enable Time, SIG
,
t
, t
PZH PZL
IN
COMP to PC2
IN OUT
Output Disable Time, SIG
,
t
, t
4.5
-
-
70
-
86
-
105
ns
IN
PHZ PLZ
COMP to PCZ
IN
OUT
AC Coupled Input Sensitivity
) at SIG or COMP
V
3
4.5
6
-
-
-
11
15
33
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
mV
mV
mV
I(P-P)
(
P-P
IN
IN
VCO SECTION
o
Frequency Stability with
Temperature Change
∆f
∆T
R
= 100kΩ,
4.5
4.5
-
-
-
-
-
Typ 0.11
-
-
-
-
%/ C
1
R = ∞
2
Maximum Frequency
f
C
R
= 50pF
24
-
-
-
-
-
-
MHz
MHz
MHz
MAX
1
= 3.5kΩ
1
R = ∞
2
C
= 0pF
4.5
4.5
-
38
17
-
-
-
-
-
-
1
R
= 9.1kΩ
1
R = ∞
2
Center Frequency
f
C = 40pF
12
o
1
R = 3kΩ
1
R = ∞
2
VCO = V /2
IN CC
Frequency Linearity
Offset Frequency
∆f
R
= 100kΩ
1
4.5
4.5
-
-
0.4
-
-
-
-
-
-
-
-
-
-
%
VCO
R = ∞
2
C
= 100pF
1
R
= 220kΩ
400
kHz
2
C
= 1nF
1
DEMODULATOR SECTION
vs f
V
R = 100kΩ
1
4.5
-
330
-
-
-
-
-
mV/kHz
OUT
IN
R = ∞
2
C
= 100pF
1
R
= 10kΩ
5
R
= 100kΩ
3
C
= 100pF
2
12
CD74HC7046A, CD74HCT7046A
Test Circuits and Waveforms
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 10. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 11. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
Typical Performance Curves
8
10
R1 = 2.2K
I
I
7
6
5
R1 = 22K
R1 = 220K
R1 = 2.2M
R1 = 11M
10
10
10
∆V
I
4
3
2
10
10
10
VCO = 0.5 V
IN CC
V
= 4.5V
10
1
CC
R2 = ∞
SELF-BIAS OPERATING POINT
2
3
4
5
6
1
10
10
10
10
10
10
CAPACITANCE, C1 (pF)
V
I
FIGURE 12. TYPICAL INPUT RESISTANCE CURVE AT
FIGURE 13. HC7046A TYPICAL CENTER FREQUENCY vs R1, C1
SIG , COMP
IN
IN
8
7
8
10
10
R1 = 3K
R1 = 1.5K
R1 = 15K
R1 = 150K
R1 = 1.5M
R1 = 30K
R1 = 330K
R1 = 3M
R1 = 15M
10
7
10
6
5
6
10
10
R1 = 7.5M
5
10
10
4
3
2
4
10
10
10
10
3
10
2
10
VCO = 0.5 V
IN CC
VCO = 0.5 V
IN
CC
V
= 6.0V
V
= 3.0V
CC
10
1
CC
10
R2 = ∞
R2 = ∞
10
1
2
3
4
5
6
2
10
3
4
5
6
1
1
10
10
10
10
10
10
10
10
10
10
CAPACITANCE, C1 (pF)
CAPACITANCE, C1 (pF)
FIGURE 14. HC7046A TYPICAL CENTER FREQUENCY vs R1, C1
FIGURE 15. HC7046A TYPICAL CENTER FREQUENCY vs R1, C1
13
CD74HC7046A, CD74HCT7046A
Typical Performance Curves (Continued)
8
7
8
10
10
R1 = 2.2K
R1 = 22K
R1 = 220K
R1 = 2.2M
R1 = 11M
R1 = 3K
R1 = 30K
R1 = 300K
R1 = 3M
R1 = 15M
10
7
6
5
4
3
2
10
10
10
10
10
10
6
5
10
10
4
3
2
10
10
10
VCO = 0.5 V
IN
CC
VCO = 0.5 V
IN
CC
V
= 4.5V
10
1
CC
V
= 5.5V
CC
10
1
R2 = ∞
R2 = ∞
2
3
4
5
6
1
10
2
3
4
5
6
10
10
10
10
10
1
10
10
10
10
10
10
CAPACITANCE, C1 (pF)
CAPACITANCE, C1 (pF)
FIGURE 16. HCT7046A TYPICAL CENTER FREQUENCY vs R1, C1
FIGURE 17. HCT7046A TYPICAL CENTER FREQUENCY vs R1, C1
90
140
C1 = 50pF
C1 = 0.1µF
R1 = 1.5M
R2 = ∞
V
= 6V
CC
V
= 6V
CC
80
R1 = 1.5M
R2 = ∞
120
100
70
60
V
= 4.5V
CC
V
= 4.5V
CC
80
60
40
50
40
V
= 3V
CC
V
= 3V
CC
30
20
10
20
0
1
2
3
4
5
6
0
1
2
3
4
5
6
VCO (V)
IN
VCO (V)
IN
FIGURE 18. HC7046A TYPICAL VCO FREQUENCY vs VCO
FIGURE 19. HC7046A TYPICAL VCO FREQUENCY vs VCO
IN
IN
(R1 = 1.5MΩ, C1 = 0.1µF)
800
18
C1 = 0.1µF
R1 = 150K
R2 = ∞
V = 6V
CC
C1 = 0.1µF
R1 = 5.6k
R2 = ∞
V
= 6V
CC
16
700
600
500
V
= 4.5V
CC
14
12
V
= 3V
CC
V
= 4.5V
CC
10
8
400
300
200
100
V
= 3V
CC
6
4
2
0
1
2
3
4
5
6
0
1
2
3
4
5
6
VCO (V)
IN
VCO (V)
IN
FIGURE 20. HC7046A TYPICAL VCO FREQUENCY vs VCO
FIGURE 21. HC7046A TYPICAL VCO FREQUENCY vs VCO
IN
IN
(R1 = 150kΩ, C1 = 0.1µF)
(R1 = 5.6kΩ, C1 = 0.1µF)
14
CD74HC7046A, CD74HCT7046A
Typical Performance Curves (Continued)
24
20
1400
1200
V
= 6V
CC
V
= 6V
C1 = 50pF
R1 = 5.6K
R2 = ∞
CC
C1 = 50pF
R1 = 150K
R2 = ∞
1000
V
= 4.5V
V
= 4.5V
CC
CC
16
12
800
600
V
= 3V
V
= 3V
CC
CC
8
4
400
200
0
1
2
3
4
5
6
0
1
2
3
4
5
6
VCO (V)
IN
VCO (V)
IN
FIGURE 23. HC7046A TYPICAL VCO FREQUENCY vs VCO
FIGURE 22. HC7046A TYPICAL VCO FREQUENCY vs VCO
IN
IN
(R1 = 5.6kΩ, C1 = 50pF)
(R1 = 150kΩ, C1 = 0.1µF)
24
VCO = 0.5 V
IN CC
20
16
12
8
VCO = 0.5 V
R1 = 2.2M
IN
CC
= 3V
R1 = 1.5M
20
16
12
8
C1 = 50pF, V
= 4.5V
CC
C1 = 50pF, V
CC
R2 = ∞
R2 = ∞
R1 = 150K
R1 = 220K
4
4
0
R1 = 3K
0
-4
R1 = 2.2K
-4
-8
-8
-12
-12
-16
-75 -50
-25
0
25
50
75
100 125 150
-75 -50
-25
0
25
50
75
100 125 150
o
o
AMBIENT TEMPERATURE, T ( C)
AMBIENT TEMPERATURE, T ( C)
A
A
FIGURE 24. HC7046A TYPICAL CHANGE IN VCO FREQUENCY
vs AMBIENT TEMPERATURE AS A FUNCTION OF
FIGURE 25. HC7046A TYPICAL CHANGE IN VCO FREQUENCY vs
AMBIENT TEMPERATURE AS A FUNCTION OF R1
R1 (V
= 3V)
CC
15
CD74HC7046A, CD74HCT7046A
Typical Performance Curves (Continued)
20
VCO = 0.5 V
IN CC
16
12
8
VCO = 0.5 V
IN
CC
= 5.5V
R1 = 3M
C1 = 50pF, V
= 6.0V
CC
C1 = 50pF, V
CC
16
12
8
R1 = 3M
R2 = ∞
R2 = ∞
R1 = 300K
R1 = 300K
4
4
0
0
-4
-8
-12
R1 = 3K
R1 = 3K
-4
-8
-12
-75
-50
-25
0
25
50
75
100 125 150
-75
-50
-25
0
25
50
75
100 125 150
o
o
AMBIENT TEMPERATURE, T ( C)
AMBIENT TEMPERATURE, T ( C)
A
A
FIGURE 26. HC7046A TYPICAL CHANGE IN VCO FREQUENCY vs
AMBIENT TEMPERATURE AS A FUNCTION OF R1
FIGURE 27. HCT7046A TYPICAL CHANGE IN VCO
FREQUENCY vs AMBIENT TEMPERATURE AS A
FUNCTION OF R1
8
10
VCO = 0.5 V
IN CC
20
16
12
8
R1 = 2.2M
C1 = 50pF, V
= 4.5V
CC
7
10
R2 = ∞
6
10
R2 = 2.2K
R1 = 220K
5
10
R2 = 22K
4
4
10
R2 = 220K
R2 = 2.2M
3
2
0
10
10
-4
R1 = 2.2K
-8
VCO = 0.5 V
IN CC
CC
10
1
R2 = 11M
5 6
V
= 4.5V
-12
-75
-50
-25
0
25
50
75
100 125 150
2
3
4
1
10
10
10
10
10
10
o
AMBIENT TEMPERATURE, T ( C)
CAPACITANCE, C1 (pF)
A
FIGURE 28. HC7046A TYPICAL CHANGE IN VCO FREQUENCY vs
AMBIENT TEMPERATURE AS A FUNCTION OF R1
FIGURE 29. HC7046A OFFSET FREQUENCY vs R2, C1
8
8
10
10
7
7
10
10
6
6
R2 = 1.5K
10
10
10
10
10
10
R2 = 2.2K
5
4
3
2
5
10
R2 = 22K
R2 = 220K
R2 = 2.2M
4
3
2
R2 = 15K
10
10
10
R2 = 150K
R2 = 1.5M
VCO = GND
IN
CC
VCO = GND
IN
CC
10
1
10
1
R2 = 7.5M
5
R2 = 11M
5
V
= 3V
V
= 4.5V
2
3
4
6
2
3
4
6
10
1
10
1
10
10
10
10
10
10
10
10
10
10
CAPACITANCE, C1 (pF)
CAPACITANCE, C1 (pF)
FIGURE 30. HC7046A OFFSET FREQUENCY vs R2, C1
FIGURE 31. HCT7046A OFFSET FREQUENCY vs R2, C1
16
CD74HC7046A, CD74HCT7046A
Typical Performance Curves (Continued)
8
7
6
5
4
3
2
10
10
10
10
10
10
10
VCO = V
IN
- 0.9V FOR f
MAX
CC
VCO = 0V FOR f
2
IN
MIN
10
V
= 3V, 4.5V, 6V
CC
R2 = 3K
R2 = 30K
10
R2 = 300K
R2 = 3M
VCO = GND
IN
HC - V
HCT - V
= 6V
CC
10
1
R2 = 15M
5 6
= 5.5V
CC
1
10
2
3
4
1
10
10
10
10
10
10
-2
-1
2
1
10
10
10
CAPACITANCE, C1 (pF)
R2/R1
FIGURE 32. HC7046A AND HCT7046A OFFSET FREQUENCY
vs R2, C1
FIGURE 33. HC7046A f
/f
MIN MAX
vs R2/R1
VCO = V
IN
- 0.9V FOR f
MAX
CC
2
VCO = 0V FOR f
IN MIN
10
V
= 4.5V TO 5.5V
CC
f
f
f
2
0
∆V = 0.5V OVER THE V
RANGE:
CC
10
f
0’
FOR VCO LINEARITY
f’ = f + f
2
o
1
f
2
1
f’ - f
o
o
LINEARITY =
x 100%
f’
o
∆V
∆V
1
10
MIN
MAX
1/2V
CC
-2
-1
2
1
10
10
10
V
VCOIN
R2/R1
FIGURE 34. HCT7046A f
/f
vs R2/R1
FIGURE 35. DEFINITION OF VCO FREQUENCY LINEARITY
MAX MIN
8
8
C1 = 50pF
C1 = 50pF
= 4.5V
R2 = ∞
6
4
V
= 3V
V
6
CC
CC
R2 = ∞
4
2
VCO = 2.25V ± 1V
IN
2
VCO = 1.50V ± 0.4V
IN
0
0
VCO = 2.25V ± 0.45V
IN
VCO = 1.50V ± 0.3V
IN
-2
-2
-4
-6
-4
-6
-8
-8
1K
10K
1K
10K
100K
R1 (OHMS)
1M
10M
100K
1M
10M
R1 (OHMS)
FIGURE 36. HC7046A VCO LINEARITY vs R1
FIGURE 37. HC7046A VCO LINEARITY vs R1
17
CD74HC7046A, CD74HCT7046A
Typical Performance Curves (Continued)
8
6
4
8
6
V
= 5.5V,
CC
VCO = 2.75V ±1.3V
C1 = 50pF
= 6V
R2 = ∞
IN
= 4.5V,
V
CC
V
CC
VCO = 2.25V ±1.0V
IN
4
2
VCO = 3V ± 1.5V
IN
2
0
0
-2
-4
-2
V
= 5.5V,
CC
VCO = 2.75V ±0.55V
IN
= 4.5V,
-4
-6
V
CC
VCO = 3V ± 0.6V
IN
VCO = 2.25V ±0.45V
IN
C1 = 50pF
R2 = OPEN
-6
-8
-8
1K
10K
1K
10K
100K
1M
10M
100K
1M
10M
R1 (OHMS)
R1 (OHMS)
FIGURE 38. HC7046A VCO LINEARITY vs R1
VCO = 0.5 V
FIGURE 39. HCT7046A VCO LINEARITY vs R1
VCO = 0.5 V
4
3
2
4
3
2
10
10
10
10
10
10
IN
CC
IN
CC
R1 = R2 = OPEN
V
= 6V
V
= 6V
CC
CC
V
= 3V
V
= 3V
CC
CC
V
= 4.5V
V
= 4.5V
CC
CC
10
1
10
1
1K
10K
100K
1M
1K
10K
100K
1M
RS (OHMS)
RS (OHMS)
FIGURE 40. HC7046A DEMODULATOR POWER DISSIPATION
vs RS (TYP)
FIGURE 41. HCT7046A DEMODULATOR POWER DISSIPATION
vs RS (TYP) (V = 3V, 4.5V, 6V)
CC
6
5
4
3
2
10
10
10
10
10
6
VCO = 0V (AT f
)
10
IN
MIN
VCO = 0.5V
V
= 6V
IN
CC
CC
C1 = 50pF
R1 = RS = ∞
R2 = RS = OPEN
= 50pF
C
= 50pF
L
C
L
V
= 6V
CC
C1 = 50pF
5
4
3
2
10
10
10
10
V
= 4.5V
CC
C1 = 50pF
V
= 6V
V
= 4.5V
CC
C1 = 1µF
CC
C1 = 50pF
V
= 4.5V
CC
C1 = 1µF
V
= 6V
CC
C1 = 1µF
V
= 3V
CC
C1 = 1µF
V
= 3V
CC
C1 = 50pF
V
= 4.5V
CC
C1 = 1µF
1K
10K
100K
1M
1K
10K
100K
1M
R2 (OHMS)
R1 (OHMS)
FIGURE 42. HC7046A VCO POWER DISSIPATION vs R1
FIGURE 43. HCT7046A VCO POWER DISSIPATION vs R2
(C1 = 50pF, 1µF)
(C1 = 50pF, 1µF)
18
CD74HC7046A, CD74HCT7046A
Typical Performance Curves (Continued)
6
5
4
3
2
10
10
10
10
10
6
5
4
3
2
VCO = 0.5V
IN
R2 = RS = ∞
10
10
10
10
10
VCO = 0V (AT f
IN
)
MIN
V
= 6V
CC
C1 = 50pF
R1 = RS = ∞
V
= 5.5V
CC
C1 = 50pF
C
= 50pF
L
V
= 4.5V
CC
V
= 4.5V
C1 = 50pF
CC
C1 = 50pF
V
= 6V
CC
C1 = 1µF
V
= 5.5V
CC
C1 = 1µF
V
= 3V
CC
C1 = 1µF
V
= 3V
C1 = 50pF
V
= 4.5V
CC
CC
C1 = 1µF
V
= 4.5V
CC
C1 = 1µF
1K
10K
100K
1M
1K
10K
100K
1M
R1 (OHMS)
R2 (OHMS)
FIGURE 44. HCT7046A VCO POWER DISSIPATION vs R1
FIGURE 45. HC7046A VCO POWER DISSIPATION vs R2 (C1 =
(C1 = 50pF, 1µF)
50pF, 1µF)
19
CD74HC7046A, CD74HCT7046A
References should be made to Figures 13 through 23 and
HC/HCT7046A C
PD
Figures 36 through 41 as indicated in the table.
CHIP SECTION
HC
48
39
61
HCT
50
UNIT
pF
Values of the selected components should be within the fol-
lowing ranges:
Comparator 1
Comparator 2
VCO
48
pF
R1
> 3kΩ;
53
pF
R2
> 3kΩ;
R1 || R2
C1
parallel value > 2.7kΩ;
greater than 40pF
Application Information
This information is a guide for the approximation of values of
external components to be used with the CD74HC7046A
and CD74HCT7046A in a phase-lock-loop system.
PHASE
SUBJECT
COMPARATOR
DESIGN CONSIDERATIONS
VCO Frequency
Without Extra Offset
(R2 = ∞)
PC1 or PC2
VCO Frequency Characteristic
The characteristics of the VCO operation are shown in Figures 13 - 23.
f
MAX
f
VCO
f
2f
o
L
f
MIN
V
MIN
1/2 V
MAX
VCOIN
CC
FIGURE 46. FREQUENCY CHARACTERISTIC OF VCO OPERATING WITHOUT
OFFSET: f = CENTER FREQUENCY: 2f = FREQUENCY LOCK RANGE
o
L
PC1
PC2
Selection of R1 and C1
Given f , determine the values of R1 and C1 using Figures 13 - 17.
o
Given f
MAX
calculate f as f /2 and determine the values of R1 and C1 using Figures 13 - 17.
MAX
o
2(∆VCO
)
IN
To obtain 2f : 2f ≈
where 0.9V < VCO < V
IN CC
- 0.9V is the range of ∆VCO
IN
L
L
R1C1
VCO Frequency Characteristic
The characteristics of the VCO operation are shown in Figures 29 - 32.
VCO Frequency with PC1 or PC2
Extra Offset
(R2 > 3kΩ)
f
MAX
f
VCO
2f
f
L
o
f
MIN
V
MIN
1/2 V
MAX
VCOIN
CC
FIGURE 47. FREQUENCY CHARACTERISTIC OF VCO OPERATING WITH OFFSET:
= CENTER FREQUENCY: 2f = FREQUENCY LOCK RANGE
f
o
L
PC1 or PC2
Selection of R1, R2 and C1
Given f and f , offset frequency, f
Obtain the values of C1 and R2 by using Figures 29 - 32.
, may be calculated from fMIN ≈ f - 1.6 f .
o
L
MIN
o
L
Calculate the values of R1 from Figures 33 - 34.
20
PHASE
SUBJECT
COMPARATOR
DESIGN CONSIDERATIONS
o
PLL Conditions with
No Signal at the
SIG Input
IN
PC1
PC2
VCO adjusts to f with φDEMOUT = 90 and V
= 1/2 V
(see Figure 2)
CC
o
VCOIN
o
VCO adjusts to f
with φDEMOUT = -360 and V
= 0V (see Figure 4)
MIN
VCOIN
PLL Frequency
Capture Range
PC1 or PC2
Loop Filter Component Selection
|F
|
)
(j
ω
R3
-1/
τ
C2
INPUT
OUTPUT
ω
(B) AMPLITUDE CHARACTERISTIC
(C) POLE-ZERO DIAGRAM
1/2
(A) τ1 = R3 x C2
A small capture range (2f ) is obtained if τ > 2f ≈ (1/π) (2πf /τ1.)
c
c
L
FIGURE 48. SIMPLE LOOP FILTER FOR PLL WITHOUT OFFSET
R3
|F
|
)
(j
ω
R4
m =
R4
C2
R3 + R4
INPUT
OUTPUT
-1/
-1/
3
2
τ
τ
m
1/
1/
2
ω
3
τ
τ
(B) AMPLITUDE CHARACTERISTIC
(C) POLE-ZERO DIAGRAM
(A) τ2 = R4 x C2;
τ3 = (R3 + R4) x C2
FIGURE 49. SIMPLE LOOP FILTER FOR PLL WITH OFFSET
PLL Locks on
Harmonics at Center
Frequency
PC1
PC2
Yes
No
Noise Rejection at
Signal Input
PC1
PC2
PC1
PC2
High
Low
o
AC Ripple Content
when PLL is Locked
f = 2f , large ripple content at φDEMOUT = 90
r i
o
f = f , small ripple content at φDEMOUT = 0
r
i
Lock Detector Circuit
The lock detector feature is very useful in data synchroniza-
tion, motor speed control, and demodulation. By adjusting
the value of the lock detector capacitor so that the lock out-
put will change slightly before actually losing lock, the
designer can create an “early warning” indication allowing
corrective measures to be implemented. The reverse is also
true, especially with motor speed controls, generators, and
clutches that must be set up before actual lock occurs or dis-
connected during loss of lock.
When using phase comparator 1, the detector will only indi-
cate a lock condition on the fundamental frequency and not
on the harmonics, which PC1 will lock on.
21
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2007
PACKAGING INFORMATION
Orderable Device
CD74HC7046AE
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PDIP
N
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HC7046AEE4
CD74HC7046AM
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
N
D
D
D
D
D
D
D
D
D
N
N
D
D
D
D
D
D
D
D
D
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC7046AM96
CD74HC7046AM96E4
CD74HC7046AM96G4
CD74HC7046AME4
CD74HC7046AMG4
CD74HC7046AMT
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC7046AMTE4
CD74HC7046AMTG4
CD74HCT7046AE
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HCT7046AEE4
CD74HCT7046AM
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HCT7046AM96
CD74HCT7046AM96E4
CD74HCT7046AM96G4
CD74HCT7046AME4
CD74HCT7046AMG4
CD74HCT7046AMT
CD74HCT7046AMTE4
CD74HCT7046AMTG4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2007
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
16
CD74HC7046AM96
CD74HCT7046AM96
D
D
16
16
SITE 27
SITE 27
6.5
6.5
10.3
10.3
2.1
2.1
8
8
16
16
Q1
Q1
330
16
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
CD74HC7046AM96
CD74HCT7046AM96
D
D
16
16
SITE 27
SITE 27
342.9
342.9
336.6
336.6
28.58
28.58
Pack Materials-Page 2
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logic.ti.com
Logic
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power.ti.com
Optical Networking
Security
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www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
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Telephony
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Wireless
www.ti.com/wireless
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