CD74HC7266E [TI]

High Speed CMOS Logic Quad 2-Input EXCLUSIVE NOR Gate; 高速CMOS逻辑四路2输入异或非门


型号：	CD74HC7266E
厂家：	TEXAS INSTRUMENTS
描述：	High Speed CMOS Logic Quad 2-Input EXCLUSIVE NOR Gate 高速CMOS逻辑四路2输入异或非门栅
文件：	总5页 (文件大小：39K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CD74HC7266

Data sheet acquired from Harris Semiconductor

SCHS219

High Speed CMOS Logic

Quad 2-Input EXCLUSIVE NOR Gate

August 1997

Features

Description

• Four Independent EXCLUSIVE NOR Gates

• Buffered Inputs and Outputs

• Logical Comparators

The Harris CD74HC7266 contains four independent

Exclusive NOR gates in one package. They provide the

system designer with a means for implementation of the

EXCLUSIVE NOR function.

[ /Title

(CD74H

C7266)

/Subject

(High

• Parity Generators and Checkers

• Adders/Subtracters

This device is functionally the same as the TTL226. They

differ in that the HC7266 has active high and low outputs

whereas the 226 has open collector outputs.

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

Speed

CMOS

Logic

Quad 2-

Input

EXCLU-

SIVE

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Ordering Information

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

PKG.

NO.

PART NUMBER TEMP. RANGE ( C) PACKAGE

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

CD74HC7266E

CD74HC7266M

NOTES:

-55 to 125

14 Ld PDIP

E14.3

14 Ld SOIC M14.15

• HC Types

- 2V to 6V Operation

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

- High Noise Immunity: N = 30%, N = 30%of V

IL IH

= 5V

2. Die for this part number is available which meets all electrical

specifications. Please contact your local sales office or Harris

customer service for ordering information.

Pinout

CD74HC7266

(PDIP, SOIC)

TOP VIEW

14 V

13 4B

12 4A

11 4Y

10 3Y

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 1780.1

CD74HC7266

Functional Diagram

GND = 7

= 14

TRUTH TABLE

INPUTS

OUTPUT

NOTE: H = High Voltage Level, L = Low Voltage Level

Logic Symbol

CD74HC7266

Absolute Maximum Ratings

Thermal Information

DC Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

Thermal Resistance (Typical, Note 3)

( C/W)

DC Input Diode Current, I

For V < -0.5V or V > V

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

For V < -0.5V or V > V

175

DC Output Diode Current, I

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C

Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C

+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

For V > -0.5V or V < V

+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

(SOIC - Lead Tips Only)

DC V

or Ground Current, I

. . . . . . . . . . . . . . . . . .±50mA

CC or GND

Operating Conditions

Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

3. θ is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Speciﬁcations

TEST

CONDITIONS

25 C

-40 C TO 85 C -55 C TO 125 C

PARAMETER

HC TYPES

SYMBOL

V (V)

(mA)

(V)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNITS

High Level Input

Voltage

4.5

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

Low Level Input

Voltage

0.5

4.5

1.35

1.8

High Level Output

Voltage

CMOS Loads

or V

IH IL

-0.02

1.9

4.4

5.9

3.98

5.48

1.9

4.4

5.9

3.84

5.34

1.9

4.4

5.9

3.7

5.2

-0.02

-4

4.5

High Level Output

Voltage

TTL Loads

4.5

-5.2

Low Level Output

Voltage

CMOS Loads

or V

IH IL

0.02

4.5

0.1

0.4

0.1

Low Level Output

Voltage

TTL Loads

4.5

0.26

0.33

5.2

CD74HC7266

DC Electrical Speciﬁcations (Continued)

TEST

CONDITIONS

25 C

TYP

-40 C TO 85 C -55 C TO 125 C

(V)

PARAMETER

Input Leakage

SYMBOL

V (V)

(mA)

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

±0.1

±1

µA

Current

GND

Quiescent Device

Current (Note)

GND

µA

NOTE:

4. For dual-supply systems theorectical worst case (V = 2.4V, V

= 5.5V) specification is 1.8mA.

Switching Speciﬁcations Input t , t = 6ns

25 C

-40 C TO 85 C -55 C TO 125 C

TEST

PARAMETER

HC TYPES

SYMBOL

CONDITIONS

(V)

TYP

MAX

UNITS

Propagation Delay

C = 50pF

4.5

115

145

150

PLH, PHL

Propagation Delay Time, Any

Input

C = 15pF

PLH, PHL

Output Transition Times

(Figure 1)

, t

TLH THL

C = 50pF

4.5

110

Input Capacitance

Power Dissipation

Capacitance

C = 15pF

NOTE:

5. C

is used to determine the dynamic power consumption per gate, P = V

f (C + C ) where f = Input Frequency, C = Output

PD L i L

Load Capacitance, V

= Supply Voltage.

Test Circuit and Waveform

t = 6ns

90%

50%

10%

INPUT

GND

TLH

THL

90%

50%

10%

INVERTING

OUTPUT

PLH

PHL

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC

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