CD74HCT125ME4 [TI]

High-Speed CMOS Logic Quad Buffer, Three-State; 高速CMOS逻辑四路缓冲器,三态
CD74HCT125ME4
型号: CD74HCT125ME4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

High-Speed CMOS Logic Quad Buffer, Three-State
高速CMOS逻辑四路缓冲器,三态

文件: 总12页 (文件大小:265K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CD54HC125, CD74HC125,  
CD54HCT125, CD74HCT125  
Data sheet acquired from Harris Semiconductor  
SCHS143C  
High-Speed CMOS Logic  
Quad Buffer, Three-State  
November 1997 - Revised August 2003  
Features  
Description  
• Three-State Outputs  
The ’HC125 and ’HCT125 contain 4 independent three-state  
buffers, each having its own output enable input, which when  
“HIGH” puts the output in the high impedance state.  
• Separate Output Enable Inputs  
[ /Title  
(CD74  
HC125  
,
CD74  
HCT12  
5)  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
Ordering Information  
o
o
TEMP. RANGE  
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
PART NUMBER  
CD54HC125F3A  
CD54HCT125F3A  
CD74HC125E  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld CERDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
/Sub-  
ject  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
CC  
(High  
Speed  
CMOS  
Logic  
Quad  
Buffer,  
Three-  
State)  
IL  
IH  
CD74HC125M  
at V  
= 5V  
CC  
CD74HC125MT  
CD74HC125M96  
CD74HCT125E  
CD74HCT125M  
CD74HCT125MT  
CD74HCT125M96  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL  
IH  
- CMOS Input Compatibility, I 1µA at V , V  
l
OL OH  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
Pinout  
CD54HC125, CD54HCT125  
(CERDIP)  
CD74HC125, CD74HCT125  
(PDIP, SOIC)  
TOP VIEW  
1OE  
1A  
1
2
3
4
5
6
7
14 V  
CC  
13 4OE  
12 4A  
1Y  
2OE  
2A  
11 4Y  
10 3OE  
2Y  
9
8
3A  
3Y  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
CD54HC125, CD74HC125, CD54HCT125, CD74HCT125  
Functional Diagram  
1
2
1OE  
1A  
3
1Y  
2Y  
3Y  
4Y  
4
2OE  
2A  
6
5
10  
9
3OE  
3A  
8
13  
12  
4OE  
4A  
11  
GND = 7  
V
= 14  
CC  
TRUTH TABLE  
INPUTS  
OUTPUTS  
nA  
H
nOE  
L
nY  
H
L
L
L
X
H
Z
H= High Voltage Level  
L= Low Voltage Level  
X= Don’t Care  
Z= High Impedance, OFF State  
Logic Diagram  
P
n
nA  
nY  
nOE  
2
CD54HC125, CD74HC125, CD54HCT125, CD74HCT125  
Absolute Maximum Ratings  
Thermal Information  
o
DC Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
Thermal Resistance (Typical, Note 1)  
θ
( C/W)  
CC  
DC Input Diode Current, I  
For V < -0.5V or V > V  
JA  
IK  
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .  
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .  
80  
86  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
OK  
For V < -0.5V or V > V  
I
I
CC  
o
DC Output Diode Current, I  
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
O
O
CC  
o
DC Drain Current, per Output, I  
O
For -0.5V < V < V  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . . ±35mA  
O
CC  
(SOIC - Lead Tips Only)  
DC Output Source or Sink Current per Output Pin, I  
O
For V > -0.5V or V < V  
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
O
O
CC  
DC V  
or Ground Current, I  
. . . . . . . . . . . . . . . . . . . . . . . . .±70mA  
CC  
CC  
Operating Conditions  
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range, V  
CC  
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
I
O
CC  
Input Rise and Fall Time  
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)  
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)  
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. The package thermal impedance is calculated in accordance with JESD 51-7.  
DC Electrical Specifications  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
PARAMETER  
HC TYPES  
SYMBOL V (V)  
I
(mA)  
V
(V) MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
High Level Input  
Voltage  
V
-
-
-
2
1.5  
3.15  
4.2  
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5  
3.15  
4.2  
-
-
1.5  
3.15  
4.2  
-
-
V
V
V
V
V
V
V
V
V
V
V
IH  
4.5  
-
-
-
6
2
-
-
-
Low Level Input  
Voltage  
V
-
0.5  
0.5  
0.5  
IL  
4.5  
6
-
1.35  
-
1.35  
-
1.35  
-
1.8  
-
1.8  
-
1.8  
High Level Output  
Voltage  
CMOS Loads  
V
V
or  
-0.02  
2
1.9  
4.4  
5.9  
3.98  
5.48  
-
-
-
-
-
1.9  
4.4  
5.9  
3.84  
5.34  
-
-
-
-
-
1.9  
4.4  
5.9  
3.7  
5.2  
-
-
-
-
-
OH  
IH  
V
IL  
-0.02  
-0.02  
-6  
4.5  
6
High Level Output  
Voltage  
TTL Loads  
4.5  
6
-7.8  
Low Level Output  
Voltage  
CMOS Loads  
V
V
V
or  
0.02  
0.02  
0.02  
6
2
4.5  
6
-
-
-
-
-
-
-
-
-
-
0.1  
0.1  
-
-
-
-
-
0.1  
0.1  
-
-
-
-
-
0.1  
0.1  
0.1  
0.4  
0.4  
V
V
V
V
V
OL  
IH  
IL  
0.1  
0.1  
Low Level Output  
Voltage  
TTL Loads  
4.5  
6
0.26  
0.26  
0.33  
0.33  
7.8  
Input Leakage  
Current  
I
V
or  
-
6
-
-
±0.1  
-
±1  
-
±1  
µA  
I
CC  
GND  
3
CD54HC125, CD74HC125, CD54HCT125, CD74HCT125  
DC Electrical Specifications  
(Continued)  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
PARAMETER  
SYMBOL V (V)  
I
(mA)  
V
(V) MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
Quiescent Device  
Current  
I
V
or  
0
6
-
-
8
-
80  
-
160  
µA  
CC  
CC  
GND  
Three-State Leakage  
Current  
I
V
V
or  
IL  
-
6
-
-
±0.5  
-
±5  
-
±10  
µA  
OZ  
IH  
HCT TYPES  
High Level Input  
Voltage  
V
-
-
-
-
4.5 to  
5.5  
2
-
-
-
-
-
0.8  
-
2
-
-
0.8  
-
2
-
-
0.8  
-
V
V
V
IH  
Low Level Input  
Voltage  
V
4.5 to  
5.5  
IL  
High Level Output  
Voltage  
CMOS Loads  
V
V
V
or  
-0.02  
4.5  
4.5  
4.5  
4.5  
4.4  
4.4  
4.4  
OH  
IH  
V
IL  
High Level Output  
Voltage  
TTL Loads  
-6  
3.98  
-
-
-
-
3.84  
-
3.7  
-
V
V
V
Low Level Output  
Voltage  
CMOS Loads  
V
or  
0.02  
6
-
-
0.1  
0.26  
-
-
0.1  
0.33  
-
-
0.1  
0.4  
OL  
IH  
V
IL  
Low Level Output  
Voltage  
TTL Loads  
Input Leakage  
Current  
I
V
to  
0
0
-
5.5  
5.5  
-
-
-
-
-
±0.1  
8
-
-
-
±1  
80  
-
-
-
±1  
µA  
µA  
µA  
I
CC  
GND  
Quiescent Device  
Current  
I
V
or  
160  
490  
CC  
CC  
GND  
Additional Quiescent  
Device Current Per  
Input Pin: 1 Unit Load  
I  
CC  
(Note 2)  
V
4.5 to  
5.5  
100  
360  
450  
CC  
-2.1  
Three-State Leakage  
Current  
I
V
V
or  
IL  
-
5.5  
-
-
±0.5  
-
±5  
-
±10  
µA  
OZ  
IH  
NOTE:  
2. For dual-supply systems theoretical worst case (V = 2.4V, V  
I
= 5.5V) specification is 1.8mA.  
CC  
HCT Input Loading Table  
INPUT  
nA, nOE  
UNIT LOADS  
1
NOTE: Unit Load is I  
Specifications table, e.g., 360µA max at 25 C.  
limit specified in DC Electrical  
o
CC  
4
CD54HC125, CD74HC125, CD54HCT125, CD74HCT125  
Switching Specifications Input t , t = 6ns  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
CONDITIONS  
PARAMETER  
HC TYPES  
SYMBOL  
V
(V)  
TYP  
MAX  
MAX  
MAX  
UNITS  
CC  
Propagation Delay Time  
nA to nY  
t
, t  
C = 50pF  
2
-
-
100  
20  
-
125  
25  
-
150  
30  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
pF  
pF  
PLH PHL  
L
4.5  
C = 15pF  
L
5
6
2
8
-
CL = 50pF  
17  
125  
25  
-
21  
155  
31  
-
26  
190  
38  
-
Enable Delay Time  
Disable Delay Time  
t
t
C = 50pF  
-
PZL, PZH  
L
4.5  
5
-
C = 15pF  
L
10  
-
CL = 50pF  
CL = 50pF  
6
21  
125  
25  
-
26  
155  
31  
-
32  
190  
38  
-
t
, t  
PLZ PHZ  
2
-
C = 50pF  
4.5  
5
-
L
C = 15pF  
L
10  
-
CL = 50pF  
6
21  
60  
12  
10  
10  
20  
26  
75  
15  
13  
10  
20  
32  
90  
18  
15  
10  
20  
Output Transition Time  
Input Capacitance  
t
, t  
TLH THL  
C = 50pF  
L
2
-
4.5  
6
-
-
C
-
-
-
-
I
Three-State Output  
Capacitance  
C
-
-
O
Power Dissipation  
Capacitance  
C
-
5
29  
-
-
-
pF  
PD  
(Notes 3, 4)  
HCT TYPES  
Propagation Delay Time  
nA to nY  
t
, t  
C = 50pF  
4.5  
5
-
10  
-
25  
-
31  
-
38  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
pF  
pF  
PLH PHL  
L
C = 15pF  
L
Output Enable Time  
t
t
C = 50pF  
4.5  
5
25  
-
31  
-
38  
-
PZL, PZH  
L
C = 15pF  
10  
-
L
Output Disabling Time  
t
, t  
PLZ PHZ  
C = 50pF  
4.5  
5
28  
-
35  
-
42  
-
L
C = 15pF  
11  
-
L
Output Transition Times  
Input Capacitance  
t
, t  
TLH THL  
C = 50pF  
L
4.5  
-
12  
10  
20  
15  
10  
20  
18  
10  
20  
C
-
-
-
I
Three-State Output  
Capacitance  
C
-
-
O
Power Dissipation  
Capacitance  
C
-
5
34  
-
-
-
pF  
PD  
(Notes 3, 4)  
NOTES:  
3. C  
is used to determine the dynamic power consumption, per channel.  
2
PD  
4. P = V  
f (C  
PD  
+ C ) where f = Input Frequency, f = Output Frequency, C = Output Load Capacitance, V  
= Supply Voltage.  
D
CC  
i
L
i
O
L
CC  
5
CD54HC125, CD74HC125, CD54HCT125, CD74HCT125  
Test Circuits and Waveforms  
t = 6ns  
t = 6ns  
t = 6ns  
t = 6ns  
r
f
r
f
V
3V  
CC  
90%  
50%  
10%  
2.7V  
1.3V  
0.3V  
INPUT  
INPUT  
GND  
GND  
t
t
t
t
THL  
TLH  
THL  
TLH  
90%  
1.3V  
90%  
50%  
10%  
INVERTING  
OUTPUT  
INVERTING  
OUTPUT  
10%  
t
t
PLH  
PHL  
t
t
PLH  
PHL  
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
6ns  
6ns  
t
6ns  
t
6ns  
r
f
V
3V  
CC  
OUTPUT  
DISABLE  
OUTPUT  
DISABLE  
90%  
2.7  
50%  
t
1.3  
10%  
0.3  
GND  
GND  
t
t
t
t
PZL  
PZL  
PLZ  
PLZ  
OUTPUT LOW  
TO OFF  
OUTPUT LOW  
TO OFF  
50%  
50%  
1.3V  
10%  
90%  
10%  
90%  
t
t
PZH  
PHZ  
PHZ  
t
PZH  
OUTPUT HIGH  
TO OFF  
OUTPUT HIGH  
TO OFF  
1.3V  
OUTPUTS  
ENABLED  
OUTPUTS  
ENABLED  
OUTPUTS  
DISABLED  
OUTPUTS  
ENABLED  
OUTPUTS  
DISABLED  
OUTPUTS  
ENABLED  
FIGURE 3. HC THREE-STATE PROPAGATION DELAY  
WAVEFORM  
FIGURE 4. HCT THREE-STATE PROPAGATION DELAY  
WAVEFORM  
OTHER  
OUTPUT  
= 1kΩ  
INPUTS  
TIED HIGH  
OR LOW  
IC WITH  
THREE-  
STATE  
R
L
V
FOR t AND t  
PLZ  
CC  
GND FOR t  
PZL  
AND t  
PHZ  
PZH  
C
L
OUTPUT  
50pF  
OUTPUT  
DISABLE  
NOTE: Open drain waveforms t  
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kto  
PZL L  
PLZ  
V
, C = 50pF.  
CC  
L
FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT  
6
PACKAGE OPTION ADDENDUM  
www.ti.com  
6-Dec-2006  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
CDIP  
CDIP  
CDIP  
PDIP  
Drawing  
CD54HC125F  
CD54HC125F3A  
CD54HCT125F3A  
CD74HC125E  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
J
J
14  
14  
14  
14  
1
1
TBD  
TBD  
TBD  
A42 SNPB  
A42 SNPB  
A42 SNPB  
N / A for Pkg Type  
N / A for Pkg Type  
N / A for Pkg Type  
J
1
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CD74HC125EE4  
CD74HC125M  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
N
D
D
D
D
D
D
N
N
D
D
D
D
D
D
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC125M96  
CD74HC125M96E4  
CD74HC125ME4  
CD74HC125MT  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC125MTE4  
CD74HCT125E  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CD74HCT125EE4  
CD74HCT125M  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HCT125M96  
CD74HCT125M96E4  
CD74HCT125ME4  
CD74HCT125MT  
CD74HCT125MTE4  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
6-Dec-2006  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process  
in which TI products or services are used. Information published by TI regarding third-party products or services  
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.  
Use of such information may require a license from a third party under the patents or other intellectual property  
of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without  
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction  
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for  
such altered documentation.  
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that  
product or service voids all express and any implied warranties for the associated TI product or service and  
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.  
Following are URLs where you can obtain information on other Texas Instruments products and application  
solutions:  
Products  
Applications  
Audio  
Amplifiers  
amplifier.ti.com  
www.ti.com/audio  
Data Converters  
dataconverter.ti.com  
Automotive  
www.ti.com/automotive  
DSP  
dsp.ti.com  
Broadband  
Digital Control  
Military  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
Logic  
interface.ti.com  
logic.ti.com  
Power Mgmt  
Microcontrollers  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
microcontroller.ti.com  
Low Power Wireless www.ti.com/lpw  
Telephony  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address:  
Texas Instruments  
Post Office Box 655303 Dallas, Texas 75265  
Copyright 2006, Texas Instruments Incorporated  

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