CD74HCT132MT [TI]
High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger; 高速CMOS逻辑四路2输入与非施密特触发器
| 型号： | CD74HCT132MT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger |
| 文件： | 总10页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC132, CD74HC132,
CD54HCT132, CD74HCT132
Data sheet acquired from Harris Semiconductor
SCHS145E
High-Speed CMOS Logic
Quad 2-Input NAND Schmitt Trigger
August 1997 - Revised March 2004
Features
Description
• Unlimited Input Rise and Fall Times
• Exceptionally High Noise Immunity
• Typical Propagation Delay: 10ns at V
The ’HC132 and ’HCT132 each contain four 2-input NAND
Schmitt Triggers in one package. This logic device utilizes
silicon gate CMOS technology to achieve operating speeds
similar to LSTTL gates with the low power consumption of
standard CMOS integrated circuits. All devices have the
ability to drive 10 LSTTL loads. The HCT logic family is
functionally pin compatible with the standard LS logic family.
[ /Title
(CD74
HC132
,
= 5V,
CC
o
C = 15pF, T = 25 C
L
A
• Fanout (Over Temperature Range)
CD74
HCT13
2)
/Sub-
ject
(High
Speed
CMOS
Logic
Quad
2-Input
NAND
Schmit
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Ordering Information
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
TEMP. RANGE
o
PART NUMBER
CD54HC132F3A
CD54HCT132F3A
CD74HC132E
( C)
PACKAGE
14 Ld CERDIP
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
CD74HC132M
- High Noise Immunity: N = 37%, N = 51% of V
IL IH CC
at V
= 5V
CC
CD74HC132MT
CD74HC132M96
CD74HCT132E
CD74HCT132M
CD74HCT132MT
CD74HCT132M96
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
Pinout
CD54HC132, CD54HCT132
(CERDIP)
CD74HC132, CD74HCT132
(PDIP, SOIC)
TOP VIEW
1A
1B
1
2
3
4
5
6
7
14 V
CC
13 4B
12 4A
11 4Y
10 3B
1Y
2A
2B
2Y
9
8
3A
3Y
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
1
CD54HC132, CD74HC132, CD54HCT132, CD74HCT132
Functional Diagram
14
13
12
11
10
9
1
2
3
4
5
6
7
V
1A
1B
CC
4B
4A
4Y
3B
3A
3Y
1Y
2A
2B
2Y
8
GND
TRUTH TABLE
INPUTS
OUTPUT
nA
L
nB
L
nY
H
L
H
L
H
H
H
H
H
L
H = High Voltage Level, L = Low Voltage Level
Logic Symbol
nA
nB
nY
2
CD54HC132, CD74HC132, CD54HCT132, CD74HCT132
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
80
86
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
CC
I
O
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
Input Switch Points
(Note 2)
V +
-
-
-
2
0.7
1.7
2.1
0.3
0.9
1.2
0.2
0.4
0.6
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
1
0.7
1.7
2.1
0.3
0.9
1.2
0.2
0.4
0.6
1.9
4.4
5.9
3.84
5.34
1.5
3.15
4.2
1
0.7
1.7
2.1
0.3
0.9
1.2
0.2
0.4
0.6
1.9
4.4
5.9
3.7
5.2
1.5
3.15
4.2
1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
T
4.5
6
2
V -
-
T
4.5
6
2.2
3
2.2
3
2.2
3
V
2
1
1
1
H
4.5
6
1.4
1.6
-
1.4
1.6
-
1.4
1.6
-
High Level Output
Voltage
CMOS Loads
V
V + or
-0.02
2
OH
T
V -
T
-0.02
-0.02
-4
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
TTL Loads
4.5
6
-
-
-
-5.2
-
-
-
Low Level Output
Voltage
CMOS Loads
V
V + or
0.02
0.02
0.02
4
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
T
V -
T
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
5.2
3
CD54HC132, CD74HC132, CD54HCT132, CD74HCT132
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
Input Leakage
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
I
V
or
-
6
-
-
±0.1
-
±1
-
±1
µA
I
CC
GND
Current
Quiescent Device
Current
I
V
GND
or
0
6
-
-
2
-
20
-
40
µA
CC
CC
HCT TYPES
Input Switch Points
(Note 2)
V +
-
-
-
-
-
-
4.5
1.2
1.4
0.5
0.6
0.4
0.4
4.4
-
-
-
-
-
-
-
1.9
2.1
1.2
1.4
1.4
1.5
-
1.2
1.4
0.5
0.6
0.4
0.4
4.4
1.9
2.1
1.2
1.4
1.4
1.5
-
1.2
1.4
0.5
0.6
0.4
0.4
4.4
1.9
2.1
1.2
1.4
1.4
1.5
-
V
V
V
V
V
V
V
T
5.5
4.5
5.5
4.5
5.5
4.5
V -
T
V
H
High Level Output
Voltage
V +
-0.02
-
T
or
V -
T
CMOS Loads
High Level Output
Voltage
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
TTL Loads
Low Level Output
Voltage CMOS Loads
V
V +
0.02
4
4.5
4.5
-
-
-
-
0.1
-
-
0.1
-
-
0.1
0.4
V
V
OL
T
or
V -
T
Low Level Output
Voltage
0.26
0.33
TTL Loads
Input Leakage
Current
I
V
and
GND
-
5.5
5.5
-
-
±0.1
-
±1
-
±1
µA
I
CC
Quiescent Device
Current
I
V
or
0
-
-
-
-
2
-
-
20
-
-
40
µA
µA
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 3)
V
4.5 to
5.5
100
360
450
490
CC
- 2.1
NOTES:
2. Hysteresis definition, characteristic and test setup see Test Circuits and Waveforms
3. For dual-supply systems theoretical worst case (V = 2.4V, V = 5.5V) specification is 1.8mA.
I
CC
4
CD54HC132, CD74HC132, CD54HCT132, CD74HCT132
HCT Input Loading Table
INPUT
nA, nB
UNIT LOADS
0.6
NOTE: Unit Load is ∆I
tions table, e.g. 360µA max at 25 C.
limit specified in DC Electrical Specifica-
o
CC
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
SYMBOL CONDITIONS
V
CC
PARAMETER
HC TYPES
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
(V)
Propagation Delay
A, B to Y (Figure 1)
t
, t
C = 50pF
2
4.5
6
-
-
-
-
-
-
125
25
21
-
-
-
-
-
156
31
27
-
-
-
-
-
188
38
32
-
ns
ns
ns
pF
PLH PHL
L
-
Propagation Delay
A, B to Y
t
t
, t
TLH THL
C = 15pF
5
10
L
Transition Times (Figure 1)
, t
TLH THL
C = 50pF
L
2
4.5
6
-
-
-
-
-
-
-
75
15
13
10
-
-
-
-
-
-
95
19
16
10
-
-
-
-
-
-
110
22
19
10
-
ns
ns
ns
pF
pF
-
Input Capacitance
C
-
-
-
-
I
Power Dissipation Capacitance
(Notes 4, 5)
C
5
30
PD
HCT TYPES
Propagation Delay
A, B to Y
(Figure 2)
t
, t
PHL PHL
C = 50pF
4.5
5
-
-
-
33
-
-
-
41
-
-
-
50
-
ns
L
Propagation Delay
A, B to Y
t , t
PLH PHL
C = 15pF
13
pF
L
Transition Times (Figure 2)
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
-
-
-
-
-
15
10
-
-
-
-
19
10
-
-
-
-
22
10
-
ns
pF
pF
C
-
-
I
Power Dissipation Capacitance
(Notes 4, 5)
C
5
30
PD
NOTES:
4. C
is used to determine the dynamic power consumption, per gate.
2
PD
5. P = V
f (C
PD
+ C ) where f = input frequency, C = output load capacitance, V
= supply voltage.
CC
D
CC
i
L
i
L
5
CD54HC132, CD74HC132, CD54HCT132, CD74HCT132
Test Circuits and Waveforms
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
V
H
V
O
+
-
T
V
= V - V
T
H
V
l
-
T
+
V
V
T
+
T
-
T
V
V
V
CC
V
l
V
H
GND
V
CC
V
CC
V
O
V
O
GND
V
l
FIGURE 3. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SET-UP
6
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