CD74HCT139E [TI]
High-Speed CMOS Logic Dual 2-to-4 Line Decoder/Demultiplexer; 高速CMOS逻辑双路2至4线译码器/多路解复用器
| 型号： | CD74HCT139E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic Dual 2-to-4 Line Decoder/Demultiplexer |
| 文件： | 总6页 (文件大小：39K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC139,
CD74HCT139
Data sheet acquired from Harris Semiconductor
SCHS148A
High-Speed CMOS Logic
September 1997 - Revised May 1999
Dual 2-to-4 Line Decoder/Demultiplexer
Features
Description
• Multifunction Capability
The CD74HC139 and CD74HCT139 devices contain two
independent binary to one of four decoders each with a
single active low enable input (1E or 2E). Data on the select
inputs (1A0 and 1A1 or 2A0 and 2A1) cause one of the four
normally high outputs to go low.
- Binary to 1 of 4 Decoders or 1 to 4 Line
Demultiplexer
[ /Title
(CD74
HC139
,
CD74
HCT13
9)
• Active Low Mutually Exclusive Outputs
• Fanout (Over Temperature Range)
If the enable input is high all four outputs remain high. For
demultiplexer operation the enable input is the data input.
The enable input also functions as a chip select when these
devices are cascaded. This device is functionally the same
as the CD4556B and is pin compatible with it.
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
/Sub-
ject
The outputs of these devices can drive 10 low power
Schottky TTL equivalent loads. The 74HCT logic family is
functionally as well as pin equivalent to the 74LS logic family.
• Significant Power Reduction Compared to LSTTL
Logic ICs
(High
Speed
CMOS
Logic
Dual
2-to-4
Line
Decod
• HC Types
Ordering Information
- 2V to 6V Operation
PKG.
- High Noise Immunity: N = 30%, N = 30%of V
IL IH CC
at
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
NO.
E16.3
E16.3
V
= 5V
CC
CD74HC139E
CD74HCT139E
CD74HC139M
CD74HCT139M
NOTES:
-55 to 125
-55 to 125
-55 to 125
-55 to 125
16 Ld PDIP
16 Ld PDIP
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
16 Ld SOIC M16.15
16 Ld SOIC M16.15
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
• Memory Decoding, Data Routing, Code Conversion
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Die is available which meets all electrical specifications. Please
contact your local sales office or customer service for ordering
information.
Pinout
CD74HC139, CD74HCT139
(PDIP, SOIC)
TOP VIEW
1E
1A0
1A1
1Y0
1Y1
1Y2
1Y3
GND
1
2
3
4
5
6
7
8
16 V
CC
15 2E
14 2A0
13 2A1
12 2Y0
11 2Y1
10 2Y2
9
2Y3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Texas Instruments Incorporated 1999
1
CD74HC139, CD74HCT139
Functional Diagram
4 (12)
Y0
2 (14)
5 (11)
A0
Y1
6 (10)
3 (13)
Y2
A1
7 (9)
Y3
1 (15)
E
TRUTH TABLE
INPUTS ENABLE SELECT
OUTPUTS
Y2 Y1
E
0
0
0
0
1
A1
0
A0
0
Y3
1
Y0
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
X
X
1
1
NOTE: X = Don’t Care, Logic 1 = High, Logic 0 = Low
Logic Diagram
4 (12)
Y0
2 (14)
A0
5 (11)
Y1
3 (13)
A1
6 (10)
Y2
7 (9)
Y3
1 (15)
E
2
CD74HC139, CD74HCT139
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
115
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
3
CD74HC139, CD74HCT139
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆I
V
4.5 to
5.5
100
360
450
CC
CC
-2.1
NOTE:
4. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
All
UNIT LOADS
0.7
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
Switching Specifications Input t , t = 6ns
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
V
CC
(V)
PARAMETER
HC TYPES
MIN
TYP MAX MIN
MAX
MIN
MAX UNITS
Propagation Delay
A0, A1 to Outputs
t
t
C = 50pF
2
4.5
6
-
-
-
-
-
-
-
-
-
-
145
29
25
135
27
23
-
-
-
-
-
-
-
-
-
180
36
31
170
34
29
-
-
-
-
-
-
-
-
-
220
44
38
205
41
35
-
ns
ns
ns
ns
ns
ns
ns
ns
PLH, PHL
L
-
E to Outputs
t
t
C = 50pF
2
-
PLH, PHL
L
4.5
6
-
-
Select to Output
Enable to Output
t
t
t
C = 15pF
5
12
11
PLH, PHL
L
t
C = 15pF
5
-
-
-
PLH, PHL
L
4
CD74HC139, CD74HCT139
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
V
CC
(V)
PARAMETER
MIN
TYP MAX MIN
MAX
95
MIN
MAX UNITS
Output Transition Time (Figure 1) t
, t
TLH THL
C = 50pF
L
2
4.5
6
-
-
-
-
-
-
75
15
13
-
-
-
-
-
-
-
-
-
110
22
19
-
ns
ns
ns
pF
19
16
-
-
Power Dissipation
Capacitance, (Notes 5, 6)
C
-
-
5
55
PD
Input Capacitance
C
-
-
-
10
-
10
-
10
pF
IN
HCT TYPES
Propagation Delay
A0, A1 to Outputs
t
t
,
C = 50pF
4.5
4.5
-
-
-
-
34
34
-
-
43
43
-
-
51
51
ns
ns
PLH
t
L
PHL
E to Outputs
,
C = 50pF
L
PLH
t
PHL
Select to Output
Enable to Output
t
t
t
t
C = 15pF
5
5
-
-
-
14
14
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
PLH, PHL
L
t
C = 15pF
L
PLH, PHL
Output Transition Time
(Figure 2)
, t
C = 50pF
L
4.5
15
19
22
TLH THL
Power Dissipation
Capacitance, (Notes 5, 6)
C
-
-
5
-
-
-
59
-
-
-
-
-
-
-
-
pF
pF
PD
Input Capacitance
NOTES:
C
10
10
10
IN
5. C
is used to determine the dynamic power consumption, per decoder/demux.
2
PD
6. P = V
f (C
PD
+ C ) where: f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
CC
i
L
i
L
Test Circuits and Waveforms
t = 6ns
t = 6ns
f
r
t = 6ns
f
t = 6ns
r
V
CC
3V
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
TLH
THL
t
t
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
t
t
PLH
PLH
PHL
PHL
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
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