CD74HCT280 [TI]
High Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker; 高速CMOS逻辑9位奇/偶校验发生器/校验器
| 型号： | CD74HCT280 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker |
| 文件： | 总5页 (文件大小：39K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC280,
CD74HCT280
Data sheet acquired from Harris Semiconductor
SCHS175
High Speed CMOS Logic
November 1997
9-Bit Odd/Even Parity Generator/Checker
at V
= 5V
Features
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
• Typical Propagation Delay = 17ns at V
o
= 5V,
CC
C = 15pF, T = 25 C
L
A
[ /Title
(CD74
HC280
,
CD74
HCT28
0)
• Replaces 74LS180 Types
• Easily Cascadable
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Description
The Harris CD74HC280 and CD74HCT280 are 9-bit
odd/even parity, generator checker devices. Both even and
odd parity outputs are available for checking or generating
parity for words up to nine bits long. Even parity is indicated
(ΣE output is high) when an even number of data inputs is
high. Odd parity is indicated (ΣO output is high) when an odd
number of data inputs is high. Parity checking for words larger
than 9 bits can be accomplished by tying the ΣE output to any
input of an additional HC/HCT280 parity checker.
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
/Sub-
ject
• Significant Power Reduction Compared to LSTTL
Logic ICs
(High
Speed
CMOS
Logic
9-Bit
Odd/E
ven
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
Ordering Information
Functional Diagram
Pinout
CD74HC280, CD74HCT280
(PDIP)
Parity
8
I0
TOP VIEW
9
I1
I6
I7
1
2
3
4
5
6
7
14 V
CC
10
I2
I3
5
6
13 I5
12 I4
11 I3
10 I2
∑ EVEN
∑ ODD
11
12
13
1
NC
I8
I4
I5
I6
ΣE
ΣO
GND
9
8
I1
I0
2
4
I7
I8
GND = 7
= 14
V
CC
NC = 3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1669.1
Copyright © Harris Corporation 1997
1
CD74HC280, CD74HCT280
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
175
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
O
CC
(SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-4
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-5.2
Low Level Output
Voltage
CMOS Loads
V
or
0.02
0.02
0.02
4
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
V
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
5.2
Input Leakage
Current
I
V
or
-
6
6
-
-
-
-
±0.1
-
-
±1
-
-
±1
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
0
8
80
160
CC
CC
GND
2
CD74HC280, CD74HCT280
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HCT TYPES
SYMBOL V (V)
I
(mA)
V (V) MIN TYP MAX
CC
MIN
MAX
MIN
MAX
UNITS
I
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or
IH
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
V
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IH
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆I
CC
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE:
4. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
All
UNIT LOADS
1
NOTE: Unit Load is ∆I
Specifications table, e.g., 360µA max at 25 C.
limit specified in DC Electrical
o
CC
Switching Specifications Input t , t = 6ns
r
f
o
-55 C TO
125 C
o
o
o
o
25 C
-40 C TO 85 C
TEST
PARAMETER
HC TYPES
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
MAX
MAX
UNITS
CC
Propagation Delay,
Any Input to ΣO
t
, t
C = 50pF
2
-
-
200
40
34
-
250
50
43
-
300
60
51
-
ns
ns
ns
ns
PLH PHL
L
4.5
6
5
-
C = 15pF
17
L
3
CD74HC280, CD74HCT280
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
-55 C TO
125 C
o
o
o
o
25 C
-40 C TO 85 C
TEST
PARAMETER
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
200
40
34
-
MAX
250
50
43
-
MAX
300
60
51
-
UNITS
ns
CC
Propagation Delay,
Any Input to ΣE
t
, t
C = 50pF
2
-
-
PLH PHL
L
4.5
ns
6
5
2
-
ns
C = 15pF
17
-
ns
L
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
L
75
15
13
10
-
95
19
16
10
-
110
22
19
10
-
ns
4.5
6
-
ns
-
ns
C
-
-
-
-
pF
pF
I
Power Dissipation
Capacitance
C
5
58
PD
(Notes 5, 6)
HCT TYPES
Propagation Delay,
Any Input to ΣO
t
, t
PLH PHL
C = 50pF
4.5
5
-
19
-
45
-
56
-
68
-
ns
ns
ns
ns
ns
pF
pF
L
C = 15pF
L
Propagation Delay,
Any Input to ΣE
t , t
PLH PHL
C = 50pF
4.5
5
42
-
53
-
63
-
L
C = 15pF
18
-
L
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
15
10
-
19
10
-
22
10
-
C
-
-
-
IN
Power Dissipation
Capacitance
C
5
58
PD
(Notes 5, 6)
NOTES:
5. C
is used to determine the dynamic power consumption, per package.
2
PD
6. P = V
f (C
PD
+ C ) where f = Input Frequency, f = Output Frequency, C = Output Load Capacitance, V
= Supply Voltage.
D
CC
i
L
i
O
L
CC
Test Circuits and Waveforms
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
4
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