CD74HCT283M96E4 [TI]
High-Speed CMOS Logic 4-Bit Binary Full Adder with Fast Carry; 高速CMOS逻辑4位二进制全加器与快速进
| 型号： | CD74HCT283M96E4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic 4-Bit Binary Full Adder with Fast Carry |
| 文件： | 总11页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC283, CD74HC283,
CD54HCT283, CD74HCT283
Data sheet acquired from Harris Semiconductor
SCHS176D
High-Speed CMOS Logic
4-Bit Binary Full Adder with Fast Carry
November 1997 - Revised October 2003
Features
Description
• Adds Two Binary Numbers
The ’HC283 and ’HCT283 binary full adders add two 4-bit
binary numbers and generate a carry-out bit if the sum
exceeds 15.
• Full Internal Lookahead
[ /Title
(CD74
HC283
,
CD74
HCT28
3)
• Fast Ripple Carry for Economical Expansion
• Operates with Both Positive and Negative Logic
Because of the symmetry of the add function, this device
can be used with either all active-high operands (positive
logic) or with all active-low operands (negative logic). When
using positive logic the carry-in input must be tied low if there
is no carry-in.
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Ordering Information
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
/Sub-
ject
o
PART NUMBER
CD54HC283F3A
CD54HCT283F3A
CD74HC283E
TEMP. RANGE ( C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
• Significant Power Reduction Compared to LSTTL
Logic ICs
(High
Speed
CMOS
Logic
4-Bit
Binary
Full
• HC Types
- 2V to 6V Operation
CD74HC283M
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
CD74HC283MT
CD74HC283M96
CD74HCT283E
CD74HCT283M
CD74HCT283MT
CD74HCT283M96
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
Adder
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
Pinout
Functional Diagram
5
4
CD54HC283, CD54HCT283
(CERDIP)
CD74HC283, CD74HCT283
(PDIP, SOIC)
A0
B0
A1
B1
A2
B2
A3
B3
S0
S1
S2
S3
C
6
3
1
TOP VIEW
2
S1
B1
A1
S0
A0
B0
1
2
3
4
5
6
7
8
16 V
CC
15 B2
14 A2
13 S2
12 A3
11 B3
10 S3
14
15
12
13
10
9
11
7
C
IN
C
9
C
OUT
GND
IN
OUT
GND = 8
= 16
V
CC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC283, CD74HC283, CD54HCT283, CD74HCT283
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
67
73
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
O
CC
(SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
CC
I
O
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
2
CD54HC283, CD74HC283, CD54HCT283, CD74HCT283
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT Types
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
V
V
or V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IL
IL
IH
IH
IH
IH
High Level Output
Voltage
TTL Loads
V
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
OH
Low Level Output
Voltage
CMOS Loads
V
or V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
V
OL
IL
TTL Loads
Input Leakage
Current
I
V
to
-
-
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
ICC
V
or
160
490
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
V
4.5 to
5.5
100
360
450
CC
CC
- 2.1
(Note 2)
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
C
1.5
1
IN
B1, A1, A0
B0
0.4
0.5
B3, A3, A2, B2
NOTE: Unit Load is ∆I
CC
Specifications table, e.g., 360µA max at 25 C.
limit specified in DC Electrical
o
Switching Specifications Input t , t = 6ns
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
Propagation Delay
to S0
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
t
t
C = 50pF
2
-
-
-
160
32
-
-
-
-
-
200
40
-
-
-
-
-
240
48
-
ns
ns
ns
ns
PLH, PHL
L
C
4.5
5
-
-
-
IN
C = 15pF
13
-
L
C = 50pF
6
27
34
41
L
3
CD54HC283, CD74HC283, CD54HCT283, CD74HCT283
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
C
C
C
to S1
t
t
t
t
t
t
C = 50pF
2
-
-
-
180
36
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
225
45
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
270
54
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
IN
IN
IN
PLH, PHL
L
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C = 15pF
15
-
L
C = 50pF
6
31
195
39
-
38
245
49
-
46
295
59
-
L
to S2, C to C
IN
t
C = 50pF
2
-
OUT
PLH, PHL
L
4.5
5
-
C = 15pF
16
-
L
C = 50pF
6
33
230
46
-
42
290
58
-
50
345
69
-
L
to S3
t
C = 50pF
2
-
PLH, PHL
L
4.5
5
-
C = 15pF
19
-
L
C = 50pF
6
39
195
39
-
49
245
49
-
59
295
59
-
L
An, Bn to C
OUT
t
C = 50pF
2
-
PLH, PHL
L
4.5
5
-
C = 15pF
16
-
L
C = 50pF
6
33
210
42
-
42
265
53
-
50
315
63
-
L
An, Bn to Sn
t
C = 50pF
2
-
PLH, PHL
L
4.5
5
-
C = 15pF
18
-
L
C = 50pF
6
36
75
15
13
10
-
45
95
19
16
10
-
54
110
22
19
10
-
L
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
2
-
L
4.5
6
-
-
C
C = 50pF
L
-
-
IN
Power Dissipation
C
-
5
70
PD
Capacitance, (Notes 3, 4)
HCT TYPES
Propagation Delay
C
C
C
C
to S0
to S1
t
t
t
t
t
t
, t
C = 15pF
5
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
13
-
-
31
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
39
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
47
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
IN
IN
IN
PLH PHL
L
C = 50pF
L
, t
PLH PHL
C = 15pF
18
L
C = 50pF
4.5
5
43
-
54
-
65
-
L
to S2, C to C
IN
, t
PLH PHL
C = 15pF
19
22
20
21
OUT
L
C = 50pF
4.5
5
46
-
58
-
69
-
L
to S3
, t
PLH PHL
C = 15pF
L
C = 50pF
4.5
5
53
-
66
-
80
-
L
An, Bn to C
OUT
, t
L
C = 15pF
L
PLH PH
C = 50pF
4.5
5
48
-
60
-
72
-
L
An, Bn to Sn
, t
PLH PHL
C = 15pF
L
C = 50pF
4.5
4.5
49
15
61
19
74
22
L
Output Transition Time
t
, t
TLH THL
C = 50pF
L
4
CD54HC283, CD74HC283, CD54HCT283, CD74HCT283
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
Input Capacitance
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
10
MIN
MAX UNITS
CC
C
-
-
-
-
-
-
10
-
-
-
-
10
-
pF
pF
IN
Power Dissipation
C
5
82
-
-
PD
Capacitance, (Notes 3, 4)
NOTES:
3. C
is used to determine the dynamic power consumption, per package.
2
PD
4. P = V
f (C
PD
+ C ) where: f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
CC
i
L
i
L
Test Circuits and Waveforms
t = 6ns
f
t = 6ns
t = 6ns
t = 6ns
r
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jul-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
CDIP
PDIP
Drawing
5962-8976501EA
CD54HC283F3A
CD54HCT283F3A
CD74HC283E
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
J
16
16
16
16
1
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
J
1
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HC283M
CD74HC283M96
CD74HC283M96E4
CD74HC283ME4
CD74HC283MT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
N
N
D
D
D
D
D
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC283MTE4
CD74HCT283E
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HCT283EE4
CD74HCT283M
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HCT283M96
CD74HCT283M96E4
CD74HCT283ME4
CD74HCT283MT
CD74HCT283MTE4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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1-Jul-2005
temperature.
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Addendum-Page 2
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