CD74HCT4024 [TI]
High Speed CMOS Logic 7-Stage Binary Ripple Counter; 高速CMOS逻辑7级二进制纹波计数器
| 型号： | CD74HCT4024 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic 7-Stage Binary Ripple Counter |
| 文件： | 总7页 (文件大小：43K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC4024,
CD74HCT4024
Data sheet acquired from Harris Semiconductor
SCHS202
High Speed CMOS Logic
November 1997
7-Stage Binary Ripple Counter
at V
= 5V
Features
CC
• HCT Types
• Fully Static Operation
• Buffered Inputs
• Common Reset
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
[ /Title
(CD74
HC402
4,
CD74
HCT40
24)
/Sub-
ject
(High
Speed
CMOS
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
• Negative Edge Clocking
• Typical f
MAX
= 60 MHz at V = 5V, C = 15pF,
CC L
Description
o
T = 25 C
A
The Harris CD74HC4024 and CD74HCT4024 are 7-stage
ripple-carry binary counters. All counter stages are master-
slave flip-flops. The state of the stage advances one count
on the negative transition of each input pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Ordering Information
• Significant Power Reduction Compared to LSTTL
Logic ICs
PKG.
NO.
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
• HC Types
CD74HC4024E
-55 to 125
-55 to 125
14 Ld PDIP
E14.3
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
CD74HCT4024M
14 Ld SOIC M14.15
Pinout
CD74HC4024, CD74HCT4024
(PDIP, SOIC)
TOP VIEW
CP
1
2
3
4
5
6
7
14
13 NC
12 Q ’
V
CC
MR
Q
Q
Q
Q
7
6
5
4
1
11 Q
2
10 NC
9
8
Q
3
NC
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1683.1
Copyright © Harris Corporation 1997
1
CD74HC4024, CD74HCT4024
Functional Diagram
12
Q ’
1
1
11
9
CP
Q
Q
Q
Q
Q
Q
2
3
4
5
6
7
6
5
2
4
MR
3
TRUTH TABLE
CP COUNT
MR
OUTPUT STATE
↑
↓
L
L
No Change
Advance to Next State
All Outputs Are Low
X
H
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
Logic Diagram
1
CP
Q
CP
CP
Q
Q
CP
CP
Q
Q
CP
CP
Q
Q
CP
CP
Q
Q
CP
CP
Q
Q
CP
CP
Q
Q
CP
Q1
Q
1
2
3
4
5
6
7
CP
R
R
R
R
R
R
R
2
MR
7
GND
14
12
11
9
6
5
4
3
V
CC
Q ’
Q
Q
Q
Q
Q
Q
7
1
2
3
4
5
6
2
CD74HC4024, CD74HCT4024
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
175
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
3
CD74HC4024, CD74HCT4024
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
V
4.5 to
5.5
100
360
450
CC
CC
-2.1
NOTE: For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
CP, MR
UNIT LOADS
0.5
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
Prerequisite for Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CC
Maximum Input Pulse
Frequency
f
2
6
-
-
-
-
-
-
-
-
-
5
24
29
100
20
17
65
13
11
-
-
-
-
-
-
-
-
-
4
20
24
120
24
20
75
15
13
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
ns
MAX
4.5
30
35
80
16
14
50
10
9
6
2
Input Pulse Width
t
W
4.5
6
ns
ns
Reset Removal Time
t
2
ns
REM
4.5
6
ns
ns
4
CD74HC4024, CD74HCT4024
Prerequisite for Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL
V
(V)
MIN
80
MAX
MIN
100
20
MAX
MIN
120
24
MAX
UNITS
ns
CC
Reset Pulse Width
t
2
-
-
-
-
-
-
-
-
-
W
4.5
16
ns
6
14
17
20
ns
HCT TYPES
Maximum Input Pulse
Frequency
f
t
4.5
25
-
20
-
16
-
MHz
MAX
Input Pulse Width
Reset Recovery Time
Reset Pulse Width
t
4.5
4.5
4.5
20
10
20
-
-
-
25
13
25
-
-
-
30
15
30
-
-
-
ns
ns
ns
W
REC
t
W
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS
(V)
MIN TYP MAX
MIN
MAX
MIN
MAX UNITS
Propagation Delay Time
(Figure 1)
t
t
C = 50pF
2
-
-
140
-
175
-
210
ns
PLH,
L
PHL
CP to Q1’ Output
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
11
-
28
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
35
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
42
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
C =15pF
L
C = 50pF
6
24
75
15
-
30
95
19
-
36
110
22
-
L
Q to Q + 1
t
t
C = 50pF
2
-
n
n
PLH,
L
t
PHL
4.5
5
-
C =15pF
6
-
L
C = 50pF
6
13
170
34
-
13
215
43
-
19
255
51
-
L
MR to Q
C = 50pF
2
-
n
PLH,
L
t
PHL
4.5
5
-
14
-
6
29
75
15
13
10
-
27
95
19
16
10
-
43
110
22
19
10
-
Output Transition Time
(Figure 1)
t
, t
C = 50pF
2
-
TLH THL
L
4.5
6
-
-
Input Capacitance
C
C = 50pF
-
-
IN
L
Power Dissipation Capacitance
(Notes 4, 5)
C
C =15pF
5
30
PD
L
HCT TYPES
Propagation Delay Time
(Figure 2)
t
t
C = 50pF
4.5
-
-
40
-
50
-
60
ns
PLH,
L
PHL
CP to Q1’ Output
C =15pF
5
4.5
5
-
-
-
-
-
17
-
-
15
-
-
-
-
-
-
-
19
-
-
-
-
-
-
-
22
-
ns
ns
ns
ns
ns
L
Q to Q + 1
t
t
C = 50pF
L
n
n
PLH,
t
PHL
C =15pF
6
L
MR to Q
C = 50pF
4.5
5
-
40
-
50
-
60
-
n
PLH,
L
t
PHL
C =15pF
17
L
5
CD74HC4024, CD74HCT4024
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
SYMBOL CONDITIONS
V
CC
(V)
PARAMETER
Output Transition
MIN TYP MAX
MIN
MAX
19
10
-
MIN
MAX UNITS
t
, t C = 50pF
4.5
-
-
-
-
-
-
15
10
-
-
-
-
-
-
-
22
10
-
ns
pF
pF
TLH THL
L
Input Capacitance
C
C =15pF
L
IN
Power Dissipation Capacitance
(Notes 4, 5)
C
C =15pF
5
30
PD
L
NOTES:
4. C
PD
is used to determine the dynamic power consumption, per package.
2
2
1
2
3
4
5
6
7
5. P = V
CC
f + ∑ (C V
CC
fi/M) where: M = 2 , 2 , 2 , 2 ,2 , 2 , 2 f = Input Frequency, C = Output Load Capacitance, V = Supply
CC
D
i
L
i
L
Voltage.
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
fC
t C
f
L
L
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%. accordance with device truth table. For f , input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6
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