CD74HCT4067ME4 [TI]
High-Speed CMOS Logic 16-Channel Analog Multiplexer/Demultiplexer; 高速CMOS逻辑16通道模拟多路复用器/多路解复用器
| 型号： | CD74HCT4067ME4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic 16-Channel Analog Multiplexer/Demultiplexer |
| 文件： | 总16页 (文件大小：724K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC4067,
CD74HCT4067
Data sheet acquired from Harris Semiconductor
SCHS209C
High-Speed CMOS Logic
16-Channel Analog Multiplexer/Demultiplexer
February 1998 - Revised July 2003
Features
Description
• Wide Analog Input Voltage Range
• Low “ON” Resistance
The CD74HC4067 and CD74HCT4067 devices are digitally
controlled analog switches that utilize silicon-gate CMOS
technology to achieve operating speeds similar to LSTTL,
with the low power consumption of standard CMOS
integrated circuits.
[ /Title
(CD74
HC406
7,
CD74
HCT40
67)
/Sub-
ject
(High-
Speed
CMOS
- V
- V
= 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . 70Ω(Typ)
CC
CC
= 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Ω(Typ)
• Fast Switching and Propagation Speeds
These analog multiplexers/demultiplexers control analog
voltages that may vary across the voltage supply range.
They are bidirectional switches thus allowing any analog
input to be used as an output and vice-versa. The switches
have low “on” resistance and low “off” leakages. In addition,
these devices have an enable control which when high will
disable all switches to their “off” state.
• “Break-Before-Make” Switching. . . . .6ns (Typ) at 4.5V
• Available in Both Narrow and Wide-Body Plastic
Packages
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Ordering Information
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
TEMP. RANGE
o
PART NUMBER
CD74HC4067E
( C)
PACKAGE
24 Ld PDIP
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• Significant Power Reduction Compared to LSTTL
Logic ICs
CD74HC4067M
24 Ld SOIC
24 Ld SOIC
24 Ld SSOP
24 Ld SOIC
CD74HC4067M96
CD74HC4067SM96
CD74HCT4067M
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
Pinout
CD74HC4067 (PDIP, SOIC, SSOP)
CD74HCT4067 (SOIC)
TOP VIEW
COMMON
1
2
24
V
CC
INPUT/OUTPUT
I
I
23 I
22 I
21 I
20 I
19 I
18 I
17 I
16 I
7
6
5
4
3
2
1
0
0
1
8
3
9
I
4
10
11
12
13
14
15
I
5
I
6
I
7
I
8
I
9
S
S
10
11
15 E
14 S
13 S
2
3
GND 12
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD74HC4067, CD74HCT4067
Functional Diagram
I
0
9
10
S
S
S
S
0
1
2
3
11
14
13
P
N
BINARY
1 OF 16
DECODER
= 5 STAGES
14 - OUTPUT CIRCUITS
SAME AS ABOVE
(WITH ANALOG INPUTS)
COMMON
INPUT/
OUTPUT
1
S
N
I
TO I
1
14
E = 4 STAGES
P
N
16
15
I
15
E
TRUTH TABLE
SELECTED
CHANNEL
S0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
S1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S2
S3
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
E
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
None
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H= High Level
L= Low Level
X= Don’t Care
2
CD74HC4067, CD74HCT4067
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
Thermal Resistance (Typical)
θ
( C/W)
CC
(Voltages Referenced to Ground) . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
JA
E (PDIP) Package, Note 1. . . . . . . . . . . . . . . . . . . .
M (SOIC) Package, Note 2 . . . . . . . . . . . . . . . . . . .
SM (SSOP) Package, Note 2. . . . . . . . . . . . . . . . . .
67
46
63
IK
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
I
I
CC
o
DC Drain Current, I
O
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
o
o
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
O
CC
DC Output Diode Current, I
OK
For V < -0.5V or V > V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The package thermal impedance is calculated in accordance with JESD 51-3.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
V
(V)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
IS
CC
High Level Input
Voltage
V
-
-
-
2
1.5
-
-
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
Ω
Ω
Ω
Ω
Ω
Ω
IH
4.5
3.15
3.15
3.15
6
2
4.2
-
-
4.2
-
4.2
-
Low Level Input
Voltage
V
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
160
140
180
160
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
200
175
225
200
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
240
210
270
240
-
IL
4.5
6
-
-
Maximum “ON”
Resistance
R
V
or
V
or
4.5
6
70
60
90
80
10
8.5
ON
CC
GND
CC
GND
I
= 1mA
O
V
to
V
to
4.5
6
CC
GND
CC
GND
Maximum “ON”
Resistance Between
Any Two Switches
∆R
ON
-
4.5
6
-
-
-
-
Switch “Off” Leakage
Current
I
E = V
V
GND
or
6
-
-
±0.8
-
±8
-
±8
µA
IZ
CC
CC
16 Channels
Logic Input Leakage
Current
I
V
GND
or
-
6
-
-
±0.1
-
±1
-
±1
µA
I
CC
3
CD74HC4067, CD74HCT4067
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL V (V)
V
(V)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
IS
CC
Quiescent Device
Current
I
V
GND
or
-
6
-
-
8
-
80
-
160
µA
CC
CC
I
= 0mA
O
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5
2
-
-
-
2
-
-
2
-
-
V
V
IH
Low Level Input
Voltage
V
4.5
4.5
4.5
4.5
-
0.8
160
180
-
0.8
200
225
-
0.8
240
270
-
IL
Maximum “ON”
Resistance
R
V
or
V
or
-
70
90
10
-
-
Ω
Ω
Ω
ON
CC
GND
CC
GND
I
= 1mA
O
V
to
V
to
-
-
-
CC
GND
CC
GND
Maximum “ON”
∆R
ON
-
-
-
-
-
Resistance Between
Any Two Switches
Switch “Off” Leakage
Current
16 Channels
I
E = V
V
GND
or
6
6
-
-
-
-
±0.8
±0.1
-
-
±8
±1
-
-
±8
±1
µA
µA
IZ
CC
CC
Logic Input Leakage
Current
I
V
or
-
I
CC
GND
(Note 3)
Quiescent Device
Current
I
V
or
-
-
6
-
-
-
-
8
-
-
80
-
-
160
490
µA
µA
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
V
100
360
450
CC
CC
-2.1
(Note 4)
NOTES:
3. Any voltage between V
and GND.
CC
4. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOAD
S - S
0
0.5
0.3
3
E
NOTE: Unit Load is ∆I
CC
tions table, e.g., 360µA max at 25 C.
limit specified in DC Electrical Specifica-
o
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
Propagation Delay Time
Switch In to Out
t
, t
C = 50pF
2
4.5
6
-
-
-
-
-
-
75
15
13
-
-
-
-
-
95
19
16
-
-
-
-
-
110
22
19
-
ns
ns
ns
ns
PLH PHL
L
-
C = 15pF
5
6
L
4
CD74HC4067, CD74HCT4067
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
Switch Turn On
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
345
69
59
-
MIN
MAX
415
83
71
-
UNITS
ns
t
t
t
t
, t
C = 50pF
2
4.5
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
275
55
47
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PZH PZL
L
E to Out
ns
-
ns
C = 15pF
5
23
-
ns
L
Switch Turn On
Sn to Out
, t
PZH PZL
C = 50pF
2
300
60
51
-
375
75
64
-
450
90
76
-
ns
L
4.5
6
-
ns
-
ns
C = 15pF
5
25
-
ns
L
Switch Turn Off
E to Out
, t
PHZ PLZ
C = 50pF
2
275
55
47
-
345
69
59
-
415
83
71
-
ns
L
4.5
6
-
ns
-
ns
C = 15pF
5
23
-
ns
L
Switch Turn Off
Sn to Out
, t
PHZ PLZ
C = 50pF
2
290
58
49
-
365
73
62
-
435
87
74
-
ns
L
4.5
6
-
ns
-
ns
C = 50pF
L
5
21
-
ns
Input (Control) Capacitance
C
-
-
-
10
-
10
-
10
-
pF
pF
I
Power Dissipation Capacitance
(Notes 5, 6)
C
5
93
PD
HCT TYPES
Propagation Delay Time
Switch In to Out
t
, t
C = 50pF
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
6
15
-
-
-
-
-
-
-
-
-
-
-
-
-
19
-
-
-
-
-
-
-
-
-
-
-
-
-
22
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
PLH PHL
L
C = 15pF
L
Switch Turn On
E to Out
t
t
t
t
, t
C = 50pF
4.5
5
-
60
-
75
-
90
-
PZH PZL
L
C = 15pF
25
-
L
Switch Turn On
Sn to Out
, t
PZH PZL
C = 50pF
4.5
5
60
-
75
-
90
-
L
C = 15pF
25
-
L
Switch Turn Off
E to Out
, t
PHZ PLZ
C = 50pF
4.5
5
55
-
69
-
83
-
L
C = 15pF
23
-
L
Switch Turn Off
Sn to Out
, t
PHZ PLZ
C = 50pF
4.5
5
58
-
73
-
87
-
L
C = 15pF
L
21
-
Input (Control) Capacitance
C
-
-
-
10
-
10
-
10
-
I
Power Dissipation Capacitance
(Notes 5, 6)
C
5
96
PD
NOTES:
5. C
is used to determine the dynamic power consumption, per package.
PD
6. P = C
2
2
V
f + Σ (C + C ) V
f where f = input frequency, f = output frequency, C = output load capacitance, C = switch
o i o L S
D
PD CC
i
L
S
CC
capacitance, V
= supply voltage.
CC
5
CD74HC4067, CD74HCT4067
o
Analog Channel Specifications T = 25 C
A
PARAMETER
TEST CONDITIONS
Figure 4, Notes 7, 8
Figure 5
V
(V)
HC/HCT
89
UNITS
MHz
%
CC
Switch Frequency Response Bandwidth at -3dB (Figure 2)
Sine Wave Distortion
4.5
4.5
4.5
0.051
TBE
Feedthrough Noise
E to Switch
Figure 6, Notes 8, 9
mV
Feedthrough Noise
S to Switch
TBE
mV
Switch “OFF” Signal Feedthrough (Figure 3)
Figure 7
4.5
-75
5
dB
pF
pF
Switch Input Capacitance, C
-
-
S
Common Capacitance, C
NOTES:
50
COM
7. Adjust input level for 0dBm at output, f = 1MHz.
8. V is centered at V /2.
IS CC
9. Adjust input for 0dBm at V
.
IS
Typical Performance Curves
0
-1
-2
-3
-4
-5
-6
-7
-8
140
o
= 25 C, GND = 0V
T
A
120
100
80
60
40
20
0
V
= 4.5V
CC
V
= 4.5V
CC
= 50Ω
R
-9
L
o
T
= 25 C
A
-10
10
4
5
6
7
8
0
1
2
3
4
5
6
7
8
9
10
10
10
FREQUENCY, f (Hz)
10
10
INPUT SIGNAL VOLTAGE, V (V)
IS
FIGURE 1. TYPICAL “ON” RESISTANCE vs INPUT SIGNAL
VOLTAGE
FIGURE 2. TYPICAL SWITCH FREQUENCY RESPONSE
0
V
= 4.5V
CC
= 50Ω
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
R
L
o
T
= 25 C
A
4
5
6
7
8
10
10
10
FREQUENCY, f (Hz)
10
10
FIGURE 3. TYPICAL SWITCH-OFF SIGNAL FEEDTHROUGH vs FREQUENCY
6
CD74HC4067, CD74HCT4067
Analog Test Circuits
V
V
CC
CC
SINE
10µF
0.1µF
V
OS
WAVE
V
OS
SWITCH
ON
SWITCH
ON
V
V
IS
IS
10kΩ
50pF
50Ω
10pF
DISTORTION
METER
dB
METER
V
/2
V
/2
CC
CC
f
= 1kHz TO 10kHz
IS
FIGURE 4. FREQUENCY RESPONSE TEST CIRCUIT
FIGURE 5. SINE WAVE DISTORTION TEST CIRCUIT
f
≥ 1MHz SINEWAVE
IS
V
CC
V
CC
R = 50Ω
C = 10pF
V
= V
C
IL
SWITCH
600Ω
0.1µF
V
OS
ALTERNATING
ON AND OFF
SWITCH
OFF
V
IS
V
OS
t , t ≤ 6ns
600Ω
r
f
R
R
C
10pF
f
= 1MHz
CONT
50% DUTY
dB
METER
CYCLE
SCOPE
V
/2
V
/2
CC
V
/2
CC
CC
FIGURE 6. CONTROL-TO-SWITCH FEEDTHROUGH NOISE
TEST CIRCUIT
FIGURE 7. SWITCH OFF SIGNAL FEEDTHROUGH TEST
CIRCUIT
Test Circuits and Waveforms
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 8. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 9. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
7
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
CD74HC4067E
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SSOP
SSOP
SSOP
SOIC
SOIC
SOIC
N
24
24
24
24
24
24
24
24
24
24
24
24
24
24
15
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
CU NIPDAU
N / A for Pkg Type
CD74HC4067E
CD74HC4067EE4
CD74HC4067M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
N
15
25
Pb-Free
(RoHS)
N / A for Pkg Type
CD74HC4067E
HC4067M
HC4067M
HC4067M
HC4067M
HC4067M
HC4067M
HP4067
DW
DW
DW
DW
DW
DW
DB
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
CD74HC4067M96
CD74HC4067M96E4
CD74HC4067M96G4
CD74HC4067ME4
CD74HC4067MG4
CD74HC4067SM96
CD74HC4067SM96E4
CD74HC4067SM96G4
CD74HCT4067M
2000
2000
2000
25
Green (RoHS CU NIPDAU | CU SN
& no Sb/Br)
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
25
Green (RoHS
& no Sb/Br)
2000
2000
2000
25
Green (RoHS
& no Sb/Br)
DB
Green (RoHS
& no Sb/Br)
HP4067
DB
Green (RoHS
& no Sb/Br)
HP4067
DW
DW
DW
Green (RoHS
& no Sb/Br)
HCT4067M
HCT4067M
HCT4067M
CD74HCT4067ME4
CD74HCT4067MG4
25
Green (RoHS
& no Sb/Br)
25
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD74HCT4067 :
Automotive: CD74HCT4067-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC4067M96
CD74HC4067M96G4
CD74HC4067SM96
SOIC
SOIC
SSOP
DW
DW
DB
24
24
24
2000
2000
2000
330.0
330.0
330.0
24.4
24.4
16.4
10.75 15.7
10.75 15.7
2.7
2.7
2.5
12.0
12.0
12.0
24.0
24.0
16.0
Q1
Q1
Q1
8.2
8.8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CD74HC4067M96
CD74HC4067M96G4
CD74HC4067SM96
SOIC
SOIC
SSOP
DW
DW
DB
24
24
24
2000
2000
2000
366.0
367.0
367.0
364.0
367.0
367.0
50.0
45.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MPDI006B – SEPTEMBER 2001 – REVISED APRIL 2002
N (R–PDIP–T24)
PLASTIC DUAL–IN–LINE
1.222 (31,04) MAX
24
13
0.360 (9,14) MAX
1
12
0.070 (1,78) MAX
0.200 (5,08) MAX
0.020 (0,51) MIN
0.425 (10,80) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0’–15’
0.021 (0,53)
0.015 (0,38)
0.010 (0,25) NOM
4040051–3/D 09/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS–010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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