CD74HCT4075 [TI]
High Speed CMOS Logic Triple 3-Input OR Gate; 高速CMOS逻辑三路3输入或门
| 型号： | CD74HCT4075 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic Triple 3-Input OR Gate |
| 文件： | 总6页 (文件大小：36K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC4075,
CD74HCT4075
Data sheet acquired from Harris Semiconductor
SCHS210
High Speed CMOS Logic
Triple 3-Input OR Gate
August 1997
Features
Description
• Buffered Inputs
The Harris CD74HC4075, CD74HCT4075 logic gates utilize
silicon-gate CMOS technology to achieve operating speeds
similar to LSTTL gates with the low power consumption of
standard CMOS integrated circuits. All devices have the
ability to drive 10 LSTTL loads. The 74HCT logic family is
functionally pin compatible with the standard 74LS logic
family.
• Typical Propagation Delay: 8ns at V
o
= 5V,
[ /Title
(CD74H
C4075,
CD74H
CT4075)
/Subject
(High
Speed
CMOS
Logic
CC
C = 15pF, T = 25 C
L
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Ordering Information
PKG.
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
NO.
E14.3
E14.3
• Significant Power Reduction Compared to LSTTL
Logic ICs
CD74HC4075E
CD74HC4075E
CD74HC4075M
CD74HC4075M
CD54HC4075H
CD54HCT4075H
CD54HC4075W
CD54HCT4075W
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
14 Ld PDIP
14 Ld PDIP
• HC Types
Triple 3-
Input
- 2V to 6V Operation
14 Ld SOIC M14.15
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
14 Ld SOIC M14.15
• HCT Types
Die
- 4.5V to 5.5V Operation
Die
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
Wafer
Wafer
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
NOTE: When ordering, use the entire part number. Add the suffix 96
to obtain the variant in the tape and reel.
Pinout
CD74HC4075, CD74HCT4075
(PDIP, SOIC)
TOP VIEW
2A
2B
1
2
3
4
5
6
7
14 V
CC
13 3C
12 3B
11 3A
10 3Y
1A
1B
1C
1C
9
8
2Y
2C
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1778.1
Copyright © Harris Corporation 1997
1
CD74HC4075, CD74HCT4075
Functional Diagram
3
1A
6
9
4
5
1Y
2Y
1B
1C
1
2A
2B
2C
2
8
11
12
13
3A
10
3Y
3B
3C
GND = 7
= 14
V
CC
TRUTH TABLE
INPUTS
OUTPUT
nA
L
nB
L
nC
L
nY
L
H
X
X
X
H
H
X
X
H
X
H
H
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Irrelevant
Logic Diagram
nA
nB
nC
nY
2
CD74HC4075, CD74HCT4075
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1)
θ
( C/W)
θ
( C/W)
CC
DC Input Diode Current, I
JA
JC
PDIP Package . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . .
100
180
N/A
N/A
IK
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature (Hermetic Package or Die) . . . 175 C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
o
DC Output Source or Sink Current per Output Pin, I
O
o
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
(SOIC - Lead Tips Only)
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
-
-
-
-
-
-
Low Level Input
Voltage
V
-
2
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
V
or V
IH IL
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
-0.02
-0.02
-4
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-5.2
Low Level Output
Voltage
CMOS Loads
V
or V
IH IL
0.02
0.02
0.02
4
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
5.2
Input Leakage
Current
I
V
or
-
6
6
-
-
-
-
±0.1
-
-
±1
-
-
±1
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
0
2
20
40
CC
CC
GND
3
CD74HC4075, CD74HCT4075
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
±0.1
2
-
-
-
±1
20
-
-
-
±1
40
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note)
∆I
V
4.5 to
5.5
100
360
450
490
CC
CC
-2.1
NOTE: For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
All
UNIT LOADS
1.6
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.
CC
o
Switching Specifications Input t , t = 6ns
r
f
o
-40 C TO
85 C
o
o
o
o
25 C
-55 C TO 125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay,
Input to Output (Figure 1)
t
t
C = 50pF
2
-
-
-
100
20
17
-
-
-
-
-
-
-
-
-
125
25
21
-
-
-
-
-
-
-
-
-
150
30
26
-
ns
ns
ns
ns
ns
ns
ns
pF
PLH, PHL
L
4.5
6
-
-
-
-
-
-
-
-
C = 15pF
5
8
-
L
Transition Times (Figure 1)
Input Capacitance
t
, t
TLH THL
C = 50pF
L
2
75
15
13
10
95
19
16
10
110
22
19
10
4.5
6
-
-
C
-
-
-
IN
4
CD74HC4075, CD74HCT4075
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
-40 C TO
85 C
o
o
o
o
25 C
-55 C TO 125 C
TEST
PARAMETER
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Power Dissipation Capacitance
(Notes 2, 3)
C
-
5
-
26
-
-
-
-
-
pF
PD
HCT TYPES
Propagation Delay, Input to
Output (Figure 2)
t
, t
C = 50pF
4.5
5
-
-
-
-
-
-
9
-
24
-
-
-
-
-
-
30
-
-
-
-
-
-
36
-
ns
ns
ns
pF
pF
PLH PHL
L
C = 15pF
L
Transition Times (Figure 2)
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
15
10
-
19
10
-
22
10
-
C
-
-
-
IN
Power Dissipation Capacitance
(Notes 2, 3)
C
5
28
PD
NOTES:
2. C
PD
is used to determine the dynamic power consumption, per gate.
2
3. P = V
CC
f (C
PD
+ C ) where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
i
L
i
L
Test Circuits and Waveforms
t = 6ns
t = 6ns
f
r
t = 6ns
f
t = 6ns
r
V
CC
3V
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
TLH
THL
t
t
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
t
t
PLH
PLH
PHL
PHL
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
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