CD74HCT4514 [TI]
HIGH-SPEED CMOS LOGIC 4-TO-16 LINE DECODER/DEMULTIPLEXER WITH INPUT LATCHES; 高速CMOS逻辑4至16线译码器/解复用器与输入锁存器
| 型号： | CD74HCT4514 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED CMOS LOGIC 4-TO-16 LINE DECODER/DEMULTIPLEXER WITH INPUT LATCHES |
| 文件： | 总14页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC4514, CD74HC4514,
CD74HC4515
Data sheet acquired from Harris Semiconductor
SCHS280C
High-Speed CMOS Logic 4- to 16-Line
November 1997 - Revised July 2003
Decoder/Demultiplexer with Input Latches
Features
Description
• Multifunction Capability
The CD54HC4514, CD74HC4514, and CD74HC4515 are
high-speed silicon gate devices consisting of a 4-bit strobed
latch and a 4- to 16-line decoder. The selected output is
enabled by a low on the enable input (E). A high on E inhibits
selection of any output. Demultiplexing is accomplished by
- Binary to 1-of-16 Decoder
- 1-to-16 Line Demultiplexer
• Fanout (Over Temperature Range)
[ /Title
(CD74
HC451
4,
CD74
HC451
5)
/Sub-
ject
(High
Speed
CMOS
using the E input as the data input and the select inputs (A0-
A3) as addresses. This E input also serves as a chip select
when these devices are cascaded.
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
When Latch Enable (LE) is high the output follows changes
in the inputs (see truth table). When LE is low the output is
isolated from changes in the input and remains at the level
(high for the 4514, low for the 4515) it had before the latches
were enabled. These devices, enhanced versions of the
equivalent CMOS types, can drive 10 LSTTL loads.
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
Ordering Information
- High Noise Immunity: N = 30%, N = 30% of V
IL
IH
CC
at V
= 5V
CC
o
PART NUMBER
CD54HC4514F3A
CD74HC4514E
TEMP. RANGE ( C)
-55 to 125
PACKAGE
24 Ld CERDIP
24 Ld PDIP
24 Ld PDIP
24 Ld SOIC
24 Ld SOIC
24 Ld PDIP
24 Ld PDIP
24 Ld SOIC
24 Ld SOIC
Pinout
-55 to 125
CD54HC4514
(CERDIP)
CD74HC4514, CD74HC4515
(PDIP, SOIC)
CD74HC4514EN
CD74HC4514M
CD74HC4514M96
CD74HC4515E
-55 to 125
-55 to 125
TOP VIEW
-55 to 125
-55 to 125
LE
A0
A1
Y7
Y6
Y5
Y4
Y3
Y1
1
2
3
4
5
6
7
8
9
24
V
CC
23 E
CD74HC4515EN
CD74HC4515M
CD74HC4515M96
-55 to 125
22 A3
21 A2
20 Y10
19 Y11
18 Y8
-55 to 125
-55 to 125
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
17 Y9
16 Y14
15 Y15
14 Y12
13 Y13
Y2 10
Y0 11
GND 12
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC4514, CD74HC4514, CD74HC4515
Functional Diagram
HC
4514
HC
4515
11
9
10
8
7
6
5
4
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
2
3
A0
A1
A2
A3
4-TO-16
LATCH
21
22
18
17
20
19
14
13
16
15
Y8
Y8
DECODER
Y9
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y10
Y11
Y12
Y13
Y14
Y15
1
LE
23
GND = 12
= 24
E
V
CC
DECODE TRUTH TABLE (LE = 1)
DECODER INPUTS
ADDRESSED OUTPUT
4514 = LOGIC 1 (HIGH)
4515 = LOGIC 0 (HIGH)
ENABLE
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
All Outputs = 0, 4514
All Outputs = 1, 4515
X = Don’t Care; Logic 1 = High; Logic 0 = Low
2
CD54HC4514, CD74HC4514, CD74HC4515
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
E (PDIP) Package (Note 1) . . . . . . . . . . . . . . . . . . .
EN (PDIP) Package (Note 1). . . . . . . . . . . . . . . . . .
M (SOIC) Package (Note 2). . . . . . . . . . . . . . . . . . .
67
67
46
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
DC Drain Current, per Output, I
O
o
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
O
CC
DC Output Source or Sink Current per Output Pin, I
O
(SOIC - Lead Tips Only)
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
CC
I
O
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The package thermal impedance is calculated in accordance with JESD 51-3.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
V
IH
-
-
-
-
-
-
Low Level Input
Voltage
V
-
2
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
4.4
5.9
-
-
-
-
-
-
-
1.9
4.4
5.9
-
-
-
-
-
-
-
1.9
4.4
5.9
-
-
-
-
-
-
-
OH
-0.02
-0.02
-
4.5
6
High Level Output
Voltage
TTL Loads
-
-4
4.5
6
3.98
5.48
3.84
5.34
3.7
5.2
-5.2
3
CD54HC4514, CD74HC4514, CD74HC4515
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
O
(V)
MIN
TYP
MAX
0.1
MIN
MAX
0.1
0.1
0.1
-
MIN
MAX
0.1
0.1
0.1
-
UNITS
I
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
0.02
0.02
0.02
-
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
OL
4.5
6
0.1
0.1
V
Low Level Output
Voltage
TTL Loads
-
-
V
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
V
5.2
-
V
Input Leakage
Current
I
V
or
6
µA
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
Prerequisite For Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
LE Pulse Width
t
-
-
-
2
4.5
6
75
30
35
100
20
17
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
95
19
16
125
25
21
0
-
-
-
-
-
-
-
-
-
110
22
19
150
30
26
0
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
W
Select to LE Set-Up Time
Select to LE Hold Time
t
2
SU
4.5
6
t
2
H
4.5
6
0
0
0
0
0
0
Switching Specifications C = 50pF, Input t , t = 6ns
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay
Select to Outputs
t
, t
C
= 50pF
PHL PLH
L
2
-
-
-
275
55
-
-
-
-
-
-
-
-
-
345
69
-
-
-
-
-
-
-
-
-
415
83
-
ns
ns
ns
ns
ns
ns
ns
ns
4.5
5
-
-
-
-
-
-
-
C
C
C
= 15pF
= 50pF
= 50pF
23
-
L
L
L
6
47
225
45
-
59
280
56
-
71
340
68
-
LE to Outputs
t
t
2
-
PHL, PLH
4.5
5
-
C
C
= 15pF
= 50pF
19
-
L
6
38
48
58
L
4
CD54HC4514, CD74HC4514, CD74HC4515
Switching Specifications C = 50pF, Input t , t = 6ns (Continued)
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
E to Outputs
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
t
t
C
= 50pF
2
-
-
-
175
35
-
-
-
-
-
-
-
-
-
-
220
44
-
-
-
-
-
-
-
-
-
-
265
53
-
ns
ns
ns
ns
ns
ns
ns
pF
pF
PHL, PLH
L
4.5
5
-
-
C
C
C
= 15pF
= 50pF
= 50pF
14
-
L
L
L
6
-
30
75
15
13
10
-
37
95
19
16
10
-
45
110
22
19
10
-
Output Transition Time
Input Capacitance
t
, t
THL TLH
2
-
-
4.5
6
-
-
-
-
C
C
= 50pF
-
-
10
-
-
IN
L
Power Dissipation Capacitance
(Notes 3, 4)
C
5
70
PD
NOTES:
3. C
is used to determine the dynamic power consumption, per package.
2
PD
4. P = V
f (C
PD
+ C ) where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
CC
i
L
i
L
Test Circuits and Waveforms
t = 6ns
t = 6ns
f
r
I
V
CC
t
+ t
=
WL
WH
90%
50%
10%
t C
fC
t C
f
L
L
r
L
INPUT
V
CC
GND
90%
10%
CLOCK
50%
10%
50%
t
50%
GND
t
t
TLH
THL
t
90%
50%
10%
WH
WL
INVERTING
OUTPUT
NOTE: Outputs should be switching from 10% V
to 90% V
in
t
t
CC
CC
PLH
PHL
accordance with device truth table. For f
, input duty cycle = 50%.
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t = 6ns
t = 6ns
f
r
V
CC
90%
50%
10%
INPUT
GND
t
t
TLH
THL
90%
50%
10%
INVERTING
OUTPUT
t
t
PLH
PHL
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
5
CD54HC4514, CD74HC4514, CD74HC4515
Test Circuits and Waveforms (Continued)
t C
t C
f L
t C
t C
r L
f
L
r
L
V
V
CC
CC
90%
10%
90%
10%
CLOCK
INPUT
CLOCK
INPUT
50%
50%
GND
GND
t
t
H(H)
t
t
H(L)
H(H)
H(L)
V
V
CC
CC
DATA
INPUT
DATA
INPUT
50%
50%
GND
GND
t
t
t
t
SU(L)
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
90%
50%
TLH
THL
TLH
THL
90%
90%
OUTPUT
OUTPUT
10%
10%
t
t
t
t
PHL
PHL
PLH
PLH
t
t
REM
REM
V
V
CC
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
50%
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 4. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
6
PACKAGE OPTION ADDENDUM
www.ti.com
17-Oct-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
PDIP
Drawing
5962-9865501QJA
CD54HC4514F3A
CD74HC4514E
ACTIVE
ACTIVE
ACTIVE
J
J
24
24
24
1
1
TBD
TBD
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
N
15
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-NC-NC-NC
CD74HC4514EE4
CD74HC4514EN
CD74HC4514ENE4
CD74HC4514M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
N
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
15
15
15
Pb-Free
(RoHS)
NT
NT
DW
DW
DW
DW
N
Pb-Free
(RoHS)
Pb-Free
(RoHS)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC4514M96
CD74HC4514M96E4
CD74HC4514ME4
CD74HC4515E
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
15
15
15
15
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-NC-NC-NC
CD74HC4515EE4
CD74HC4515EN
CD74HC4515ENE4
CD74HC4515M
N
Pb-Free
(RoHS)
NT
NT
DW
DW
DW
DW
Pb-Free
(RoHS)
Pb-Free
(RoHS)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC4515M96
CD74HC4515M96E4
CD74HC4515ME4
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Oct-2005
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MCDI004A – JANUARY 1995 – REVISED NOVEMBER 1997
J (R-GDIP-T**)
CERAMIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
B
13
24
C
12
1
0.065 (1,65)
0.045 (1,14)
Lens Protrusion (Lens Optional)
0.010 (0.25) MAX
0.090 (2,29)
0.060 (1,53)
0.175 (4,45)
0.140 (3,56)
A
Seating Plane
0.018 (0,46) MIN
0.125 (3,18) MIN
0.022 (0,56)
0.014 (0,36)
0.100 (2,54)
0.012 (0,30)
0.008 (0,20)
24
28
32
40
PINS **
DIM
”A”
NARR
WIDE
NARR
WIDE
NARR
WIDE
NARR
WIDE
0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85)
0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99)
1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53)
1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61)
0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19)
0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)
MAX
MIN
MAX
MIN
”B”
”C”
MAX
MIN
4040084/C 10/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Window (lens) added to this group of packages (24-, 28-, 32-, 40-pin).
D. This package can be hermetically sealed with a ceramic lid using glass frit.
E. Index point is provided on cap for terminal identification.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI004 – OCTOBER 1994
NT (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
A
PINS **
24
28
DIM
24
13
1.260
(32,04) (36,20)
1.425
A MAX
1.230
(31,24) (35,18)
1.385
A MIN
B MAX
B MIN
0.280 (7,11)
0.250 (6,35)
0.310
(7,87)
0.315
(8,00)
1
12
0.290
(7,37)
0.295
(7,49)
0.070 (1,78) MAX
B
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0°–15°
0.021 (0,53)
0.015 (0,38)
M
0.010 (0,25) NOM
4040050/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI006B – SEPTEMBER 2001 – REVISED APRIL 2002
N (R–PDIP–T24)
PLASTIC DUAL–IN–LINE
1.222 (31,04) MAX
24
13
0.360 (9,14) MAX
1
12
0.070 (1,78) MAX
0.200 (5,08) MAX
0.020 (0,51) MIN
0.425 (10,80) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0’–15’
0.021 (0,53)
0.015 (0,38)
0.010 (0,25) NOM
4040051–3/D 09/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS–010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI008 – OCTOBER 1994
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PIN SHOWN
A
24
13
0.560 (14,22)
0.520 (13,21)
1
12
0.060 (1,52) TYP
0.200 (5,08) MAX
0.020 (0,51) MIN
0.610 (15,49)
0.590 (14,99)
Seating Plane
0.100 (2,54)
0.125 (3,18) MIN
0.010 (0,25) NOM
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
PINS **
M
24
28
32
40
48
52
DIM
1.270
1.450
1.650
2.090
2.450
2.650
A MAX
(32,26) (36,83) (41,91) (53,09) (62,23) (67,31)
1.230
1.410
1.610
2.040
2.390
2.590
A MIN
(31,24) (35,81) (40,89) (51,82) (60,71) (65,79)
4040053/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-011
D. Falls within JEDEC MS-015 (32 pin only)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
相关型号：
CD74HCT4514EE4
High Speed CMOS Logic 4-to-16 Line Decoder/Demultiplexer with Input Latches 24-PDIP -55 to 125
TI
©2020 ICPDF网 联系我们和版权申明