CDC209-7 [TI]
DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS;
| 型号： | CDC209-7 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS 驱动 输出元件 |
| 文件： | 总11页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC209, CDC209–7
DUAL 1-LINE TO 4-LINE CLOCK DRIVERS
WITH 3-STATE OUTPUTS
SCAS108D – MARCH 1990 – REVISED MAY 1997
DW OR N PACKAGE
(TOP VIEW)
CDC209 Replaces 74AC11208
CDC209-7 Replaces 74AC11208-7
Low-Skew Propagation Delay
Specifications for Clock-Driver
Applications
1Y2
1Y3
1Y4
GND
GND
GND
GND
2Y1
1Y1
1A
1OE1
1OE2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CMOS-Compatible Inputs and Outputs
V
Flow-Through Architecture Optimizes
PCB Layout
CC
V
CC
2A
Characterized for Operation at 5-V and
2OE1
2OE2
2Y4
3.3-V V
CC
2Y2
2Y3
Center-Pin V
and GND Pin
CC
Configurations Minimize High-Speed
Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic
Small-Outline Package (DW) and Standard
Plastic 300-mil DIPs (N)
description
The CDC209/209-7 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum
skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1 and OE2) inputs for
each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level
independent of the signal on the respective A input.
Skew parameters are specified for a reduced temperature and voltage range common to many applications.
The CDC209/209-7 is characterized for operation fromT = –40°C to 85°C.
A
FUNCTION TABLES
INPUTS
OUTPUTS
1OE1 1OE2
1A
L
1Y1
L
1Y2
L
1Y3
L
1Y4
L
L
L
L
L
H
X
H
H
H
H
L
H
L
L
L
L
L
H
H
X
H
H
H
H
H
X
Z
Z
Z
Z
INPUTS
OUTPUTS
2OE1 2OE2
2A
L
2Y1
L
2Y2
L
2Y3
L
2Y4
L
L
L
L
L
H
X
H
H
H
H
L
H
L
L
L
L
L
H
H
X
H
H
H
H
H
X
Z
Z
Z
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC209, CDC209–7
DUAL 1-LINE TO 4-LINE CLOCK DRIVERS
WITH 3-STATE OUTPUTS
SCAS108D – MARCH 1990 – REVISED MAY 1997
†
logic symbol
X/Y
1
18
17
1
2
3
V4
1
2
1OE1
1OE2
G5
EN
20
1
4, 5
1Y1
1Y2
1Y3
1Y4
4, 5
4, 5
4, 5
19
2
1A
3
13
12
8
9
2Y1
2Y2
2Y3
2Y4
2OE1
2OE2
10
11
14
2A
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
18
1OE1
20
1
1Y1
1Y2
17
1OE2
2
3
1Y3
1Y4
19
1A
13
2OE1
8
9
2Y1
2Y2
12
2OE2
10
11
2Y3
2Y4
14
2A
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC209, CDC209–7
DUAL 1-LINE TO 4-LINE CLOCK DRIVERS
WITH 3-STATE OUTPUTS
SCAS108D – MARCH 1990 – REVISED MAY 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DW package . . . . . . . . . . . . . . . . . . 1.6 W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
A
N package . . . . . . . . . . . . . . . . . . . . 1.3 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations
application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage
3
2.1
5
5.5
V
CC
IH
V
V
V
V
V
V
= 3 V
CC
CC
CC
CC
CC
CC
V
High-level input voltage
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
V
0.9
1.35
1.65
V
V
Low-level input voltage
Input voltage
= 4.5 V
= 5.5 V
V
V
IL
0
V
I
CC
–4
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
I
High-level output current
= 4.5 V
= 5.5 V
= 3 V
–24
–24
12
mA
OH
I
Low-level output current
= 4.5 V
= 5.5 V
24
mA
OL
24
∆t/∆v
Input transition rise or fall rate
Input clock frequency
0
10
ns/V
MHz
°C
f
60
clock
T
A
Operating free-air temperature
–40
85
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC209, CDC209–7
DUAL 1-LINE TO 4-LINE CLOCK DRIVERS
WITH 3-STATE OUTPUTS
SCAS108D – MARCH 1990 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
T
MIN
2.9
TYP
MAX
UNIT
A†
25°C
Full range
25°C
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
2.9
4.4
I
= –50 µA
= 4.5 V
= 5.5 V
= 3 V
OH
OH
Full range
25°C
4.4
5.4
Full range
25°C
5.4
V
OH
High-level output voltage
2.58
2.48
3.94
3.8
V
I
= –4 mA
Full range
25°C
= 4.5 V
Full range
25°C
I
I
= –24 mA
OH
4.94
4.8
V
CC
V
CC
V
CC
= 5.5 V
= 5.5 V
= 3 V
Full range
Full range
25°C
‡
= –75 mA ,
3.85
OH
0.1
0.1
Full range
25°C
0.1
I
= 50 µA
V
CC
V
CC
V
CC
V
CC
= 4.5 V
= 5.5 V
= 3 V
OL
OL
Full range
25°C
0.1
0.1
Full range
25°C
0.1
V
OL
Low-level output voltage
0.36
0.44
0.36
0.44
0.36
0.44
1.65
±0.1
±1
V
I
= 12 mA
= 24 mA
Full range
25°C
= 4.5 V
Full range
25°C
I
I
OL
V
CC
V
CC
V
CC
= 5.5 V
= 5.5 V
= 5.5 V
Full range
Full range
25°C
‡
= 75 mA ,
OL
I
I
I
Input current
V = V
or GND
µA
µA
µA
I
I
CC
Full range
25°C
±0.5
±5
High-impedance output current
Supply current
V
= V
or GND
V
= 5.5 V
= 5.5 V
OZ
CC
O
CC
CC
CC
Full range
25°C
8
V = V
or GND,
I
CC
V
I
O
= 0
Full range
25°C
80
C
C
Input capacitance
Output capacitance
V = V
or GND
V
V
= 5 V
= 5 V
4
pF
pF
i
I
CC
CC
V
= V or GND
CC
25°C
10
o
O
CC
†
‡
Full range is T = –40°C to 85°C.
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC209, CDC209–7
DUAL 1-LINE TO 4-LINE CLOCK DRIVERS
WITH 3-STATE OUTPUTS
SCAS108D – MARCH 1990 – REVISED MAY 1997
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
T
A†
MIN
TYP
MAX
UNIT
25°C
Full range
25°C
4.8
4.8
5.1
5.1
5.2
5.2
7.8
7.8
5.1
5.1
6.8
6.8
3.4
3.4
4.1
4.1
11.1
13.1
14.6
14.3
15.6
14.2
15.8
15.7
17.4
14.2
15.7
19.5
22.8
8.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
Propagation delay time, low-to-high level
1A and 2A
1A and 2A
Any Y
Any Y
Any Y
Any Y
Any Y
Any Y
Any Y
Any Y
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
12.2
11.9
13.3
11.8
16.3
6.9
Propagation delay time, high-to-low level
Propagation delay time, low-to-high level
Propagation delay time, high-to-low level
Enable time to the high level
Full range
25°C
1OE1, 1OE2, and
2OE1, 2OE2
Full range
25°C
1OE1, 1OE2, and
2OE1, 2OE2
Full range
25°C
1OE2 or 2OE2
1OE1 or 2OE1
1OE2 or 2OE2
1OE1 or 2OE1
Full range
25°C
Enable time to the low level
Full range
25°C
Disable time from the high level
Disable time from the low level
Full range
25°C
9.2
7.5
9.4
Full range
10.2
†
Full range is T = –40°C to 85°C.
A
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
T
A†
MIN
TYP
MAX
UNIT
25°C
Full range
25°C
4.2
4.2
4.2
4.2
4.6
4.6
4.8
4.8
4.3
4.3
5.3
5.3
3
5.5
9
9.9
9.3
10.1
9.6
10.7
10.2
11
t
t
t
t
t
t
t
t
Propagation delay time, low-to-high level
1A and 2A
1A and 2A
Any Y
ns
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
7
7.3
7.7
7.2
9
Propagation delay time, high-to-low level
Propagation delay time, low-to-high level
Propagation delay time, high-to-low level
Enable time to the high level
Any Y
Any Y
Any Y
Any Y
Any Y
Any Y
Any Y
ns
ns
ns
ns
ns
ns
ns
Full range
25°C
1OE1, 1OE2, and
2OE1, 2OE2
Full range
25°C
1OE1, 1OE2, and
2OE1, 2OE2
Full range
25°C
9.4
4
1OE2 or 2OE2
1OE1 or 2OE1
1OE2 or 2OE2
1OE1 or 2OE1
Full range
25°C
12.2
13.5
7.5
8
Enable time to the low level
Full range
25°C
5.4
5.7
Disable time from the high level
Disable time from the low level
Full range
25°C
3
3.7
3.7
7.5
8.2
Full range
†
Full range is T = –40°C to 85°C.
A
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC209, CDC209–7
DUAL 1-LINE TO 4-LINE CLOCK DRIVERS
WITH 3-STATE OUTPUTS
SCAS108D – MARCH 1990 – REVISED MAY 1997
switching characteristics, V
= 5 V ± 0.25 V, T = 25°C to 70°C (see Note 3 and Figures 1 and 2)
A
CC
CDC209
CDC209-7
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
6
MAX
MIN
6
MAX
t
t
t
Propagation delay time, low-to-high level
8.5
9.3
1
8.5
9.3
0.7
PLH
PHL
sk(o)
1A and 2A
1A and 2A
Any Y
Any Y
ns
ns
Propagation delay time, high-to-low level
output skew time
6
6
NOTE 3: All specifications are valid only for all outputs switching simultaneously and in phase.
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
MIN
TYP
95
MAX
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per bank
C
pF
pd
10
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
TEST
S1
Open
2 × V
S1
t
t
t
/t
500 Ω
PLH PHL
From Output
Under Test
/t
PLZ PZL
CC
GND
/t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
V
CC
Output
Control
(low-level
enabling)
LOAD CIRCUIT FOR OUTPUTS
50%
50%
0 V
t
PZL
t
PLZ
≈ V
V
CC
CC
Input
(see Note B)
Output
Waveform 1
50%
50%
50% V
CC
20% V
CC
0 V
S1 at 2 × V
(see Note C)
CC
V
OL
OH
t
PLH
t
PHZ
t
PHL
t
PZH
Output
Waveform 2
S1 at GND
V
V
OH
80% V
CC
Output
50% V
50% V
50% V
CC
CC
V
CC
(see Note C)
OL
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
For testing pulse duration: t = t = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low.
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC209, CDC209–7
DUAL 1-LINE TO 4-LINE CLOCK DRIVERS
WITH 3-STATE OUTPUTS
SCAS108D – MARCH 1990 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
1A, 2A
1Y1
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PLH1
PLH2
PLH3
PLH4
PLH5
PLH6
PLH7
PLH8
PHL1
PHL2
PHL3
PHL4
PHL5
PHL6
PHL7
PHL8
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
NOTE D: Output skew, t
sk(o)
, is calculated as the greater of:
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
(n = 1, 2, . . . , 8)
(n = 1, 2, . . . , 8)
PLHn
PHLn
Figure 2. Waveforms for Calculation of t
sk(o)
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC209, CDC209–7
DUAL 1-LINE TO 4-LINE CLOCK DRIVERS
WITH 3-STATE OUTPUTS
SCAS108D – MARCH 1990 – REVISED MAY 1997
MECHANICAL INFORMATION
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
PINS **
0.050 (1,27)
16
20
24
28
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
0.410
0.510
0.610
0.710
A MAX
(10,41) (12,95) (15,49) (18,03)
16
9
0.400
0.500
0.600
0.700
A MIN
(10,16) (12,70) (15,24) (17,78)
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°–8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
4040000/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC209, CDC209–7
DUAL 1-LINE TO 4-LINE CLOCK DRIVERS
WITH 3-STATE OUTPUTS
SCAS108D – MARCH 1990 – REVISED MAY 1997
MECHANICAL INFORMATION
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
PINS **
14
16
18
20
DIM
0.775
(19,69)
0.775
(19,69)
0.920
(23.37)
0.975
(24,77)
A MAX
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21.59)
0.940
(23,88)
A MIN
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.020 (0,51) MIN
0.310 (7,87)
0.290 (7,37)
0.035 (0,89) MAX
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
16-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
SOIC
SSOP
SOIC
SOIC
PDIP
Drawing
DW
DW
DB
CDC209-7DW
CDC209-7DWR
CDC209DBLE
CDC209DW
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
20
20
20
20
20
20
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
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DW
DW
N
CDC209DWR
CDC209N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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