CDC2351-EP [TI]
1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS; 1线路至10线路时钟驱动器，具有三态输出
| 型号： | CDC2351-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS |
| 文件： | 总10页 (文件大小：451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢀꢂ ꢃꢄ ꢅꢆ ꢇꢈ
ꢅ ꢆꢉ ꢊꢋꢇ ꢌ ꢍ ꢅ ꢎ ꢆꢉ ꢊꢋꢇ ꢀꢉ ꢍ ꢀꢏ ꢁ ꢐꢊ ꢑ ꢇꢐ
ꢒ ꢊꢌ ꢓ ꢃ ꢆꢔꢌꢕꢌ ꢇ ꢍ ꢖꢌ ꢈ ꢖꢌꢔ
SGLS248A − JUNE 2004 − REVISED AUGUST 2004
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
Outputs Have Internal Series Damping
Resistor to Reduce Transmission Line
Effects
D
D
D
D
D
Extended Temperature Performance of
−55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
D
D
D
Distributed V
Switching Noise
and Ground Pins Reduce
CC
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
Enhanced Product-Change Notification
Shrink Small-Outline (DB) Package
†
Qualification Pedigree
DB PACKAGE
(TOP VIEW)
Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
Applications
GND
Y10
GND
23 Y1
1
24
D
D
D
Operates at 3.3-V V
CC
LVTTL-Compatible Inputs and Outputs
2
V
3
22
21
20
19
18
17
16
15
14
13
V
Y2
GND
Y3
Y4
GND
Y5
V
Y6
GND
CC
CC
4
Y9
OE
A
P0
P1
Y8
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
5
6
3.3-V V
)
CC
7
D
Distributes One Clock Input to 10 Outputs
8
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
9
10
11
12
V
CC
Y7
CC
GND
description
The CDC2351 is a high-performance clock-driver circuit that distributes one input (A) to 10 outputs (Y) with
minimum skew for clock distribution. The output-enable (OE) input disables the outputs to a high-impedance
state. Each output has an internal series damping resistor to improve signal integrity at the load. The CDC2351
operates at nominal 3.3-V V
.
CC
The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure
that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended
for customer use and should be connected to GND.
The CDC2351M is characterized for operation over the full military temperature range of −55°C to 125°C.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
−55°C to 125°C
SSOP − DB Tape and Reel
CDC2351MDBREP
CK2351MEP
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙΒ is a trademark of Texas Instruments.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀꢂ ꢃ ꢄ ꢅ ꢆꢇꢈ
ꢅꢆ ꢉ ꢊ ꢋꢇ ꢌꢍ ꢅ ꢎꢆ ꢉ ꢊꢋ ꢇ ꢀꢉ ꢍꢀ ꢏ ꢁꢐ ꢊ ꢑꢇ ꢐ
ꢒꢊ ꢌ ꢓ ꢃ ꢆꢔꢌꢕꢌ ꢇ ꢍꢖꢌ ꢈ ꢖꢌꢔ
SGLS248A − JUNE 2004 − REVISED AUGUST 2004
FUNCTION TABLE
INPUTS
OUTPUTS
In
Z
A
L
OE
H
H
L
H
Z
L
L
H
L
H
logic diagram (positive logic)
5
OE
23
21
19
Y1
Y2
Y3
18
16
Y4
Y5
6
A
7
8
P0 P1
14
11
Y6
Y7
9
4
Y8
Y9
2
Y10
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢒ ꢊꢌ ꢓ ꢃ ꢆꢔꢌꢕꢌ ꢇ ꢍ ꢖꢌ ꢈꢖ ꢌꢔ
SGLS248A − JUNE 2004 − REVISED AUGUST 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state,
V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
O
Current into any output in the low state, I
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
Output clamp current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 mA
O
IK
OK
I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . 0.65 W
A
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, see the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002.
recommended operating conditions (see Note 3)
MIN
3
MAX
UNIT
V
V
V
V
V
Supply voltage
3.6
CC
High-level input voltage
Low-level input voltage
Input voltage
2
V
IH
0.8
5.5
V
IL
0
V
I
I
I
f
High-level output current
Low-level output current
Input clock frequency
Operating free-air temperature
−12
12
mA
mA
MHz
°C
OH
OL
clock
100
125
T
CDC2351M
−55
A
NOTE 3: Unused pins (input or I/O) must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V,
I = −18 mA
−1.2
IK
I
= 3 V,
I
I
= − 12 mA
= 12 mA
2
V
OH
OL
OH
OL
= 3 V,
0.8
1
V
I
I
I
= 3.6 V,
= 3.6 V,
= 3.6 V,
V = V
or GND
= 2.5 V
µA
mA
µA
I
I
CC
‡
V
−7
−70
10
O
O
V
= 3 V or 0
OZ
CC
Outputs high
Outputs low
0.3
15
I
V
= 3.6 V,
I
= 0,
V = V
or GND
mA
CC
CC
O
I
CC
Outputs disabled
f = 10 MHz
0.3
C
C
V = V
CC
or GND,
or GND,
V
V
= 3.3 V,
= 3.3 V,
4
6
pF
pF
i
I
CC
V = V
O CC
f = 10 MHz
o
CC
‡
Not more than one output should be tested at a time and the duration of the test should not exceed one second.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀꢂ ꢃ ꢄ ꢅ ꢆꢇꢈ
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ꢒꢊ ꢌ ꢓ ꢃ ꢆꢔꢌꢕꢌ ꢇ ꢍꢖꢌ ꢈ ꢖꢌꢔ
SGLS248A − JUNE 2004 − REVISED AUGUST 2004
switching characteristics, C = 50 pF (see Figure 1 and Figure 2)
L
V
T
= 3.3 V,
= 25°C
V
= 3 V to 3.6 V,
CC
A
CC
T = −55°C to 125°C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
3.8
3.6
2.4
2.4
2.2
2.2
TYP
4.3
4.1
4.9
4.3
4.4
4.6
0.3
MAX
4.8
4.6
6
MIN
1.1
MAX
11
t
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(o)
A
Y
Y
ns
ns
1
1
1
1
1
9.7
12
OE
6
11.1
11.1
11.5
2.5
6.3
6.3
0.5
Y
Y
ns
ns
OE
A
t
A
A
A
A
Y
Y
Y
Y
0.2
0.8
1
3
ns
ns
ns
ns
sk(p)
t
t
t
sk(pr)
2.5
2.5
r
f
switching characteristics temperature and V
coefficients over recommended operating free-air
CC
temperature and V
range (see Note 4)
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
†
∝t
∝t
(T)
(T)
Average temperature coefficient of low-to-high propagation delay
Average temperature coefficient of high-to-low propagation delay
A
A
Y
Y
85
ps/10°C
ps/10°C
PLH
†
50
PHL
ps/
100 mV
‡
∝t
(V
)
)
Average V
coefficient of low-to-high propagation delay
coefficient of high-to-low propagation delay
Y
Y
−145
A
A
PLH CC
CC
CC
ps/
100 mV
‡
∝t
(V
Average V
−100
PHL CC
†
‡
∝t
∝t
(T) and ∝t
(T) are virtually independent of V .
CC
PLH
PHL
(V ) and ∝t
(V ) are virtually independent of temperature.
PLH CC PHL CC
NOTE 4: This data was extracted from characterization material and has not been tested at the factory.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢒ ꢊꢌ ꢓ ꢃ ꢆꢔꢌꢕꢌ ꢇ ꢍ ꢖꢌ ꢈꢖ ꢌꢔ
SGLS248A − JUNE 2004 − REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
6 V
TEST
t /t
PLH PHL
S1
Open
6 V
S1
500 Ω
Open
GND
From Output
Under Test
t
/t
PLZ PZL
/t
t
GND
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
1.5 V
3 V
0 V
Input
1.5 V
1.5 V
3 V
Timing Input
0 V
VOLTAGE WAVEFORMS
t
t
h
su
3 V
0 V
Data Input
1.5 V
1.5 V
3 V
0 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
t
PZL
3 V
0 V
t
PLZ
Input
1.5 V
1.5 V
3 V
Output
Waveform 1
S1 at 6 V
1.5 V
t
PLH
V
V
+ 0.3 V
− 0.3 V
OL
t
PHL
V
OL
OH
(see Note B)
t
V
V
PHZ
OH
2 V
0.8 V
2 V
t
PZH
Output
1.5 V
Output
Waveform 2
S1 at GND
0.8 V
V
OL
OH
1.5 V
t
t
f
r
(see Note B)
≈ 0 V
VOLTAGE WAVEFORMS
C includes probe and jig capacitance.
L
VOLTAGE WAVEFORMS
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢒꢊ ꢌ ꢓ ꢃ ꢆꢔꢌꢕꢌ ꢇ ꢍꢖꢌ ꢈ ꢖꢌꢔ
SGLS248A − JUNE 2004 − REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
A
Y1
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PHL1
PHL2
PHL3
PHL4
PHL5
PHL6
PHL7
PHL8
PHL9
PLH1
PLH2
PLH3
PLH4
PLH5
PLH6
PLH7
PLH8
PLH9
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
t
t
PLH10
PHL10
NOTES: A. Output skew, t , is calculated as the greater of:
sk(o)
− The difference between the fastest and slowest of t
− The difference between the fastest and slowest of t
(n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10)
(n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10)
PLHn
PHLn
B. Pulse skew, t
C. Process skew, t
, is calculated as the greater of | t
− t
| (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10).
sk(p)
PLHn PHLn
, is calculated as the greater of:
sk(pr)
− The difference between the fastest and slowest of t
operating conditions.
(n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) across multiple devices under identical
(n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) across multiple devices under identical
PLHn
− The difference between the fastest and slowest of t
operating conditions.
PHLn
Figure 2. Waveforms for Calculation of t
, t
, t
sk(o) sk(p) sk(pr)
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
22-Sep-2008
PACKAGING INFORMATION
Orderable Device
CDC2351MDBREP
CDC2351MDBREPG4
V62/04757-01XE
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
24
24
24
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP
SSOP
DB
DB
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CDC2351-EP :
Catalog: CDC2351
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDC2351MDBREP
SSOP
DB
24
2000
330.0
16.4
8.2
8.8
2.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DB 24
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
CDC2351MDBREP
2000
Pack Materials-Page 2
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