CDC2509C [TI]
3.3-V PHASE-LOCK LOOP CLOCK DRIVER; 3.3 -V锁相环时钟驱动器
| 型号： | CDC2509C |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V PHASE-LOCK LOOP CLOCK DRIVER |
| 文件： | 总12页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC2509C
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS620 – DECEMBER 1998
PW PACKAGE
(TOP VIEW)
Designed to Meet PC SDRAM Registered
DIMM Design Support Document Rev. 1.2
Spread Spectrum Clock Compatible
AGND
CLK
AV
1
24
23
22
21
20
19
18
17
16
15
14
13
Operating Frequency 25 MHz to 125 MHz
V
2
CC
CC
Static tPhase Error Distribution at 66MHz to
100 MHz is ±150 ps
1Y0
1Y1
1Y2
GND
GND
1Y3
V
3
CC
2Y0
2Y1
GND
GND
2Y2
2Y3
4
5
Drop-In Replacement for TI CDC2509A With
Enhanced Performance
6
7
Jitter (cyc – cyc) at 66 MHz to 100 MHz is
|100 ps|
8
1Y4
9
Available in Plastic 24-Pin TSSOP
V
10
11
12
V
CC
CC
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
1G
FBOUT
2G
FBIN
Distributes One Clock Input to One Bank of
Five and One Bank of Four Outputs
Separate Output Enable for Each Output
Bank
External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input
On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3 V
description
The CDC2509C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDC2509C operates at 3.3 V V . It also
CC
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output
signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled
or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in
phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2509C does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2509C requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AV
to ground.
CC
The CDC2509C is characterized for operation from 0°C to 85°C.
For application information refer to application reports High Speed Distribution Design Techniques for
CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread
Spectrum Clocking (SSC) (literature number SCAA039).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2509C
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS620 – DECEMBER 1998
FUNCTION TABLE
INPUTS
2G
OUTPUTS
2Y
1Y
(0:4)
1G
CLK
FBOUT
(0:3)
X
L
X
L
L
L
L
L
L
H
H
H
H
L
H
H
H
H
L
H
L
L
H
H
H
H
H
L
H
H
functional block diagram
11
1G
3
4
5
8
9
1Y0
1Y1
1Y2
1Y3
1Y4
14
2G
21
20
2Y0
2Y1
17
16
24
2Y2
CLK
PLL
13
2Y3
FBIN
12
FBOUT
23
AV
CC
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
(PW)
0°C to 85°C
CDC2509CPWR
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2509C
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS620 – DECEMBER 1998
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME
NO.
Clock input. CLK provides the clock signal to be distributed by the CDC2509C clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.
CLK
24
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally
zero phase error between CLK and FBIN.
FBIN
1G
13
I
I
Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4) are
disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same
frequency as CLK.
11
Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are
disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same
frequency as CLK.
2G
14
12
I
Feedbackoutput. FBOUTisdedicatedforexternalfeedback. ItswitchesatthesamefrequencyasCLK.
When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an
integrated 25-Ω series-damping resistor.
FBOUT
1Y (0:4)
2Y (0:3)
O
O
O
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via the
1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input. Each
output has an integrated 25-Ω series-damping resistor.
3, 4, 5, 8, 9
21, 20, 17, 16
23
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via the
2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input. Each
output has an integrated 25-Ω series-damping resistor.
Analogpowersupply.AV
CC
providesthepowerreferencefortheanalogcircuitry.Inaddition,AV
can
is strapped to ground, PLL is bypassed and
CC
AV
CC
Power be used to bypass the PLL for test purposes. When AV
CLK is buffered directly to the device outputs.
CC
AGND
1
Ground Analog ground. AGND provides the ground reference for the analog circuitry.
V
CC
GND
2, 10, 15, 22
6, 7, 18, 19
Power Power supply
Ground Ground
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2509C
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS620 – DECEMBER 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, AV
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
< V
+0.7 V
CC
CC
CC
Supply voltage range, V
CC
Input voltage range, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
I
Voltage range applied to any output in the high or low state,
V
(see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, I
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V
Maximum power dissipation at T = 55°C (in still air) (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, T
IK
OK
I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
O O CC
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. AV
must not exceed V
.
CC
CC
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 4.6 V maximum.
4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation, refertothePackageThermalConsiderationsapplicationnoteintheABTAdvancedBiCMOSTechnologyData
Book, literature number SCBD002.
recommended operating conditions (see Note 5)
MIN
3
MAX
UNIT
V
V
V
V
V
, AV
CC
Supply voltage
3.6
CC
High-level input voltage
Low-level input voltage
Input voltage
2
V
IH
0.8
V
IL
0
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Operating free-air temperature
–12
12
mA
mA
°C
OH
OL
T
A
85
NOTE 5: Unused inputs must be held high or low to prevent them from floating.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
25
MAX
125
60%
1
UNIT
f
Clock frequency
MHz
clk
Input clock duty cycle
40%
†
Stabilization time
ms
†
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phasereferencesignalmustbepresentatCLK. Untilphaselockisobtained, thespecificationsforpropagationdelay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2509C
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS620 – DECEMBER 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
TYP
PARAMETER
TEST CONDITIONS
V
CC
, AV
CC
MIN
MAX
UNIT
V
IK
Input clamp voltage
I = –18 mA
I
3 V
–1.2
V
I
I
I
I
I
I
= –100 µA
= –12 mA
= –6 mA
= 100 µA
= 12 mA
= 6 mA
MIN to MAX
3 V
V
CC
–0.2
OH
OH
OH
OL
OL
OL
V
High-level output voltage
Low-level output voltage
High-level output current
Low-level output current
2.1
2.4
V
V
OH
3 V
MIN to MAX
3 V
0.2
0.8
V
OL
3 V
0.55
V
V
V
V
V
V
= 1 V
3.135 V
3.3 V
–32
34
O
O
O
O
O
O
I
= 1.65 V
= 3.135 V
= 1.95 V
= 1.65 V
= 0.4 V
–36
40
mA
mA
OH
3.465 V
3.135 V
3.3 V
–12
I
OL
3.465 V
3.6 V
14
I
I
Input current
V = V
or GND
±5
µA
µA
I
I
CC
CC
V = V
Outputs: low or high
or GND,
I
O
= 0,
I
§
Supply current
3.6 V
10
CC
One input at V – 0.6 V,
CC
Other inputs at V
∆I
Change in supply current
3.3 V to 3.6 V
500
µA
CC
or GND
CC
or GND
C
C
Input capacitance
Output capacitance
V = V
3.3 V
3.3 V
4
6
pF
pF
i
I
CC
= V or GND
CC
V
O
o
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
For I of AV , and I vs Frequency (see Figures 11 and 12).
CC
CC
CC
switching characteristics over recommended ranges of supply voltage and operating free-air
‡
temperature, C = 30 pF (see Note 6 and Figures 1 and 2)
L
V
, AV
± 0.165 V
= 3.3 V
CC
CC
FROM
(INPUT)/CONDITION
TO
(OUTPUT)
PARAMETER
UNIT
MIN
TYP
MAX
Phase error time – static (normalized)
CLKIN↑ = 66 MHz to100 MHz
(See Figures 3 – 8)
FBIN↑
–150
150
ps
ps
§
t
Output skew time
Phase error time – jitter (see Note 7)
Jitter
Any Y or FBOUT
Clkin = 66 MHz to 100 MHz
F(clkin > 60 MHz)
Any Y or FBOUT
Any Y or FBOUT
200
50
sk(o)
–50
ps
(cycle-cycle)
(See Figures 9 and 10)
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
|100|
55%
1
Duty cycle
45%
2.5
V
= 1.2 V to 1.8 V,
IBIS simulation
O
t
t
Rise time (See Notes 8 and 9)
Fall time (See Notes 8 and 9)
V/ns
V/ns
r
V
O
= 1.2 V to 1.8 V,
IBIS simulation
Any Y or FBOUT
2.5
1
f
‡
These parameters are not production tested.
§
The t
specification is only valid for equal loading of all outputs.
sk(o)
NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
7. Calculated per PC DRAM SPEC (t , static – jitter ).
phase error
(cycle-to-cycle)
8. This is equivalent to 0.8 ns/2.5 ns and 0.8 ns/2.7 ns into standard 500 Ω/ 30 pf load for output swing of 04. V to 2 V.
9. 64 MB DIMM configuration according to PC SDRAM Registered DIMM Design Support Document, Figure 20 and Table 13.
Intel is a trademark of Intel Corporation.
PC SDRAM Register DIMM Design Support Document is published by Intel Corporation.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2509C
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS620 – DECEMBER 1998
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
Input
50% V
CC
t
pd
From Output
Under Test
V
V
OH
2 V
0.4 V
2 V
Output
500
50% V
CC
0.4 V
30 pF
OL
t
r
t
f
LOAD CIRCUIT FOR OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, Z = 50 Ω, t ≤ 1.2 ns, t ≤ 1.2 ns.
O
r
f
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
CLKIN
FBIN
t
phase error
FBOUT
Any Y
t
sk(o)
Any Y
Any Y
t
sk(o)
Figure 2. Phase Error and Skew Calculations
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2509C
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS620 – DECEMBER 1998
TYPICAL CHARACTERISTICS
CDC2509C
PHASE ADJUSTMENT SLOPE AND PHASE ERROR
vs
LOAD CAPACITANCE
20
10
200
V
= 3.3 V
CC
= 100 MHz
f
C
c
= 30pF
(LY)
= 25°C
100
T
A
See Notes A and B
0
0
Phase Error
–10
–100
–20
–200
–30
–40
–300
–400
Phase Adjustment Slope
45 50
0
5
10 15 20 25 30 35 40
C
– Lumped Feedback Capacitance at FBIN – pF
(LF)
Figure 3
CDC2509A
PHASE ADJUSTMENT SLOPE AND PHASE ERROR
vs
LOAD CAPACITANCE
10
0
100
V
= 3.3 V
CC
= 100 MHz
f
C
c
= 30pF
(LY)
= 25°C
0
T
A
See Notes A and B
–10
–20
–100
–200
Phase Error
–30
–300
–40
–50
–400
–500
Phase
Adjustment Slope
45 50
0
5
10 15 20 25 30 35 40
C
– Lumped Feedback Capacitance at FBIN – pF
(LF)
Figure 4
NOTES: A. Trace feedback length FBOUT to FBIN = 5 mm, Z = 50 Ω Phase error measured from CLK to Y
O
B. CLF = Lumped feedback capacitance at FBIN
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2509C
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS620 – DECEMBER 1998
TYPICAL CHARACTERISTICS
PHASE ERROR
vs
CLOCK FREQUENCY
PHASE ERROR
vs
SUPPLY VOLTAGE
0
–50
0
–50
V
= 3.3 V
f
= 100 MHz
CC
c
C
C
T
= 30 pF
= 0
C
C
T
= 30 pF
= 0
= 25°C
(LY)
(LF)
(LY)
(LF)
–100
–100
= 25°C
A
A
See Note A
See Note A
–150
–200
–250
–150
–200
–250
–300
–350
–400
–300
–350
–400
–450
–500
–450
–500
20
40
60
80
100
120
140
160
3.1
3.2
V
3.3
3.4
3.5
f
c
– Clock Frequency – MHz
– Supply Voltage – V
Figure 6
CC
Figure 5
CDC2509C
STATIC PHASE ERROR
vs
CDC2509A
STATIC PHASE ERROR
vs
CLOCK FREQUENCY
CLOCK FREQUENCY
–200
–300
–200
–300
V
C
= 3.3 V
CC
V
C
= 3.3 V
CC
= C
= 30 pF
(LF)
(LY)
= 25°C
= C
= 30 pF
(LF)
(LY)
See Notes B to D
T
A
See Notes B to D
–400
–500
–400
–500
–600
–700
–600
–700
35 45
55
65
75
85 95 105 115 125
35 45
55
65
75
85 95 105 115 125
f
c
– Clock Frequency – MHz
f
c
– Clock Frequency – MHz
Figure 7
Figure 8
NOTES: A. Trace feedback length FBOUT to FBIN = 5 mm, Z = 50 Ω
O
B. Phase error measured from CLK to FBIN
C. CLY = Lumped capacitive load at Y
D. CLF = Lumped feedback capacitance at FBIN
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2509C
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS620 – DECEMBER 1998
TYPICAL CHARACTERISTICS
CDC2509C
JITTER
CDC2509A
JITTER
vs
vs
CLOCK FREQUENCY
CLOCK FREQUENCY
400
350
300
250
700
600
500
V
= 3.3 V
CC
V
C
= 3.3 V
CC
C
T
= C
= 30 pF
(LF)
(LY)
= 25°C
= C
= 30 pF
(LF)
(LY)
= 25°C
A
T
A
See Notes A and B
See Notes A and B
400
300
200
150
Peak to Peak
Peak to Peak
200
100
Cycle to Cycle
Cycle to Cycle
100
0
50
0
35 45
55
65 75
85 95 105 115 125
35 45
55
65 75
85 95 105 115 125
f
c
– Clock Frequency – MHz
f
c
– Clock Frequency – MHz
Figure 9
Figure 10
ANALOG SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
CLOCK FREQUENCY
CLOCK FREQUENCY
16
300
AV
CC
= V
Bias = 0/3 V
= 3.465 V
CC
AV
CC
= V
= 3.465 V
CC
Bias = 0/3 V
14
12
C
C
T
= 30 pf
= 0
C
C
T
= 30 pf
= 0
250
200
150
100
(LY)
(LF)
A
(LY)
(LF)
A
= 25°C
= 25°C
See Notes A and B
See Notes A and B
10
8
6
4
2
0
50
0
10
30
50
70
90
110
130
150
10
30
50
70
90
110
130
150
f
c
– Clock Frequency – MHz
f
c
– Clock Frequency – MHz
Figure 11
Figure 12
NOTES: A.
B.
C
(LY)
C
(LF)
= Lumped capacitive load at Y
= Lumped feedback capacitance at FBIN
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2509C
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS620 – DECEMBER 1998
TYPICAL CHARACTERISTICS
TI SILICON-BASED
PLL PULLDOWN IBIS I/V
TI SILICON-BASED
PLL PULLUP IBIS I/V
120
100
0
V
= 3.135 V
CC
V
= 3.465 V
CC
High IDS
Low IDS
= 85°C
T
A
T
A
= 0°C
–20
I
(Intel)
I
(Intel)
min
max
80
60
40
V
= 3.3 V
CC
Nom IDS
–40
–60
V
= 3.3 V
T
A
= 25°C
CC
Nom IDS
= 25°C
T
A
V
= 3.465 V
CC
High IDS
= 0°C
V
= 3.135 V
CC
Low IDS
= 85°C
–80
T
A
20
0
T
A
I
(Intel)
2
I
(Intel)
min
max
–100
0
0.5
1
1.5
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
V
O
– Output Voltage – V
V
O
– Output Voltage – V
Figure 13
Figure 14
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2509C
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS620 – DECEMBER 1998
MECHANICAL INFORMATION
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,30
0,19
0,65
M
0,10
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
0,75
A
0,50
Seating Plane
0,10
1,20 MAX
0,05 MIN
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/E 08/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
11
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