CDC2510APW [ETC]
TEN DISTRIBUTED-OUTPUT CLOCK DRIVER|TSSOP|24PIN|PLASTIC ; 10个分发输出时钟驱动器| TSSOP封装| 24PIN |塑料\n
| 型号： | CDC2510APW |
| 厂家： | 
ETC |
| 描述： | TEN DISTRIBUTED-OUTPUT CLOCK DRIVER|TSSOP|24PIN|PLASTIC
|
| 文件： | 总9页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC2510A
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS604B– APRIL 1998 – REVISED JULY 2001
PW PACKAGE
(TOP VIEW)
Spread Spectrum Clock Compatible
100-MHz Maximum Frequency
Available in Plastic 24-Pin TSSOP
AGND
CLK
AV
1
24
23
22
21
20
19
18
17
16
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
V
2
CC
CC
1Y0
1Y1
1Y2
GND
GND
1Y3
V
3
CC
1Y9
1Y8
GND
GND
1Y7
1Y6
4
Distributes One Clock Input to One Bank of
Ten Outputs
5
6
Single Output Enable Terminal Controls All
Ten Outputs
7
8
External Feedback (FBIN) Pin Is Used to
Synchronize the Outputs to the Clock Input
1Y4
9
V
10
11
12
15 1Y5
CC
G
On-Chip Series Damping Resistors
No External RC Network Required
V
14
13
CC
FBOUT
FBIN
Operates at 3.3-V V
CC
description
The CDC2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
ItisspecificallydesignedforusewithsynchronousDRAMs.TheCDC2510Aoperatesat3.3-VV andprovides
CC
integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output
enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input
is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2510A does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2510A requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AV
to ground.
CC
The CDC2510A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
CLK
OUTPUTS
1Y
G
FBOUT
(0:9)
X
L
L
L
L
L
H
H
H
H
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2510A
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS604B– APRIL 1998 – REVISED JULY 2001
functional block diagram
11
G
3
4
5
8
9
1Y0
1Y1
1Y2
1Y3
1Y4
15
16
1Y5
1Y6
1Y7
1Y8
17
20
21
12
24
CLK
PLL
13
FBIN
1Y9
23
AV
CC
FBOUT
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
(PW)
0°C to 70°C
CDC2510A
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2510A
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS604B– APRIL 1998 – REVISED JULY 2001
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME
NO.
Clock input. CLK provides the clock signal to be distributed by the CDC2510A clock driver. CLK is
usedtoprovidethereferencesignaltotheintegratedPLLthatgeneratestheclockoutputsignals. CLK
must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is
powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock
the feedback signal to its reference signal.
CLK
24
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
FBIN
G
13
11
12
I
Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are
disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the same
frequency as CLK.
I
O
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
and integrated 25-Ω series-damping resistor.
FBOUT
1Y (0:9)
3, 4, 5, 8, 9
15, 16, 17, 20,
21
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via
the G input. These outputs can be disabled to a logic-low state by deasserting the G control input.
Each output has an integrated 25-Ω series-damping resistor.
O
Analog power supply. AV
CC
provides the power reference for the analog circuitry. In addition, AV
CC
AV
CC
23
Power
can be used to bypass the PLL for test purposes. When AV
is strapped to ground, PLL is bypassed
CC
and CLK is buffered directly to the device outputs.
AGND
1
Ground Analog ground. AGND provides the ground reference for the analog circuitry.
Power Power supply
Ground Ground
V
CC
GND
2, 10, 14, 22
6, 7, 18, 19
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2510A
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS604B– APRIL 1998 – REVISED JULY 2001
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, AV
Supply voltage range, V , AV
Input voltage range, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV
< V
+0.7 V
CC
CC
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
CC
I
or low state, V (see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V
Maximum power dissipation at T = 55°C (in still air) (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, T
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. AV
must not exceed V
.
CC
CC
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 4.6 V maximum.
4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation, refertothePackageThermalConsiderationsapplicationnoteintheABTAdvancedBiCMOSTechnologyData
Book, literature number SCBD002.
recommended operating conditions (see Note 5)
MIN
3
MAX
UNIT
V
Supply voltage, V , AV
CC CC
3.6
High-level input voltage, V
IH
2
V
Low-level input voltage, V
0.8
V
IL
Input voltage, V
0
0
V
V
I
CC
High-level output current, I
–12
12
mA
mA
°C
OH
Low-level output current, I
OL
Operating free-air temperature, T
70
A
NOTE 5: Unused inputs must be held high or low to prevent them from floating.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2510A
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS604B– APRIL 1998 – REVISED JULY 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
AV , V
CC CC
MIN TYP
MAX
UNIT
V
IK
I = –18 mA
I
3 V
–1.2
V
I
I
I
I
I
I
= –100 µA
= –12 mA
= –6 mA
= 100 µA
= 12 mA
= 6 mA
MIN to MAX
3 V
V
CC
–0.2
2.1
OH
OH
OH
OL
OL
OL
V
V
V
OH
3 V
2.4
MIN to MAX
3 V
0.2
0.8
0.55
±5
V
OL
3 V
I
I
V = V
or GND
or GND,
3.6 V
µA
µA
µA
pF
pF
I
I
CC
CC
§
V = V
I = 0, Outputs: low or high
O
3.6 V
10
CC
I
∆I
CC
One input at V
CC
– 0.6 V,
Other inputs at V
or GND
3.3 V to 3.6 V
3.3 V
500
CC
C
C
V = V
or GND
4
6
i
I
CC
= V or GND
CC
V
3.3 V
o
O
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
For I of AV , see Figure 5.
CC
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
80
MAX
100
60%
1
UNIT
f
Clock frequency
MHz
clk
Input clock duty cycle
40%
†
Stabilization time
ms
†
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phasereferencesignalmustbepresentatCLK. Untilphaselockisobtained, thespecificationsforpropagationdelay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
switching characteristics over recommended ranges of supply voltage and operating free-air
‡
temperature, C = 30 pF (see Note 6 and Figures 1 and 2)
L
V
, AV
± 0.165 V
= 3.3 V
V
, AV
± 0.3 V
= 3.3 V
CC
CC
CC
CC
FROM
(INPUT)/CONDITION
TO
(OUTPUT)
PARAMETER
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
t
, reference
phase error
80 MHz < CLKIN↑ ≤ 100 MHz
FBIN↑
–700
–300
ps
(see Note 7, Figure 3)
t
– jitter
phase error
(see Note 8)
CLKIN↑ = 100 MHz
Any Y or FBOUT
Clkin = 100 MHz
FBIN↑
–750
–350
–540
ps
ps
ps
§
t
Any Y or FBOUT
Any Y or FBOUT
200
150
sk(o)
Jitter
(see Figure 4)
(pk-pk)
–150
Duty cycle reference
(see Figure 4)
F(clkin > 80 MHz)
Any Y or FBOUT
45%
55%
t
t
Any Y or FBOUT
Any Y or FBOUT
1.3
1.7
1.9
2.5
0.8
1.2
2.1
2.7
ns
ns
r
f
‡
§
These parameters are not production tested.
The t
specification is only valid for equal loading of all outputs.
sk(o)
NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
7. This is considered as static phase error.
8. Phase error does not include jitter. The total phase error is –900 ps to –200 ps for the 5% V
range.
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2510A
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS604B– APRIL 1998 – REVISED JULY 2001
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
Input
50% V
CC
t
pd
From Output
Under Test
V
V
OH
2 V
0.4 V
2 V
Output
500
50% V
CC
0.4 V
30 pF
OL
t
t
f
r
LOAD CIRCUIT FOR OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, Z = 50 Ω, t ≤ 1.2 ns, t ≤ 1.2 ns.
O
r
f
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
CLKIN
FBIN
t
phase error
FBOUT
Any Y
t
sk(o)
Any Y
Any Y
t
sk(o)
Figure 2. Phase Error and Skew Calculations
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2510A
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS604B– APRIL 1998 – REVISED JULY 2001
TYPICAL CHARACTERISTICS
STATIC PHASE ERROR
vs
CLOCK FREQUENCY
JITTER (PEAK-TO-PEAK)
vs
CLOCK FREQUENCY
–300
–350
–400
–450
–500
–550
–600
–650
550
500
450
400
350
300
250
200
AV , V
CC CC
A
= 3.3 V
AV , V
CC CC
= 3.3 V
T
= 25°C
R
C
T
= 500 Ω
= 30 pF
= 25°C
L
L
A
All Outputs Switching
–700
–750
150
100
60
70
80
90
100
110
120
130
60
70
80
90
100
110
120
130
f
– Clock Frequency – MHz
clk
f
– Clock Frequency – MHz
clk
Figure 3
Figure 4
ANALOG SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
CLOCK FREQUENCY
CLOCK FREQUENCY
14
250
200
150
100
50
AV , V
CC CC
A
= 3.3 V
V
T
= 3.6 V
CC
= 25°C
T
= 25°C
A
12
10
CLY = CLF = 30 pF
8
6
4
2
0
0
30
50
f
70
90
110
130
20
40
60
80
100
120
140
– Clock Frequency – MHz
f
– Clock Frequency – MHz
clk
clk
Figure 5
Figure 6
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2510A
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS604B– APRIL 1998 – REVISED JULY 2001
MECHANICAL INFORMATION
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,30
0,19
0,65
M
0,10
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
0,75
A
0,50
Seating Plane
0,10
1,20 MAX
0,05 MIN
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/E 08/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Post Office Box 655303
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Copyright 2001, Texas Instruments Incorporated
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