CDC318ADLR [TI]
具有 I2C 控制接口的 1 线路至 18 线路时钟驱动器 | DL | 48 | 0 to 70;
| 型号： | CDC318ADLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 I2C 控制接口的 1 线路至 18 线路时钟驱动器 | DL | 48 | 0 to 70 时钟 驱动 时钟驱动器 |
| 文件： | 总12页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
2
WITH I C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
DL PACKAGE
(TOP VIEW)
High-Speed, Low-Skew 1-to-18 Clock Buffer
for Synchronous DRAM (SDRAM) Clock
Buffering Applications
1
2
3
4
5
6
7
8
9
48
47
46
NC
NC
NC
NC
Output Skew, t
, Less Than 250 ps
sk(o)
Pulse Skew, t
, Less Than 500 ps
sk(p)
V
V
CC
CC
Supports up to Four Unbuffered SDRAM
Dual Inline Memory Modules (DIMMs)
1Y0
1Y1
GND
45 4Y3
44 4Y2
43 GND
2
I C Serial Interface Provides Individual
Enable Control for Each Output
V
42
V
CC
CC
1Y2
1Y3
41 4Y1
40 4Y0
39 GND
38 OE
Operates at 3.3 V
Distributed V
Switching Noise
and Ground Pins Reduce
CC
GND 10
A
11
12
100-MHz Operation
V
V
37
36 3Y3
CC
CC
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
2Y0 13
2Y1
GND
3Y2
GND
14
15
16
17
18
19
20
21
22
23
24
35
34
33
32
31
30
29
28
27
26
25
Packaged in 48-Pin Shrink Small Outline
(DL) Package
V
V
CC
CC
2Y2
2Y3
GND
3Y1
3Y0
GND
description
The CDC318A is a high-performance clock buffer
designed to distribute high-speed clocks in PC
applications. This device distributes one input (A)
to 18 outputs (Y) with minimum skew for clock
distribution. The CDC318A operates from a 3.3-V
power supply. It is characterized for operation
from 0°C to 70°C.
V
V
CC
CC
5Y0
GND
5Y1
GND
GND
SCLOCK
V
CC
SDATA
NC – No internal connection
This device has been designed with consideration
foroptimizedEMIperformance. Dependingonthe
application layout, damping resistors in series to
the clock outputs (like proposed in the PC100
specification) may not be needed in most cases.
2
The device provides a standard mode (100K-bits/s) I C serial interface for device control. The implementation
2
2
is as a slave/receiver. The device address is specified in the I C device address table. Both of the I C inputs
(SDATA and SCLOCK) are 5-V tolerant and provide integrated pullup resistors (typically 140 kΩ).
2
Three 8-bit I C registers provide individual enable control for each of the outputs. All outputs default to enabled
at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit
is written to the control register. The registers are write only and must be accessed in sequential order (i.e.,
random access of the registers is not supported).
The CDC318A provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a
high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state.
When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Intel is a trademark of Intel Corporation
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
2
WITH I C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
FUNCTION TABLE
OUTPUTS
INPUTS
OE
L
A
X
L
1Y0–1Y3
2Y0–2Y3
3Y0–3Y3
4Y0–4Y3
5Y0–5Y1
Hi-Z
L
Hi-Z
L
Hi-Z
L
Hi-Z
L
Hi-Z
L
H
†
†
†
†
†
H
H
H
H
H
H
H
†
2
The function table assumes that all outputs are enabled via the appropriate I C configuration register bit. If the output is disabled
via the appropriate configuration bit, then the output is driven to a low state, regardless of the state of the A input.
logic diagram (positive logic)
38
OE
24
SDATA
2
I C
18
Register
Space
2
I C
/
4, 5, 8, 9
13, 14, 17, 18
31, 32, 35, 36
25
11
1Y0–1Y3
SCLOCK
2Y0–2Y3
3Y0–3Y3
4Y0–4Y3
5Y0–5Y1
A
40, 41, 44, 45
21, 28
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
2
WITH I C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME
1Y0–1Y3
2Y0–2Y3
3Y0–3Y3
4Y0–4Y3
5Y0–5Y1
A
4, 5, 8, 9
13, 14, 17, 18
31, 32, 35, 36
40, 41, 44, 45
21, 28
O
O
O
O
O
I
3.3-V SDRAM byte 0 clock outputs
3.3-V SDRAM byte 1 clock outputs
3.3-V SDRAM byte 2 clock outputs
3.3-V SDRAM byte 3 clock outputs
3.3-V clock outputs provided for feedback control of external phase-locked loops (PLLs)
Clock input
11
Output enable. When asserted, OE puts all outputs in a high-impedance state. A nominal
140-kΩ pullup resistor is internally integrated.
38
25
24
I
I
OE
2
I C serial clock input. A nominal 140-kΩ pullup resistor is internally integrated.
SCLOCK
SDATA
2
Bidirectional I C serial data input/output. A nominal 140-kΩ pullup resistor is internally
I/O
integrated.
6, 10, 15, 19, 22, 26,
27, 30, 34, 39, 43
Ground
GND
NC
1, 2, 47, 48
No internal connection. Reserved for future use.
3.3-V power supply
3, 7, 12, 16, 20, 23,
29, 33, 37, 42, 46
V
CC
2
I C DEVICE ADDRESS
A7
A6
A5
A4
A3
A2
A1
A0 (R/W)
H
H
L
H
L
L
H
—
2
†
I C BYTE 0-BIT DEFINITION
BIT
7
DEFINITION
DEFAULT VALUE
2Y3 enable (pin 18)
2Y2 enable (pin 17)
2Y1 enable (pin 14)
2Y0 enable (pin 13)
1Y3 enable (pin 9)
1Y2 enable (pin 8)
1Y1 enable (pin 5)
1Y0 enable (pin 4)
H
H
H
H
H
H
H
H
6
5
4
3
2
1
0
†
When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
2
WITH I C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
2
†
I C BYTE 1-BIT DEFINITION
BIT
7
DEFINITION
DEFAULT VALUE
4Y3 enable (pin 45)
4Y2 enable (pin 44)
4Y1 enable (pin 41)
4Y0 enable (pin 40)
3Y3 enable (pin 36)
3Y2 enable (pin 35)
3Y1 enable (pin 32)
3Y0 enable (pin 31)
H
H
H
H
H
H
H
H
6
5
4
3
2
1
0
†
When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.
2
†
I C BYTE 2-BIT DEFINITION
BIT
7
DEFINITION
5Y1 enable (pin 28)
5Y0 enable (pin 21)
Reserved
DEFAULT VALUE
H
H
H
H
H
H
H
H
6
5
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
†
When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
2
WITH I C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Input voltage range, V (SCLOCK, SDATA) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
I
Output voltage range, V (SDATA) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
O
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . –0.5 V to V
+0.5 V
O
CC
Current into any output in the low state (except SDATA), I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
Current into SDATA in the low state, I
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 mA
O
Input clamp current, I (V < 0) (SCLOCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0) (SDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Package thermal impedance, θ (see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84°C/W
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 C
JA
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero. The absolute maximum power dissipation allowed at T = 55°C (in still air) is 1.2 W.
A
3. Thermal impedance (Θ ) can be considerably lower if the device is soldered on the PCB board with a copper layer underneath the
JA
package. A simulation on a PCB board (3 in. × 3 in.) with two internal copper planes (1 oz. cu, 0.036 mm thick) and 0.071 mm cu
(202) in area underneath the package, resulted in Θ = 60°C/W. This would allow 1.2 W total power dissipation at TA = 70°C.
JA
recommended operating conditions (see Note 4)
MIN
3.135
2
TYP
MAX
UNIT
V
V
3.3-V core supply voltage
High-level input voltage
3.465
CC
IH
A, OE
V
+0.3
V
CC
V
SDATA, SCLOCK
(see Note 3)
2.2
–0.3
0
5.5
V
V
V
A, OE
0.8
V
IL
Low-level input voltage
SDATA, SCLOCK
(see Note 3)
1.04
I
I
High-level output current
Low-level output current
Y outputs
Y outputs
–36
24
mA
mA
OH
OL
SDATA, SCLOCK
(see Note 3)
r
i
Input resistance to V
140
kΩ
CC
f
t
t
t
t
t
t
t
t
t
t
SCLOCK frequency
Bus free time
100
kHz
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs
°C
(SCL)
4.7
4.7
4
(BUS)
START setup time
START hold time
su(START)
h(START)
w(SCLL)
w(SCLH)
r(SDATA)
f(SDATA)
su(SDATA)
h(SDATA)
su(STOP)
SCLOCK low pulse duration
SCLOCK high pulse duration
SDATA input rise time
SDATA input fall time
SDATA setup time
4.7
4
1000
300
250
20
4
SDATA hold time
STOP setup time
T
Operating free-air temperature
0
70
A
NOTE 4: The CMOS-level inputs fall within these limits: V min = 0.7 × V
IH
and V max = 0.3 × V
IL
.
CC
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
2
WITH I C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
Input clamp voltage
V
V
= 3.135 V,
I = –18 mA
–1.2
V
IK
CC
I
V
0.1 V
–
CC
= Min to Max,
I
= –1 mA
CC
OH
V
OH
High-level output voltage
Low-level output voltage
Y outputs
Y outputs
V
V
V
CC
V
CC
V
CC
= 3.135 V,
I
I
I
I
I
= –36 mA
= 1 mA
2.4
OH
OL
OL
OL
OL
= Min to Max,
= 3.135 V,
0.1
0.4
= 24 mA
= 3 mA
V
OL
0.4
SDATA
SDATA
V
CC
= 3.135 V
= 6 mA
0.6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3.135 V,
= 3.135 V,
= 3.3 V,
V
O
V
O
V
O
V
O
V
O
V
O
V
O
= V
MAX
20
µA
CC
= 2 V
–54
–126
I
High-level output current
OH
Y outputs
Y outputs
= 1.65 V
= 3.135 V
= 1 V
–92
93
mA
= 3.465 V,
= 3.135 V,
= 3.3 V,
–21
49
–46
118
I
I
I
Low-level output current
High-level input current
Low-level input current
= 1.65 V
= 0.4 V
mA
µA
µA
OL
IH
IL
= 3.465 V,
24
53
5
A
OE
V
= 3.465 V,
= 3.465 V,
V = V
I CC
20
CC
CC
SCLOCK, SDATA
20
A
–5
–50
–50
±10
50
OE
V
V = GND
I
–10
–10
SCLOCK, SDATA
I
I
I
High-impedance-state output current
V
CC
V
CC
V
CC
V
CC
= 3.465 V,
= 0,
V = 3.465 V or 0
O
µA
µA
OZ
Off-state current
Supply current
SCLOCK, SDATA
V = 0 V to 5.5 V
I
off
= 3.465 V,
I
O
= 0
0.2
0.5
mA
CC
= 3.135 V to 3.465 V,
– 0.6 V,
∆I
CC
Change in supply current
One input at V
CC
All other inputs at V
500
µA
or GND
CC
Dynamic I
at 100 MHz
V
= 3.465 V,
C
= 20 pF,
230
4
mA
pF
pF
CC
CC
V = V
L
C
C
C
Input capacitance
or GND,
V
V
V
= 3.3 V
= 3.3 V
= 3.3 V
I
I
CC
= V
CC
CC
Output capacitance
SDATA I/O capacitance
V
O
or GND,
6
O
CC
= V
V
I/O
or GND,
7
pF
I/O
CC
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
2
WITH I C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
switching characteristics over recommended operating conditions
PARAMETER
FROM
TO
TEST CONDITIONS
MIN
MAX
UNIT
A
Y
1.2
4.5
ns
t
t
t
t
Low-to-high level propagation delay time
SDATA
valid
V
= 3.3 V ±0.165 V,
PLH
PLH
PHL
PHL
CC
SCLOCK↓
2
µs
See Figure 3
V
= 3.3 V ±0.165 V,
CC
See Figure 3
Low-to-high level propagation delay time
High-to-low level propagation delay time
High-to-low level propagation delay time
SDATA↑
A
Y
Y
150
4.5
2
ns
ns
µs
1.2
SDATA
valid
V
= 3.3 V ±0.165 V,
CC
See Figure 3
SCLOCK↓
V
= 3.3 V ±0.165 V,
CC
See Figure 3
SDATA↑
Y
Y
150
ns
ns
t
t
t
t
t
t
t
t
Enable time to the high level
Enable time to the low level
Disable time from the high level
Disable time from the low level
Skew time
1
1
1
1
7
7
PZH
PZL
PHZ
PLZ
sk(o)
sk(p)
sk(pr)
r
OE
7
OE
Y
ns
7
A
A
A
Y
Y
Y
Y
250
500
1
ps
ps
ns
ns
Skew time
Skew time
Rise time
0.5
6
2.2
C
C
= 10 pF
Rise time (see Note 5 and
Figure 3)
L
L
t
r
t
f
t
f
SDATA
ns
ns
ns
= 400 pF
950
2.3
Fall time
Y
0.5
20
C
C
= 10 pF
Fall time (see Note 5 and
Figure 3)
L
L
SDATA
= 400 pF
250
NOTE 5: This parameter has a lower limit than BUS specification. This allows use of series resistors for current spike protection.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
2
WITH I C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
PARAMETER MEASUREMENT INFORMATION
6 V
S1
TEST
/t
S1
Open
6 V
500 Ω
Open
GND
From Output
Under Test
t
t
t
PLH PHL
/t
PLZ PZL
C
= 30 pF
/t
GND
L
PHZ PZH
500 Ω
(see Note A)
t
w
LOAD CIRCUIT FOR t AND t
pd
sk
3 V
0 V
Input
1.5 V
1.5 V
From Output
Under Test
VOLTAGE WAVEFORMS
C
= 30 pF
L
(see Note A)
V
CC
Output
Enable
(high-level
enabling)
LOAD CIRCUIT FOR t AND t
r
f
1.5 V
1.5 V
0 V
t
PZL
3 V
0 V
t
PLZ
Input
1.5 V
1.5 V
≈ 3 V
Output
Waveform 1
S1 at 6 V
1.5 V
t
PLH
V
V
+ 0.3 V
OL
t
PHL
V
OL
OH
(see Note B)
t
V
V
PHZ
OH
2.4 V
0.4 V
2.4 V
t
PZH
Output
1.5 V
Output
Waveform 2
S1 at GND
0.4 V
V
OL
– 0.3 V
OH
1.5 V
t
r
t
f
(see Note B)
≈ 0 V
VOLTAGE WAVEFORMS
C includes probe and jig capacitance.
L
VOLTAGE WAVEFORMS
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
2
WITH I C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
PARAMETER MEASUREMENT INFORMATION
A
1Y0
t
t
t
t
t
t
t
t
t
t
t
PHL1
1Y1
PLH1
PHL2
1Y2
PLH2
t
t
t
t
t
t
t
PHL3
1Y3
PLH3
PLH4
PLH5
PLH6
PLH7
PLH8
PLH9
PHL4
2Y0
PHL5
2Y1
PHL6
2Y2
PHL7
2Y3
PHL8
3Y0
PHL9
3Y1
t
t
PLH10
PHL10
3Y2
t
t
PHL11
3Y3
PLH11
PLH12
PLH13
PLH14
PLH15
PLH16
PLH17
PLH18
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PHL12
4Y0
PHL13
4Y1
PHL14
4Y2
PHL15
4Y3
PHL16
5Y0
PHL17
5Y1
PHL18
NOTES: A. Output skew, t , is calculated as the greater of:
sk(o)
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
(n = 1:18)
(n = 1:18)
PLHn
PHLn
B. Pulse skew, t
, is calculated as the greater of |t
– t
| (n = 1:18)
sk(p)
PLHn PHLn
, is calculated as the greater of:
C. Process skew, t
sk(pr)
– Thedifferencebetweenthefastestandslowestoft
– Thedifferencebetweenthefastestandslowestoft
(n=1:18)acrossmultipledevicesunderidenticaloperatingconditions
(n=1:18)acrossmultipledevicesunderidenticaloperatingconditions
PLHn
PHLn
Figure 2. Waveforms for Calculation of t
, t
, t
sk(o) sk(p) sk(pr)
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
2
WITH I C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
PARAMETER MEASUREMENT INFORMATION
V
= 3.3 V
O
R
= 1 kΩ
L
DUT
C
C
= 10 pF or
L
= 400 pF
L
GND
TEST CIRCUIT
4 to 6 Bytes for Complete Device
Programming
Bit 0
LSB
(R/W)
Stop
Condition
(P)
Start
Condition
(S)
Bit 7
MSB
Acknowledge
(A)
Bit 6
t
t
t
w(SCLH)
su(START)
w(SCLL)
SCLOCK
0.7 V
0.3 V
CC
CC
t
su(START)
t
r
t
PHL
t
f
t
t
PLH
(BUS)
0.7 V
0.3 V
CC
CC
SDATA
t
t
r(SDATA)
f(SDATA)
t
t
h(SDATA)
su(STOP)
t
h(START)
t
Repeat Start
su(SDATA)
Condition
(see Note A)
Stop Condition
Start or
Repeat Start
Condition
VOLTAGE WAVEFORMS
DESCRIPTION
BYTE
2
I C address
1
2
3
4
5
6
Command (dummy value, ignored)
Byte count (dummy value, ignored)
2
I C data byte 0
2
I C data byte 1
2
I C data byte 2
NOTES: A. The repeat start condition is not supported.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 kHz, Z = 50 Ω, t ≥ 10 ns, t ≥ 10 ns.
O
r
f
Figure 3. Propagation Delay Times, t and t
r
f
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
2
WITH I C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
MECHANICAL INFORMATION
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PIN SHOWN
0.025 (0,635)
0.012 (0,305)
0.008 (0,203)
0.005 (0,13)
25
M
48
0.006 (0,15) NOM
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–8°
1
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/C 03/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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