CDC857-3DGGG4 [TI]
PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, PLASTIC, TSSOP-48;
| 型号： | CDC857-3DGGG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, PLASTIC, TSSOP-48 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总12页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
DGG PACKAGE
(TOP VIEW)
Phase-Lock Loop Clock Distribution for
Double Data Rate Synchronous DRAM
Applications
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
Y0
GND
Y5
Distributes One Differential Clock Input to
Ten Differential Outputs
2
3
Y0
Y5
External Feedback Pins (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Clock Input
4
V
V
CC
Y1
CC
5
Y6
6
Y1
Y6
Operates at V
= 2.5 V and AV
= 3.3 V
CC
CC
7
GND
GND
Y2
GND
GND
Y7
Packaged in Plastic 48-Pin (DGG) Thin
Shrink Small-Outline Package (TSSOP)
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Y2
Y7
Spread Spectrum Clocking Tracking
Capability to Reduce EMI
V
V
V
CC
CC
CLK
CLK
CC
G
description
FBIN
FBIN
The CDC857-2 and CDC857-3 are high-perfor-
mance, low-skew, low-jitter, phase-lock loop
(PLL) clock driver. They use a PLL to precisely
align, in both frequency and phase, the feedback
(FBOUT) output to the clock (CLK) input signal.
The CDC857-3 operates at 3.3 V (PLL) and 2.5 V
(output buffer). The CDC857-2 operates at
2.5 V (PLL and output buffer).
V
V
CC
CC
AGND
GND
Y3
CC
AV
FBOUT
FBOUT
GND
Y8
Y3
Y8
V
V
CC
Y4
CC
Y9
One bank of ten inverting and noninverting
outputs provide ten low-skew, low-jitter copies of
CLK. Output signal duty cycles are adjusted to
50%, independent of the duty cycle at CLK.
Y4
Y9
GND
GND
All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs
switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to high impedance
state (3-state).
Unlike many products containing PLLs, the CDC857 does not require external RC networks. The loop filter for
the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuity, the CDC857 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL can be bypassed for test purposes by strapping AV
to ground. If AV
is at GND
CC
CC
and V = ON, 2 falling edges on G cause the PLL to run with FBOUT being enabled and all other outputs being
CC
disabled, after AV
ramps up to its specified V
value, with G being kept low. The CDC857 is characterized
CC
CC
for operation from 0°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
FUNCTION TABLE
INPUTS
OUTPUTS
PLL
G
L
CLK
CLK
Y
Z
L
Y
Z
H
L
FBOUT
FBOUT
X
X
Z
L
Z
H
L
OFF
RUN
RUN
OFF
H
H
H
L
H
H
L
H
Z
H
Z
< 20 MHz
< 20 MHz
Z
Z
logic symbol
Test
G
Mode
Logic
Y0
Y0
Y1
AV
CC
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Clk
Clk
Y7
Y8
PLL
Y8
Y9
FBIN
FBIN
Y9
AV
= 3.3 V
CC
FBOUT
FBOUT
NOTE A: All outputs are connected to V
= 2.5 V.
CC
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
SPECIAL TEST MODES
INPUTS
OUTPUTS
COMMENTS
V
CC
AV
CC
G
L
CLK
L
Y
Z
Z
L
Y
Z
Z
H
L
FBOUT
FBOUT
†
ON
ON
ON
ON
ON
ON
0 V
Z
Z
L
Z
Z
H
L
Clock Mode
Clock Mode
Clock Mode
Clock Mode
PLL Mode
0 V
0 V
0 V
L
H
H
H
L
H
H
Z
Z
H
L
‡
§
UP
UP
↓
L
Z
Z
H
L
‡
§
↓
H
H
PLL Mode
†
‡
§
Only one signal shown for this differential input.
AV ramped up after two (2) high-to-low transitions on G input & G being low.
CC
At least two (2) high-to-low transitions during AV
= 0.
CC
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
AGND
AV
NO.
17
16
Ground
Power
Analog ground. AGND provides the ground reference for the analog circuitry.
Analogpower supply. AV provides the power reference for the analog circuitry. Inaddition, AV
CC
CC CC
canbeusedtobypassthePLLfortestpurposes.WhenAV isstrappedtoground,PLLisbypassed
CC
and CLK is buffered directly to the device outputs. During disable (G = 0), the PLL is powered down.
CLK
CLK
13
14
I
I
Clock input, CLK provides the clock signal to be distributed by the CDC857 clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK
must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is
powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase
lock the feedback signal to its reference signal.
FBIN
FBIN
36
35
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired
to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
FBOUT
FBOUT
32
33
O
I
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL.
G
37
Outputbankenable. GistheoutputenableforoutputsYandY. WhenGislowoutputsYaredisabled
to a high-impedance state. When G is high, all outputs Y are enabled and switch at the same
frequency as CLK.
GND
1, 7, 8, 18,
24, 25, 31,
41, 42, 48
Ground
Power
O
Ground
V
CC
4, 11, 12,
15, 21, 28,
34, 38, 45
Power supply
Y0, Y1, Y2,
Y3, Y4, Y5,
Y6, Y7, Y8,
Y9
3, 5, 10,
20, 22, 46,
44, 39, 29,
27
Clock outputs. These outputs provide low-skew copies of CLK.
Y0, Y1, Y2,
Y3, Y4, Y5,
Y6, Y7, Y8,
Y9
2, 6, 9,
19, 23, 47,
43, 40, 30,
26
O
Clock outputs. These outputs provide low-skew copies of CLK.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
or AV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
CC
Input voltage range V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+0.5 V
+0.5 V
I
CC
CC
Output voltage range, V , (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
IK
I
I
CC
Output clamp current, I
Continuous total output current, I (V = 0 to V )
(V < 0 or V > V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θ (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
OK
O
O
CC
O
O
CC
JA
stg
Storage temperature range T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN
2.3
2.3
3
NOM
MAX
2.7
UNIT
V
Supply voltage, V
CC
CDC857–2
CDC857–3
2.7
V
Analog supply voltage, AV
CC
3.6
V
V
G input
0.3 × V
V
Low–level input voltage, IL(G)
CC
V
G input
0.7 × V
V
High–level input voltage, IH(G)
CC
DC input signal voltage (see Note 5)
CLK, FBIN
CLK, FBIN
CLK, FBIN
–0.3
V
CC
V
CC
V
CC
+0.3
+0.6
+0.6
V
dc
ac
0.35
0.7
V
Differential input signal voltage, V
(see Note 6)
ID
V
Differential cross-point input voltage (see Note 7)
V
CC
/2–0.2
V
CC
/2
V
CC
/2+0.2
–12
V
High-level output current, I
mA
mA
V/ns
°C
OH
Low-level output current, I
Input slew rate, SR
12
OL
1
0
Operating free-air temperature, T
85
A
NOTES: 4. Unused inputs must be held high or low to prevent them from floating.
5. DC input signal voltage specifies the allowable dc execution of differential input.
6. Differentialinput signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level
and VCP is the complementary input level (see figure 3).
7. Differential cross-point voltage is expected to track variations of V
crossing.
and is the voltage at which the differential signals must be
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
All input pins
V
V
V
V
V
V
V
= 2.3 V,
I
I
= –18 mA
–1.2
V
IK
CC
CC
CC
CC
CC
CC
CC
= min to max, I
–1 mA
V
CC
–0.1
1.7
OH=
OH =
High-level output voltage
Low-level output voltage
V
V
OH
= 2.3 V,
I
–12 mA
= min to max, I
= 1 mA
= 12 mA
= 1 V
0.1
0.6
OL
OL
V
OL
= 2.3 V,
= 2.3 V,
= 2.3 V,
I
I
I
High-level output current
Low-level output current
Output voltage swing
V
–18
26
–32
35
mA
mA
V
OH
O
O
V
= 1.2 V
OL
V
O
For load condition see Figure 3
1.1
V
–0.4
±10
±10
±10
CC
V
CC
V
CC
V
CC
= 2.7 V,
= 2.7 V,
V = 0 V to 2.7 V
I
G
I
I
Input current
µA
I
CLK, FBIN
V = 0 V to 2.7 V
I
High-impedance output current
= 2.7 V
V
O
= V or GND
CC
µA
OZ
,
(V /2)–
CC
(V /2)+
CC
‡
V
OC
V
CC
/2
V
Output crossing point voltage
0.1
0.1
AV
CC
and V
= max,
CC
I
Supply current, disabled
500
235
800
µA
CCZ
G = L or no input CLK signal
V
= 2.7 V, = 167 MHz,
f
O
CC
All outputs switching 16 pF in 60 Ω
environment, See Figure 3
Supply current on V
(see Figure 7)
CC
l
300
mA
CC
CDC857–2
CDC857–3
AV
AV
= 2.7 V,
= 3.6 V,
f
f
= 167 MHz
= 167 MHz
9
15
2
12
19
CC
O
Supply current on
AI
CC
mA
AV
CC
CC
O
C
C
Input capacitance
Output capacitance
V
= 2.5 V,
V = V
or GND
pF
pF
I
CC
CC
I
CC
= 2.5 V,V = V or GND
CC
V
3
O
O
†
‡
All typical values are at respective nominal V
.
CC
is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120-Ω resistor, where VTR is the true input
The value of V
OC
signal voltage and VCP is the complementary input signal voltage (see Figure 3).
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
timing requirements over recommended ranges or supply voltage and operating free–air
temperature
PARAMETER
Clock frequency
Input clock duty cycle
TEST CONDITIONS
MIN
66
MAX
167
60%
0.1
UNIT
f
C
MHz
40%
†
Stabilization time
ms
†
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed–frequency, fixed–phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay,
skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation
under SSC application.
switching characteristics
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
Low–to high level propagation delay time
‡
‡
t
t
CLK mode/CLK to any output
1.5
1.5
3.5
3.5
6
ns
PLH
(see Figure 5)
High–to low level propagation delay time
(see Figure 5)
CLK mode/CLK to any output
6
ns
PHL
t
t
Output enable time
Output disable time
CLK mode/G to any Y output
CLK mode/G to any Y output
66 MHz
3
3
ns
ns
en
dis
120
75
t
Jitter (peak-to–peak)
Jitter (cycle-to-cycle)
ps
ps
(jitter)
(jitter)
100/125/133/167 MHz
66 MHz
110
t
100/125/133/167 MHz
65
t
t
t
Phase error (see Figure 4)
Output skew (see Figure 4)
Pulse skew
–150
150
100
100
50.5%
51%
950
ps
ps
ps
(phase error)
All differential input and output termi-
nals are terminated with 120 Ω/
16 pF as shown in Figure 2
skew(0)
skew(p)
66 MHz to 100 MHz
101 MHz to 167 MHz
Load = 120 Ω/16 pF
49.5%
49%
650
§
Duty cycle (see Figure 6)
t , t
r f
Output rise and fall times (20% – 80%)
800
ps
‡
§
Refers to transition of noninverting output.
While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty
cycle = t /t , were the cycle time (t ) decreases as the frequency goes up.
wH c
c
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
APPLICATION EXAMPLE
Table 1. Clock Structure and SDRAM Loads per Clock
CAPACITIVE LOADING ON
NUMBER of
CLOCK
STRUCTURE
THE PLL OUTPUTS (pF)
SDRAM LOADS
PER CLOCK
MIN
5
MAX
8
1
2
2
4
10
16
≈ 2.5”
≈ 0.6” (Split to Terminator)
SDRAM represents
a capacitive load
SDRAM
SDRAM
VTR
VCP
120 Ω
CLK
CLK
PLL
16 pF
120 Ω
0.3”
FBIN
FBIN
16 pF
120 Ω
Figure 1. Clock Structure #1
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
APPLICATION EXAMPLE
≈ 2.5”
≈ 0.6” (Split to Terminator)
SDRAM represents
a capacitive load
SDRAM
Stack
CLK
CLK
PLL
VTR
VCP
16 pF
120 Ω
120 Ω
FBIN
SDRAM
Stack
16 pF
120 Ω
FBIN
0.3”
Figure 2. Clock Structure #2
differential clock signals
Figure 3 shows the differential clocks are directly terminated by a 120-Ω resistor.
V
CC
V
CC
VTR
Device
Under
Test
60 Ω
60 Ω
OUT
OUT
R
= 120 Ω
T
VCP
Receiver
Figure 3. Differential Signal Using Direct Termination Resistor
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
CLKIN
FBIN
t
(phase error)
FBOUT
Yx
t
sk(o)
Yx
Yx
t
sk(o)
Figure 4. Phase Error and Skew Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
CLKIN
Yx or FBIN
t
pd
Figure 5. Propagation Delay Time; t
, t
PLH PHL
Yx
Yx
t
WH
t
c
NOTE A: Duty cycle = t
/t
WH c
Figure 6. Output Duty Cycle
Yx
t
c(n)
t
c(n+1)
NOTE A: Cycle-to-cycle jitter = |t | over 2000 consecutive cycles.
– t
c(n) c(n+1)
Figure 7. Cycle-to-Cycle Jitter
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
MECHANICAL DATA
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PIN SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: B. All linear dimensions are in millimeters.
C. This drawing is subject to change without notice.
D. Body dimensions do not include mold protrusion not to exceed 0,15.
E. Falls within JEDEC MO-153
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
相关型号：
CDC857-3DGGR
PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, PLASTIC, TSSOP-48
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