CDC925DLR [TI]
133MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56, GREEN, PLASTIC, SSOP-56;
| 型号： | CDC925DLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 133MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56, GREEN, PLASTIC, SSOP-56 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总19页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
DL PACKAGE
(TOP VIEW)
Supports Pentium III Class Motherboards
Uses a 14.318-MHz Crystal Input to
Generate Multiple Output Frequencies
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
REF0
REF1
V
2.5V
DD
Includes Spread Spectrum Clocking (SSC),
0.34% Downspread for Reduced EMI
Performance
2
APIC2
APIC1
APIC0
GND
3
4
V
V
V
3.3V
XIN
DD
Power Management Control Terminals
5
6
XOUT
GND
V
2.5V
Low Output Skew and Jitter for Clock
Distribution
DD
7
CPU_DIV2(1)
CPU_DIV2(0)
GND
8
PCI_F
PCI1
2.5-V and 3.3-V Supplies
9
Generates the Following Clocks:
– 4 CPU (2.5 V, 100/133 MHz)
– 7 PCI (3.3 V, 33.3 MHz)
– 1 PCI_F (Free Running, 3.3 V, 33.3 MHz)
– 2 CPU/2 (2.5 V, 50/66 MHz)
– 3 APIC (2.5 V, 16.67 MHz)
– 4 3V66 (3.3 V, 66 MHz)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
3.3V
V
2.5V
DD
DD
PCI2
PCI3
GND
PCI4
PCI5
3.3V
CPU3
CPU2
GND
V
2.5V
DD
CPU1
CPU0
GND
– 2 REF (3.3 V, 14.318 MHz)
– 1 48MHz (3.3 V, 48 MHz)
DD
PCI6
PCI7
GND
GND
V
3.3V
DD
Packaged in 56-Pin SSOP Package
GND
Designed for Use with TI’s Direct Rambus
Clock Generators (CDCR81, CDCR82,
CDCR83)
PCI_STOP
CPU_STOP
PWR_DWN
SPREAD
SEL1
3V66(0)
3V66(1)
V
3.3V
DD
description
GND
The CDC925 is a clock synthesizer/driver that
generates system clocks necessary to support
Intel Pentium III systems on CPU, CPU_DIV2,
3V66, PCI, APIC, 48MHz, and REF clock signals.
3V66(2)
3V66(3)
SEL0
V
3.3V
DD
V
3.3V
48MHz
GND
DD
SEL133/100
All output frequencies are generated from a
14.318-MHz crystal input. A reference clock input instead of a crystal can be provided at the XIN input. Two
phase-lockedloops(PLLs)areused, onetogeneratethehostfrequenciesandtheothertogeneratethe48-MHz
clock frequency. On-chip loop filters and internal feedback loops eliminate the need for external components.
The host and PCI clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. All
outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100.
The outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN
terminal, the device operates normally, but when a logical low-level input is applied, the device powers down
completely, with the outputs in a low-level output state. When a high-level is applied to the PCI_STOP or
CPU_STOP, the outputs operate normally. With a low-level applied to the PCI_STOP or CPU_STOP terminals,
the PCI or CPU and 3V66 outputs, respectively, are held in a low-level state.
The CPU bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding
setting for SEL133/100 control input. The PCI bus frequency is fixed to 33MHz.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Intel and Pentium III are trademarks of Intel Corporation.
Direct Rambus and Rambus are trademarks of Rambus Inc.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
description (continued)
Since the CDC925 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL.
This stabilization time is required after power up or after changes to the SEL inputs are made. With use of an
externalreferenceclock, thissignalmustbefixed-frequencyandfixed-phasebeforethestabilizationtimestarts.
function tables
SELECT FUNCTIONS
INPUTS
SEL1
OUTPUTS
FUNCTION
SEL133/
100
PCI,
PCI_F
SEL0
CPU
CPU_DIV2
3V66
48MHz
REF
APIC
L
L
L
L
L
H
L
Hi-Z
N/A
Hi-Z
N/A
Hi-Z
N/A
Hi-Z
N/A
Hi-Z
N/A
Hi-Z
N/A
Hi-Z
N/A
3-state
Reserved
L
H
H
L
100 MHz
100 MHz
TCLK/2
N/A
50 MHz
50 MHz
TCLK/4
N/A
66 MHz
66 MHz
TCLK/4
N/A
33 MHz
33 MHz
TCLK/8
N/A
Hi-Z
14.318 MHz 16.67 MHz 48-MHz PLL off
14.318 MHz 16.67 MHz 48-MHz PLL on
L
H
L
48 MHz
TCLK/2
N/A
H
H
H
H
TCLK
N/A
TCLK/16
N/A
Test
L
H
L
Reserved
H
H
133 MHz
133 MHz
66 MHz
66 MHz
66 MHz
66 MHz
33 MHz
33 MHz
Hi-Z
14.318 MHz 16.67 MHz 48-MHz PLL off
14.318 MHz 16.67 MHz 48-MHz PLL on
H
48 MHz
ENABLE FUNCTIONS
OUTPUTS
INPUTS
CPU_STOP PWR_DWN PCI_STOP
INTERNAL
REF,
CPU
CPU_DIV2 APIC
3V66
PCI
PCI_F
Crystal VCOs
48MHz
X
L
L
X
L
L
L
L
L
L
L
L
L
L
L
Off
On
On
On
On
Off
On
On
On
On
H
H
H
H
On
On
On
On
On
On
On
On
On
On
On
On
On
L
H
L
L
L
On
L
On
H
H
On
On
On
On
On
H
On
On
OUTPUT BUFFER SPECIFICATIONS
V
DD
RANGE
(V)
IMPEDANCE
BUFFER NAME
BUFFER TYPE
(Ω)
CPU, CPU_DIV2, APIC
48MHz, REF
2.375 – 2.625
3.135 – 3.465
3.135 – 3.465
13.5 – 45
20 – 60
12 – 55
TYPE 1
TYPE 3
TYPE 5
PCI, PCI_F, 3V66
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
21, 22, 25, 26
30
3V66 [0–3]
48MHz
O
O
O
O
O
I
3.3 V, Type 5, 66-MHz clock outputs
3.3 V, Type 3, 48-MHz clock output
2.5 V, Type 1, APIC clock outputs
2.5 V, Type 1, CPU clock outputs
APIC [0–2]
CPU [0–3]
CPU_DIV2 [0–1]
CPU_STOP
GND
53, 54, 55
41, 42, 45, 46
49, 50
2.5 V, Type 1, CPU_DIV2 clock outputs
Disables CPU clock to low state
Ground
36
1, 7, 13, 19,
20, 24, 29, 38,
40, 44, 48, 52
PCI [1–7]
9, 11, 12, 14,
O
3.3 V, Type 5, 33-MHz PCI clock outputs
15, 17, 18
PCI_F
8
37
O
I
Free-running 3.3-V, Type 5, 33-MHz PCI clock output
Disables PCI clock to low state
PCI_STOP
PWR_DWN
REF0, REF1
SEL0, SEL1
SEL133/100
SPREAD
35
I
Power down for complete device with outputs forced low
3.3 V, Type 3, 14.318-MHz reference clock output
LVTTL level logic select terminals for function selection
LVTTL level logic select pins for enabling 100/133 MHz
Disables SSC function
2, 3
32, 33
28
O
I
I
34
I
V
DD
3.3V
4, 10, 16, 23,
27, 31, 39
Power for the 3V66, 48MHz, PCI, REF outputs and CORE logic
V
2.5V
43, 47, 51, 56
Power for CPU and APIC outputs
Crystal input – 14.318 MHz
Crystal output – 14.318 MHz
DD
XIN
XOUT
5
6
I
O
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
spread spectrum clock (SSC) implementation for CDC925
Simultaneously switching at fixed frequency generates a significant power peak at the selected frequency,
which in turn will cause EMI disturbance to the environment. The purpose of the internal frequency modulation
of the CPU–PLL allows to distribute the energy to many different frequencies which reduces the power peak.
A typical characteristic for a single frequency spectrum and a frequency modulated spectrum is shown in
Figure 1.
Highest Peak
∆
Non-SSC
SSC
δ of f
nom
f
nom
Figure 1. Frequency Power Spectrum With and Without the Use of SSC
The modulated spectrum has its distribution left hand to the single frequency spectrum which indicates a
“down-spread modulation”.
Thepeakreductiondependsonthemodulationschemeandmodulationprofile. Systemperformanceandtiming
requirements are the limiting factors for actual design implementations. The implementation was driven to keep
the average clock frequency closed to its upper specification limit. The modulation amount was set to
approximately –0.34% (compared to –0.5% on the CDC924).
In order to allow a downstream PLL to follow the frequency modulated signal, the bandwidth of the modulation
signal is limited in order to minimize SSC induced tracking skew jitter. The ideal modulation profile used for
CDC925 is shown in Figure 2.
10.03
10.02
10.01
10
9.99
9.98
9.97
5
10
15
20
25
30
35
40
45
Period of Modulation Signal – µs
Figure 2. SSC Modulation Profile
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
functional block diagram
3–State
28
SEL133/100
48–MHz Inactive
Control
32
SEL0
Test
Logic
33
SEL133/100
SEL1
2*REF
14.318 MHz
(2,3)
1*48MHz
48 MHz
(30)
5
XIN
48 MHz
PLL
Xtal
Oscillator
6
XOUT
/3
/4
4*AGP (3V66)
66 MHz
(21,22,25,26)
STOP
STOP
36
CPU_STOP
4*CPU
100/133 MHz
(41,42,45,46)
2*CPU_DIV2
50/66 MHz
(49,50)
Spread
Logic
CPU
PLL
/2
/2
34
SPREAD
3*APIC
16.67 MHz
(53, 54, 55)
/2
/3
/4
1*PCI_F
33 MHz
(8)
7*PCI
33 MHz
STOP
(9,11,12,14,
15,17,18)
37
35
PCI_STOP
PWR_DOWN
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
DD
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Voltage range applied to any output in the high-impedance state or power-off state,
V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
DD
O
Current into any output in the low state, I
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, I
Operating free-air temperature range, T
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 × I
O
OL
IK
OK
I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0°C to 85°C
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
DISSIPATION RATING TABLE
†
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
POWER RATING
A
A
PACKAGE
POWER RATNG
ABOVE T = 25°C
POWER RATING
A
DL
1558.6 mW
12.468 mW/°C
997.5 mW
810.52 mW
†
This is the inverse of the traditional junction-to-case thermal resistance (R
at 80.2°C/W.
) and uses a board-mounted device
θJA
recommended operating conditions (see Note 2)
†
MIN
3.135
2.375
NOM
MAX
3.465
2.625
UNIT
3.3 V
2.5 V
Supply voltage, V
V
DD
V
0.3 V
+
DD
High-level input voltage, V
IH
2
V
GND –
0.3 V
Low-level input voltage, V
0.8
V
V
IL
Input voltage, V
0
V
DD
I
CPUx, CPU_DIV2x
APICx
–12
–12
–14
–18
12
High-level output current, I
mA
mA
OH
48MHz, REFx
PCIx, PCI_F, 3V66x
CPUx, CPU_DIV2x
APICx
12
Low-level output current, I
OL
‡
48MHz, REFx
PCIx, PCI_F, 3V66x
Test mode
9
12
Reference frequency, f
130
MHz
MHz
°C
(XIN)
§
Crystal frequency, f
(XTAL)
Normal mode
13.8 14.318
0
14.8
85
Operating free-air temperature, T
A
NOTE 2: Unused inputs must be held high or low to prevent them from floating.
†
‡
All nominal values are measured at their respective nominal V
DD
values.
Reference frequency is a test clock driven on the XIN input during the device test mode and normal mode. In test mode, XIN can be driven
externally up to f = 130 MHz. If XIN is driven externally, XOUT is floating.
(XIN)
This is a series fundamental crystal with f = 14.31818 MHz.
§
O
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Input clamp voltage
TEST CONDITIONS
= 3.135 V, I = –18 mA
MIN TYP
MAX
–1.2
350
50
UNIT
V
V
IK
V
DD
V
DD
V
DD
I
R
Input resistance
XIN-XOUT
XOUT
= 3.465 V,
= 3.135 V,
V = V
–0.5 V
–0.5 V
80
kΩ
I
I
DD
DD
V = V
I
20
mA
SEL0, SEL1,
CPU_STOP,
PCI_STOP,
SPREAD
V
DD
= 3.465 V,
V = V
I
<10
10
µA
DD
I
IH
High-level input current
PWR_DWN
SEL133/100
XOUT
V
DD
V
DD
V
DD
= 3.465 V,
= 3.465 V,
= 3.135 V,
V = V
<10
<10
–2
10
10
–5
µA
µA
I
DD
DD
V = V
I
V
O
= 0 V
mA
SEL0, SEL1,
CPU_STOP,
PCI_STOP,
SPREAD
V
= 3.465 V,
V = GND
<10
–10
µA
DD
I
I
I
Low-level input current
IL
PWR_DWN
SEL133/100
V
V
= 3.465 V,
= 3.465 V,
V = GND
I
<10
<10
–10
–10
±10
µA
µA
µA
DD
V = GND
I
DD
High-impedance-state output current
Supply current
|V | = max,
DD
V
O
= V
or GND
OZ
DD
V
= 2.625 V,
PWR_DWN = low,
DD
All outputs = low
<20
<20
100
100
200
V
= 2.625 V,
V
DD
x = 2.5 V,
DD
All outputs = high
µA
I
DD
V
= 3.465 V,
PWR_DWN = low,
All outputs = high
DD
All outputs = low
<50
12
V
DD
V
DD
V
DD
= 3.465 V,
= 2.625 V
= 3.465 V
= 20 pF,
35
1.4
28
mA
mA
I
High-impedance-state supply current
Dynamic supply current
DD(Z)
V
V
= 3.465 V
= 2.625 V
114
52
146
70
C
DD
L
mA
CPU = 133 MHz
DD
C
Input capacitance
V
V
= 3.3 V,
= 3.3 V,
V = V
or GND
3.3
18
5.8
pF
pF
I
DD
I
DD
Crystal terminal capacitance
V = 0.3 V
I
18.5
22.5
DD
†
All typical values are measured at their respective nominal V
DD
values.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
CPUx, CPU_DIV2x, APICx (Type 1)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
VDD –
V
= min to max,
I
= –1 mA
DD
OH
0.1 V
2
V
V
High-level output voltage
V
OH
V
V
V
V
V
V
V
V
V
V
V
V
= 2.375 V,
= min to max,
= 2.375 V,
= 2.375 V,
= 2.5 V,
I
I
I
= –12 mA
= 1 mA
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
OH
OL
OL
0.1
0.4
Low-level output voltage
High-level output current
V
OL
= 12 mA
= 1 V
0.18
–42
–46
–16
57
V
V
V
V
V
V
V
V
V
–26
27
O
O
O
O
O
O
O
I
= 1.25 V
= 2.375 V
= 1.2 V
mA
OH
= 2.625 V,
= 2.375 V,
= 2.5 V,
–27
I
Low-level output current
= 1.25 V
= 0.3 V
63
mA
OL
= 2.625 V,
= 3.3 V,
23
43
8.5
45
C
Output capacitance
Output impedance
= V
or GND
DD
6
13.5
13.5
pF
O
High state
Low state
= 0.5 V
,
,
/I
O OH
27
20
O
O
DD
DD
Z
O
Ω
= 0.5 V
/I
O OL
45
†
All typical values are measured at their respective nominal V
DD
values.
48MHz, REFx (Type 3)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
VDD –
0.1 V
V
= min to max,
I
= –1 mA
DD
OH
V
V
High-level output voltage
V
OH
V
V
V
V
V
V
V
V
V
V
V
V
= 3.135 V,
= min to max,
= 3.135 V,
= 3.135 V,
= 3.3 V,
I
I
I
= –14 mA
= 1 mA
2.4
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
OH
OL
OL
0.1
0.4
Low-level output voltage
High-level output current
V
OL
= 9 mA
0.18
–41
–41
–12
50
V
V
V
V
V
V
V
V
V
= 1 V
–27
29
O
O
O
O
O
O
O
I
= 1.65 V
= 3.135 V
= 1.95 V
= 1.65 V
= 0.4 V
mA
OH
= 3.465 V,
= 3.135 V,
= 3.3 V,
–23
I
Low-level output current
53
mA
OL
= 3.465 V,
= 3.3 V,
20
37
7
C
Output capacitance
Output impedance
= V
or GND
DD
4.5
20
20
pF
O
High state
Low state
= 0.5 V
,
,
/I
O OH
40
31
60
60
O
O
DD
DD
Z
O
Ω
= 0.5 V
/I
O OL
†
All typical values are measured at their respective nominal V
DD
values.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PCIx, PCI_F, 3V66x (Type 5)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
VDD –
V
= min to max,
I
= –1 mA
DD
OH
0.1 V
2.4
V
V
High-level output voltage
V
OH
V
V
V
V
V
V
V
V
V
V
V
V
= 3.135 V,
= min to max,
= 3.135 V,
= 3.135 V,
= 3.3 V,
I
I
I
= –18 mA
= 1 mA
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
OH
OL
OL
0.1
0.4
Low-level output voltage
High-level output current
V
OL
= 12 mA
= 1 V
0.15
–53
–53
–16
67
V
V
V
V
V
V
V
V
V
–33
30
O
O
O
O
O
O
O
I
= 1.65 V
= 3.135 V
= 1.95 V
= 1.65 V
= 0.4 V
mA
OH
= 3.465 V,
= 3.135 V,
= 3.3 V,
–33
I
Low-level output current
70
mA
OL
= 3.465 V,
= 3.3 V,
27
49
7.5
55
C
Output capacitance
Output impedance
= V
or GND
DD
4.5
12
12
pF
O
High state
Low state
= 0.5 V
,
,
/I
O OH
31
24
O
O
DD
DD
Z
O
Ω
= 0.5 V
/I
O OL
55
†
All typical values are measured at their respective nominal V
DD
values.
switching characteristics, V
= 3.135 V to 3.465 V, T = 0°C to 85°C
A
DD
PARAMETER
Overshoot/undershoot
Ring back
TEST CONDITIONS
MIN
GND – 0.7 V
– 0.1 V
TYP
MAX
UNIT
V
V
+ 0.7 V
+ 0.1 V
3
DD
V
V
V
IL
IH
Stabilization time, PWR_DWN to PCIx
Disable time, PWR_DWN to PCIx
Stabilization time, PWR_DWN to CPUx
Disable time, PWR_DWN to CPUx
f
f
f
f
= 133 MHz
= 133 MHz
= 133 MHz
= 133 MHz
0.05
50
ms
ns
(CPU)
(CPU)
(CPU)
(CPU)
t
t
dis3
0.03
50
3
ms
ns
dis4
After SEL1, SEL0
After power up
3
3
†
Stabilization time
ms
†
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for
phaselock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at XIN. Until phase lock is obtained, thespecifications
for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the
time from when V
DD
achieves its nominal operating level until the output frequency is stable and operating within specification.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
switching characteristics, V
= 2.375 V to 2.625 V, T = 0°C to 85°C (continued)
A
DD
CPUx
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
t
t
Output enable time
Output disable time
SEL133/100 CPUx
SEL133/100 CPUx
f
f
f
f
f
f
f
f
= 100 or 133MHz
= 100 or 133MHz
= 100 MHz
6
8
10
10
ns
ns
ns
ns
ps
%
en1
(CPU)
(CPU)
(CPU)
(CPU)
(CPU)
(CPU)
(CPU)
(CPU)
dis1
10 10.04
10.2
7.7
250
55
†
t
c
CPU clock period
= 133 MHz
7.5
7.53
Cycle to cycle jitter
Duty cycle
= 100 or 133MHz
= 100 or 133MHz
= 100 or 133MHz
= 100 or 133MHz
45
t
t
t
t
CPU bus skew
CPU pulse skew
CPUx
CPUn
CPUx
CPUn
50
175
2.2
4
ps
ns
ns
ns
sk(o)
sk(p)
(off)
CPU clock to APIC clock offset, rising edge
CPU clock to 3V66 clock offset, rising edge
1.5
0
2.8
0.75
4.3
3.7
4.3
4
1.5
(off)
f
f
f
f
= 100 MHz
= 133 MHz
2.6
1.4
2.8
1.7
0.4
0.4
(CPU)
(CPU)
(CPU)
(CPU)
t
Pulse duration width, high
Pulse duration width, low
ns
ns
w1
w2
= 100 MHz
t
= 133 MHz
t
t
Rise time
Fall time
V
= 0.4 V to 2.0 V
= 0.4 V to 2.0 V
1.5
1.4
2.2
2
ns
ns
r
O
O
V
f
†
The average over any 1-µs period of time is greater than the minimum specified period.
CPU_DIV2x
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
t
t
Output enable time
Output disable time
SEL133/100 CPU_DIV2x
SEL133/100 CPU_DIV2x
f
f
f
f
f
f
f
f
f
f
f
f
= 100 or 133MHz
= 100 or 133MHz
= 100 MHz
6
8
10
10
ns
ns
ns
ns
ps
%
en1
(CPU)
(CPU)
(CPU)
(CPU)
(CPU)
(CPU)
(CPU)
(CPU)
(CPU)
(CPU)
(CPU)
(CPU)
dis1
20 20.08
15 15.06
20.4
15.3
250
55
†
t
c
CPU_DIV2 clock period
= 133 MHz
Cycle to cycle jitter
Duty cycle
= 100 or 133MHz
= 100 or 133MHz
= 100 or 133MHz
= 100 or 133MHz
= 100 MHz
45
t
t
CPU_DIV2 bus skew
CPU_DIV2 pulse skew
CPU_DIV2x CPU_DIV2x
CPU_DIV2n CPU_DIV2n
50
175
1.6
ps
ns
sk(o)
sk(p)
7.1
4.7
t
Pulse duration width, high
Pulse duration width, low
ns
ns
w1
w2
= 133 MHz
= 100 MHz
7.3
5
8.9
6.6
1.4
1.3
t
= 133 MHz
t
t
Rise time
Fall time
V
= 0.4 V to 2.0 V
= 0.4 V to 2.0 V
0.4
0.4
2
ns
ns
r
O
O
V
1.8
f
†
The average over any 1-µs period of time is greater than the minimum specified period.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
switching characteristics, V
= 2.375 V to 2.625 V, T = 0°C to 85°C (continued)
A
DD
APIC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
t
t
Output enable time
Output disable time
SEL133/100 APICx
SEL133/100 APICx
f
f
f
f
f
f
f
= 16.67 MHz
= 16.67 MHz
= 16.67 MHz
= 100 or 133 MHz
= 16.67 MHz
= 16.67 MHz
= 16.67 MHz
6
8
10
10
ns
ns
ns
ps
%
en1
dis1
c
(APIC)
(APIC)
(APIC)
(CPU)
(APIC)
(APIC)
(APIC)
†
APIC clock period
60 60.24
60.6
400
55
Cycle to cycle jitter
Duty cycle
45
t
t
APIC bus skew
APIC pulse skew
APICx
APICn
APICx
APICn
30
100
3
ps
ns
sk(o)
sk(p)
APIC clock to CPU clock offset,
rising edge
t
APICx
CPUx
–1.5
–4
ns
(off)
t
t
t
t
Pulse duration width, high
Pulse duration width, low
Rise time
f
f
= 16.67 MHz
= 16.67 MHz
25.5
25.3
0.4
28
29.2
1.6
ns
ns
ns
ns
w1
w2
r
(APIC)
(APIC)
V
= 0.4 V to 2 V
2.1
1.7
O
O
Fall time
V
= 0.4 V to 2 V
0.4
1.2
f
†
The average over any 1-µs period of time is greater than the minimum specified period.
switching characteristics, V
= 3.135 V to 3.465 V, T = 0°C to 85°C
A
DD
3V66
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
t
t
Output enable time
Output disable time
SEL133/100 3V66x
SEL133/100 3V66x
f
f
f
f
f
f
f
= 66 MHz
= 66 MHz
6
8
10
10
ns
ns
ns
ps
%
en1
dis1
c
(3V66)
(3V66)
(3V66)
(CPU)
(3V66)
(3V66)
(3V66)
†
3V66 clock period
= 66 MHz
15 15.06
15.3
400
55
Cycle to cycle jitter
Duty cycle
= 100 or 133 MHz
= 66 MHz
45
t
t
t
t
t
t
t
t
3V66 bus skew
3V66 pulse skew
3V66x
3V66n
3V66x
3V66x
3V66n
CPUx
= 66 MHz
50
150
2.6
–1.5
3
ps
ns
ns
ns
ns
ns
ns
ns
sk(o)
sk(p)
(off)
(off)
w1
w2
r
= 66 MHz
3V66 clock to CPU clock offset
0
1.2
5.2
5
–0.75
2.1
3V66 clock to PCI clock offset, rising edge
Pulse duration width, high
Pulse duration width, low
Rise time
f
f
= 66 MHz
= 66 MHz
(3V66)
(3V66)
V
= 0.4 V to 2 V
0.5
0.5
1.5
1.5
2
2
O
O
Fall time
V
= 0.4 V to 2 V
f
†
The average over any 1-µs period of time is greater than the minimum specified period.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
switching characteristics, V
= 3.135 V to 3.465 V, T = 0°C to 85°C (continued)
A
DD
48MHz
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
t
t
Output enable time
Output disable time
48MHz clock period
Cycle to cycle jitter
Duty cycle
SEL133/100 48MHz
SEL133/100 48MHz
f
f
f
f
f
f
f
f
= 48 MHz
= 48 MHz
= 48 MHz
6
8
10
10
ns
ns
ns
ps
%
en1
dis1
c
(48MHz)
(48MHz)
(48MHz)
†
20.5 20.83
21.1
500
55
= 100 or 133 MHz
(CPU)
= 48 MHz
= 48 MHz
45
(48MHz)
(48MHz)
(48MHz)
(48MHz)
t
t
t
t
t
48MHz pulse skew
48MHz
48MHz
3
ns
ns
ns
ns
ns
sk(p)
Pulse duration width, high
Pulse duration width, low
Rise time
= 48 MHz
7.8
7.8
w1
w2
r
= 48 MHz
V
= 0.4 V to 2 V
= 0.4 V to 2 V
1
1
2.1
1.9
2.8
2.8
O
O
Fall time
V
f
†
The average over any 1-µs period of time is greater than the minimum specified period.
REF
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
t
t
Output enable time
Output disable time
SEL133/100 REFx
SEL133/100 REFx
f
f
f
f
f
f
f
f
f
= 14.318 MHz
= 14.318 MHz
= 14.318 MHz
= 100 or 133 MHz
= 14.318 MHz
= 14.318 MHz
= 14.318 MHz
= 14.318 MHz
= 14.318 MHz
= 0.4 V to 2 V
= 0.4 V to 2 V
6
8
10
10
ns
ns
ns
ps
%
en1
dis1
c
(REF)
(REF)
(REF)
(CPU)
(REF)
(REF)
(REF)
(REF)
(REF)
†
REF clock period
69.84
Cycle to cycle jitter
Duty cycle
700
55
45
t
t
t
t
t
t
REF bus skew
REFx
REFn
REFx
REFn
150
250
2
ps
ns
ns
ns
ns
ns
sk(o)
sk(p)
w1
w2
r
REF pulse skew
Pulse duration width, high
Pulse duration width, low
Rise time
26.2
26.2
1
32.7
31.2
2
V
2.8
2.8
O
O
Fall time
V
1
1.9
f
†
The average over any 1-µs period of time is greater than the minimum specified period.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
switching characteristics, V
PCI, PCI_F
= 3.135 V to 3.465 V, T = 0°C to 85°C (continued)
A
DD
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
t
t
Output enable time
Output disable time
SEL133/100 PCIx
SEL133/100 PCIx
f
f
f
f
f
f
f
= 33 MHz
= 33 MHz
= 33 MHz
6
8
10
10
ns
ns
ns
ps
%
en1
dis1
c
(PCI)
(PCI)
(PCI)
(CPU)
†
PCIx clock period
30 30.12
30.5
300
55
Cycle to cycle jitter
Duty cycle
= 100 or 133 MHz
= 33 MHz
= 33 MHz
= 33 MHz
45
(PCI)
(PCI)
(PCI)
t
t
t
t
t
t
t
PCIx bus skew
PCIx pulse skew
PCIx
PCIn
PCIx
PCIn
70
300
4
ps
ns
ns
ns
ns
ns
ns
sk(o)
sk(p)
(off)
w1
w2
r
PCIx clock to 3V66 clock offset
Pulse duration width, high
Pulse duration width, low
Rise time
–1.2
–3
f
f
= 33 MHz
= 33 MHz
12
12
(PCI)
(PCI)
V
V
= 0.4 V to 2 V
= 0.4 V to 2 V
0.5
0.5
1.6
1.5
2
2
O
Fall time
f
O
†
The average over any 1-µs period of time is greater than the minimum specified period.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
PARAMETER MEASUREMENT INFORMATION
R
= 500 Ω
V
L
S1
O_REF
OPEN
From Output
Under Test
TEST
/t
S1
GND
t
t
t
Open
PLH PHL
C
L
R = 500 Ω
L
/t
V
PLZ PZL
/t
O_REF
GND
(see Note A)
PHZ PZH
LOAD CIRCUIT for t and t
pd
sk
t
w
From Output
Under Test
Test
Point
3 V
V
V
V
IH_REF
T_REF
IL_REF
Input
C
L
0 V
(see Note A)
VOLTAGE WAVEFORMS
LOAD CIRCUIT FOR t and t
r
f
Output
Enable
(high-level
enabling)
V
3 V
0 V
DD
Input
V
V
T_REF
V
V
T_REF
T_REF
T_REF
0 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
S1 at 6 V
≈3 V
V
OH
V
V
IH_REF
V
T_REF
Output
V
T_REF
IL_REF
V
+ 0.3 V
OL
(see Note B)
V
V
OL
V
t
OL
t
PZH
t
t
PHZ
r
f
Output
Waveform 2
S1 at GND
OH
t
V
OH
– 0.3 V
w_high
V
T_REF
t
w_low
(see Note B)
≈0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 14.318 MHz, Z = 50 Ω, t ≤ 2.5 ns,
C includes probe and jig capacitance. C = 20 pF (CPUx, APICx, 48MHz, REF), C = 30 pF (PCIx, 3V66)
L L L
O
r
t ≤ 2.5 ns.
f
D. The outputs are measured one at a time with one transition per measurement.
PARAMETER
3.3-V INTERFACE
2.5-V INTERFACE
UNIT
V
V
V
V
High-level reference voltage
2.4
2
V
IH_REF
IL_REF
T_REF
O_REF
Low-level reference voltage
Input Threshold reference voltage
Off-state reference voltage
0.4
1.5
6
0.4
1.25
4.6
V
V
V
Figure 3. Load Circuit and Voltage Waveforms
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
PARAMETER MEASUREMENT INFORMATION
V
T_REF
T_REF
CPUx or PCIx Clock
CPUx or PCIx Clock
t
c
V
t
t
t
(high)
sk(o)
(low)
t
(low or high)
t
t
–t
Duty Cycle
100
sk(p)
PLH PHL
t
c
3V66 or CPUx
V _REF
T
V _REF
T
3V66, PCIx, or APICx
t
t
t
[3V66 to PCIx]
[CPUx to APICx]
[CPUx to 3V66]
(off)
(off)
(off)
Figure 4. Waveforms for Calculation of Skew, Offset, and Jitter
CPU
(internal)
PCI
(internal)
CPU_STOP
PCI_STOP
PWR_DOWN
PCI_F
(external)
CPU
(external)
3V66
(external)
Figure 5. CPU_STOP Timing
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
PARAMETER MEASUREMENT INFORMATION
CPU
(internal)
PCI
(internal)
CPU_STOP
PCI_STOP
PWR_DOWN
PCI_F
(external)
PCI
(external)
Figure 6. PCI_STOP Timing
CPU
(internal)
PCI
(internal)
PWR_DOWN
CPU
(external)
PCI
(external)
VCO
CRYSTAL
NOTE A: Shaded sections on the VCO and Crystal waveforms indicate that the VCO and crystal oscillators are active and there is a valid clock.
Figure 7. Power-Down Timing
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
MECHANICAL DATA
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48-PIN SHOWN
0.025 (0,635)
48
0.012 (0,305)
0.005 (0,13)
M
0.008 (0,203)
25
0.006 (0,15) NOM
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/D 08/97
NOTES: B. All linear dimensions are in inches (millimeters).
C. This drawing is subject to change without notice.
D. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
E. Falls within JEDEC MO-118
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2008
PACKAGING INFORMATION
Orderable Device
CDC925DL
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DL
56
20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
CDC925DLG4
SSOP
DL
56
20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
Logic
Military
Power Mgmt
Microcontrollers
RFID
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2008, Texas Instruments Incorporated
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明