CDC950_技术文档

ꢀ ꢁꢀ ꢂꢃ ꢄ

ꢅ ꢆ ꢆ ꢇꢈꢉ ꢊ ꢁꢋ ꢌꢌ ꢍꢎ ꢍꢏꢐ ꢋꢑ ꢒ ꢀꢒ ꢓ ꢀꢔ ꢕꢖ ꢏꢐ ꢉꢍꢕꢋ ꢗ ꢍꢎꢘ ꢁꢎꢋ ꢙ ꢍ ꢎ ꢌꢓ ꢎ

ꢚꢀ ꢈ ꢓꢐ ꢉꢍ ꢎꢛꢓ ꢑꢎꢁꢕ ꢘꢕ ꢍ ꢎꢙ ꢍꢎ ꢕ

SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

DGG PACKAGE

(TOP VIEW)

D

Generates Clocks for Next Generation

Microprocessors

Uses a 14.318-MHz Crystal Input to

Generate Multiple Output Frequencies

CLK33

3.3V

SEL100/133

GND

1

48

47

46

45

44

43

V

2

DD

Includes Spread Spectrum Clocking (SSC),

0.6% Downspread for Reduced EMI With

Theoretical EMI of 7 dB

3V48/SelA

3V48/SelB

GND

AV 3.3V

3

DD

AGND

4

PWRDWN

5

D

Power Management Control Terminals

V

3.3V

V

3.3V

6

DD

HCLK(0)

GND

7

42 HCLK(4)

41 HCLK(4)

40 GND

Low Output Skew and Jitter for Clock

Distribution

8

9

D

Operates From a Single 3.3-V Supply

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

HCLK(1)

HCLK(5)

D

Generates the Following Clocks:

− 8 Host (Diff Pairs, 100/133 MHz)

− 1 CLK33 (3.3 V, 33.3 MHz)

− 1 REFCLK (3.3 V, 14.318 MHz)

− 2 3V48 (3.3 V, 180° Shifted Pairs, 48 MHz)

V

3.3V

V

3.3V

DD

HCLK(2)

GND

HCLK(6)

GND

D

Packaged in a 48-Pin TSSOP Package

HCLK(3)

HCLK(7)

description

V

3.3V

V

3.3V

DD

REFCLK

SPREAD

GND

MultSel0

MultSel1

GND

The CDC950 is a differential clock synthesizer/

driver that generates HCLK/HCLK, CLK33, 3V48,

and REFCLK system clock signals to support a

computer system with next generation processors

and double data rate (DDR) memory subsystems.

XIN

AGND

I_REF

XOUT

V

3.3V

AV 3.3V

DD

All output frequencies are generated from a

14.318-MHz crystal input. A reference clock input

can be provided at the XIN input instead of a crystal. Two phase-locked loops (PLLs) are used to generate the

host frequencies and the 48-MHz clock frequencies. On-chip loop filters and internal feedback eliminate the

need for external components.

The HCLK, CLK33 clock, and 48-MHz clock outputs provide low-skew/low-jitter clock signals for reliable clock

operation. All outputs have 3-state capability, which can be selected through control inputs SEL100/133,

3V48/SelA, and 3V48/SelB.

The outputs are either differential host clock or 3.3-V single-ended CMOS buffers. With a logic high-level on the

PWRDWN terminal, the device operates normally. When a logical low-level input is applied, the device powers

down completely with the HOST clock at 2 × I

, HOSTB is undriven, CLK33, 3V48, and REFCLK outputs are

in a low-level output state and 3V48B is in a high-level output state.

REF

The host bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with the corresponding

setting for SEL100/133 control input. The CLK33 (PCI) frequency is fixed to 33 MHz.

Since the CDC950 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.

This stabilization time is required following power up, as well as following changes to the SEL inputs. With the

use of an external reference clock, this signal must be fixed-frequency and fixed-phase prior to stabilization time

starts. The CDC950 is characterized for operation from 0°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ꢚ

ꢎ

ꢓ

ꢬ

ꢁ

ꢧ

ꢜ

ꢀ

ꢥ

ꢐ

ꢦ

ꢋ

ꢠ

ꢓ

ꢞ

ꢏ

ꢟ

ꢁ

ꢑ

ꢐ

ꢑ

ꢝ

ꢞ

ꢨ

ꢟ

ꢠ

ꢦ

ꢡ

ꢢ

ꢣ

ꢤ

ꢝ

ꢠ

ꢞ

ꢝ

ꢥ

ꢩ

ꢦ

ꢧ

ꢡ

ꢨ

ꢞ

ꢤ

ꢣ

ꢢ

ꢥ

ꢠ

ꢟ

ꢩ

ꢐꢨ

ꢧ

ꢪ

ꢥ

ꢫ

ꢝ

ꢦ

ꢣ

ꢥ

ꢤ

ꢝ

ꢤ

ꢠ

ꢡ

ꢞ

ꢧ

ꢬ

ꢣ

ꢞ

ꢤ

ꢨ

ꢥ

ꢭ

Copyright  2001 − 2003, Texas Instruments Incorporated

ꢡ

ꢠ

ꢦ

ꢤ

ꢠ

ꢡ

ꢢ

ꢤ

ꢠ

ꢥ

ꢩ

ꢝ

ꢟ

ꢝ

ꢦ

ꢨ

ꢡ

ꢤ

ꢮ

ꢤ

ꢨ

ꢡ

ꢠ

ꢟ

ꢯ

ꢣ

ꢋ

ꢞ

ꢢ

ꢨ

ꢥ

ꢤ

ꢣ

ꢞ

ꢬ

ꢣ

ꢡ

ꢬ

ꢰ

ꢣ

ꢤ ꢨ ꢥ ꢤꢝ ꢞꢲ ꢠꢟ ꢣ ꢫꢫ ꢩꢣ ꢡ ꢣ ꢢ ꢨ ꢤ ꢨ ꢡ ꢥ ꢭ

ꢡ

ꢣ

ꢞ

ꢤ

ꢱ

ꢭ

ꢚ

ꢡ

ꢠ

ꢬ

ꢧ

ꢦ

ꢤ

ꢝ

ꢠ

ꢞ

ꢩ

ꢡ

ꢠ

ꢦ

ꢨ

ꢥ

ꢝ

ꢞ

ꢲ

ꢬ

ꢠ

ꢨ

ꢥ

ꢞ

ꢠ

ꢤ

ꢞ

ꢨ

ꢦ

ꢨ

ꢥ

ꢣ

ꢡ

ꢝ

ꢫ

ꢱ

ꢝ

ꢞ

ꢦ

ꢫ

ꢧ

ꢬ

ꢨ

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀꢂ ꢃ ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢉ

ꢊ

ꢁ

ꢋ

ꢌ

ꢍ

ꢎ

ꢍ

ꢏ

ꢐ

ꢋ

ꢑ

ꢒ

ꢀ

ꢒ

ꢓ

ꢀ

ꢔ

ꢚ ꢀ ꢈ ꢓꢐ ꢉ ꢍꢎ ꢛ ꢓꢑ ꢎꢁ ꢕꢘ ꢕ ꢍ ꢎꢙ ꢍꢎ ꢕ

ꢕ

ꢖ

ꢏ

ꢐꢉ

ꢍ

ꢕ

ꢋ

ꢗ

ꢍ

ꢎ

ꢘ

ꢁ

ꢎ

ꢋ

ꢙ

ꢍ

ꢎ

ꢌ

ꢓ

ꢎ

SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

functional block diagram

3-State/Low

Test

Control

Logic

48

SEL100/133

2

1 REFCLK

14.318 MHz

(19)

3

4

3V48/SelA

3V48/SelB

Latched

1 3V48

48 MHz

(3)

22

23

XIN

48-MHz

PLL

Xtal

Oscillator

180°

Phase

Shift

XOUT

1 3V48B

48 MHz

(4)

/3

1 CLK33

33.3 MHz

(1)

Spread

Logic

CPU

PLL

20

44

/2

SPREAD

/2

PWRDWN

8 HCLKs

30

29

MultSel0

MultSel1

100/133 MHz

Control Logic

(7,10,13,16,

33,36,39,42)

2

8 HCLKs

100/133 MHz

(8,11,14,17

32,35,38,41)

26

I_REF

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀ ꢂꢃ ꢄ

ꢅ ꢆ ꢆ ꢇꢈꢉ ꢊ ꢁꢋ ꢌꢌ ꢍꢎ ꢍꢏꢐ ꢋꢑ ꢒ ꢀꢒ ꢓ ꢀꢔ ꢕꢖ ꢏꢐ ꢉꢍꢕꢋ ꢗ ꢍꢎꢘ ꢁꢎꢋ ꢙ ꢍ ꢎ ꢌꢓ ꢎ

ꢚꢀ ꢈ ꢓꢐ ꢉꢍ ꢎꢛꢓ ꢑꢎꢁꢕ ꢘꢕ ꢍ ꢎꢙ ꢍꢎ ꢕ

SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

Terminal Functions

TERMINAL

NAME

I/O

DESCRIPTION

NO.

3V48/SelA,

3V48/SelB

3, 4

I/O 48-MHz 180° shifted pair clocks for USB use

Logic select pins. Selects the mode of operation, see Table 1 for details.

AGND

27, 45

25, 46

1

P

O

P

Analog ground

AV 3.3V

DD

Power. Analog power supply

CLK33

GND

33-MHz reference clock for PCI use, host clock divided by 3 or by 4

Ground

5, 9, 15,

21, 28, 34,

40, 47

HCLK

I_REF

7, 10, 13,

16, 33, 36,

39, 42

CPU and host clock outputs [7:0]. These eight differential CPU clock pairs run at 100/133 MHz. The V

swing amplitude is configured by MultSel0, MultSel1 pins. See Table 5 and Intel’s CK00 document for

details.

OH

O

8, 11, 14,

17, 32, 35,

38, 41

CPU and host clock outputs [7:0]. These eight differential CPU clock pairs run at 100/133 MHz. The V

OH

swing amplitude is configured by MultSel0, MultSel1 pins. See Table 5 and Intel’s CK00 document for

details.

O

I

26

Current reference. This pin establishes the reference current for host clock parts. See Table 5 and Intel’s

CK00 document for details.

MultSel0

MultSel1

PWRDWN

30

29

44

I

See Table 5 and Intel’s CK00 document for details.

Power-down input. 3.3-V LVTTL compatible, asynchronous input that requests the device to enter the

power-down mode. See Table 2 for details.

REFCLK

19

48

O

I

14.138-MHz reference clock output: 3.3 V copy of the 14.318-MHz reference clock.

SEL100/133

Active low LVTTL level logic select. SEL100/133 is used for enabling 100/133 MHz. Low = 100 MHz, high

= 133 MHz

SPREAD

20

U

P

Spread spectrum enable. 3.3-V LVTTL compatible, input that enables the spread spectrum mode when

held low. See Table 4 for details.

V

DD

3.3V

2, 6, 12,

18, 24, 31,

37, 43

Power. Power supply

XIN

22

I

Crystal connection or an external reference frequency input. Connect to either a 14.138-MHz crystal or

an external reference signal.

XOUT

23

O

Crystal connection. An output connection for an external 14.318-MHz crystal. If using an external

reference, this pin must be left unconnected.

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀꢂ ꢃ ꢄ

ꢅꢆ ꢆꢇꢈ ꢉꢊ ꢁ ꢋ ꢌ ꢌ ꢍꢎꢍ ꢏꢐ ꢋ ꢑꢒ ꢀꢒ ꢓꢀ ꢔ ꢕ ꢖꢏ ꢐꢉ ꢍꢕꢋ ꢗ ꢍꢎꢘ ꢁꢎꢋ ꢙꢍꢎ ꢌ ꢓꢎ

ꢚ ꢀ ꢈ ꢓꢐ ꢉ ꢍꢎ ꢛ ꢓꢑ ꢎꢁ ꢕꢘ ꢕ ꢍ ꢎꢙ ꢍꢎ ꢕ

SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

Function Tables

Table 1. Select Functions

INPUTS

OUTPUTS

FUNCTION

Active 100 MHz

SEL100/133

SelA

SelB

HCLK, HCLK

100 MHz

105 MHz

Hi-Z

CLK33

33 MHz

35 MHz

Hi-Z

3V48, 3V48

48 MHz

L, H

REFCLK

14.318 MHz

Hi-Z

0

1

0

1

0

1

0

1

0

1

0

1

0

1

100 MHz mode; PLL48 powerdown

100 MHz mode 5% overclocking

All 3-state outputs

48 MHz

Hi-Z

133 MHz

127 MHz

133 MHz

TCLK/2

33 MHz

31.7 MHz

33 MHz

TCLK/8

48 MHz

TCLK/2

14.318 MHz

TCLK

Active 133 MHz

133 MHz mode −5% underclocking

Test mode

Test mode (PLL bypass)

Table 2. Enable Functions

INPUT

OUTPUTS

PWRDWN

HCLK

Hi-Z

On

CLK33

L

3V48

L

3V48

H

REFCLK

0

1

2 × I

REF

L

On

Table 3. Output Buffer Specifications

V

DD

RANGE

(V)

IMPEDANCE

BUFFER NAME

BUFFER TYPE

(Ω)

3V48, REFCLK

CLK33

3.135 − 3.465

20−60

12−55

TYPE 3

TYPE 5

TYPE X1

HCLK/HCLK

Table 4. Spread Spectrum Functions

INPUT

OUTPUTS

SPREAD

0

1

Spread spectrum clocking active, −0.6% at HCLK/HCLK, CLK33

Spread spectrum clocking inactive

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀ ꢂꢃ ꢄ

ꢅ ꢆ ꢆ ꢇꢈꢉ ꢊ ꢁꢋ ꢌꢌ ꢍꢎ ꢍꢏꢐ ꢋꢑ ꢒ ꢀꢒ ꢓ ꢀꢔ ꢕꢖ ꢏꢐ ꢉꢍꢕꢋ ꢗ ꢍꢎꢘ ꢁꢎꢋ ꢙ ꢍ ꢎ ꢌꢓ ꢎ

ꢚꢀ ꢈ ꢓꢐ ꢉꢍ ꢎꢛꢓ ꢑꢎꢁꢕ ꢘꢕ ꢍ ꢎꢙ ꢍꢎ ꢕ

SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

Function Tables (Continued)

Table 5. Host/HOST Output Buffer Specifications

INPUT

BOARD TARGET

TRACE/TERM Z

REFERENCE R,

OUTPUT CURRENT

V

OH

at Z

I

= VDD/(3 Rr)

I

OH

MultSel0 MultSel1

REF

0

1

0

1

0

1

0

1

0

1

0

1

60 Ω

50 Ω

Rr = 475 1%,

Rr = 221 1%,

I_REF = 2.32 mA

I_REF = 5 mA

5 × I

6 × I

4 × I

7 × I

5 × I

6 × I

4 × I

7 × I

0.71 V at 60 Ω

0.59 V at 50 Ω

0.85 V at 60 Ω

0.71 V at 50 Ω

0.56 V at 60 Ω

0.47 V at 50 Ω

0.99 V at 60 Ω

0.82 V at 50 Ω

0.75 V at 30 Ω

0.62 V at 25 Ω

0.90 V at 30 Ω

0.75 V at 25 Ω

0.60 V at 30 Ω

0.5 V at 25 Ω

1.05 V at 30 Ω

0.84 V at 25 Ω

REF

60 Ω

50 Ω

60 Ω

50 Ω

60 Ω

50 Ω

30 (dc equivalent)

25 (dc equivalent)

30 (dc equivalent)

25 (dc equivalent)

30 (dc equivalent)

25 (dc equivalent)

30 (dc equivalent)

25 (dc equivalent)

I_REF = 5 mA

NOTE: The entries in boldface are the primary system configurations of interest. The outputs should be optimized for these configurations.

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.3 V

DD

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V

+ 0.5 V

I

DD

Voltage range applied to any output in the high-impedance or power-off state, V

O

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V

Current into any output in the low state, I

+ 0.5 V

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 × rated I

O

OL

Input clamp current, I : (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA

IK

I

(V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

DD

Output clamp current, I : (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA

OK

O

V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

O

DD

Package thermal impedance, θ (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W

JA

Maximum power dissipation at T = 55°C (in still air) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 mW

A

Operating free-air temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0°C to 85°C

A

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for the through-hole packages,

which use a trace length of zero.

3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.

For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data

Book, literature number SCBD002.

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀꢂ ꢃ ꢄ

ꢅꢆ ꢆꢇꢈ ꢉꢊ ꢁ ꢋ ꢌ ꢌ ꢍꢎꢍ ꢏꢐ ꢋ ꢑꢒ ꢀꢒ ꢓꢀ ꢔ ꢕ ꢖꢏ ꢐꢉ ꢍꢕꢋ ꢗ ꢍꢎꢘ ꢁꢎꢋ ꢙꢍꢎ ꢌ ꢓꢎ

ꢚ ꢀ ꢈ ꢓꢐ ꢉ ꢍꢎ ꢛ ꢓꢑ ꢎꢁ ꢕꢘ ꢕ ꢍ ꢎꢙ ꢍꢎ ꢕ

SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

DISSIPATION RATING TABLE

†

T

≤ 25°C

DERATING FACTOR

T

= 70°C

T = 85°C

A

PACKAGE

POWER RATING

ABOVE T = 25°C

POWER RATING POWER RATING

A

DGG

1400 mW

11.2 mW/°C

900 mW

730 mW

†

This is the inverse of the traditional junction-to-case thermal resistance (R

board-mounted device at 89°C/W

) and uses a

θJA

recommended operating conditions (see Note 4)

‡

MIN NOM

MAX

UNIT

Supply voltages, V , AV

DD

3.135

2

3.3

3.465

DD

High-level input voltage, V

IH

V

Low-level input voltage, V

0.8

+ 0.3

−40

−18

−14

0

IL

Input voltage, V

−0.3

V

DD

I

HCLK/HCLK

CLK33

High-level output current, I

OH

3V48/SelA and 3V48/SelB

REFCLK

mA

HCLK/HCLK

CLK33

12

Low-level output current, I

OL

3V48/SelA and 3V48/SelB

REFCLK

9

§

Reference frequency, f

(XIN)

Test mode

14

MHz

¶

Crystal, f

(XTAL)

Normal mode

13.8 14.318

0

14.8

85

Operating free-air temperature, T

°C

A

‡

§

All nominal values are measured at their respective nominal V

DD

values.

Reference frequency is a test clock driven on the XIN input during the device test mode or normal mode. In test mode, XIN can be driven externally

up to f = 16 MHz. If XIN is driven externally, XOUT is floating.

(XIN)

This is a series fundamental crystal with fo = 14.31818 MHz

¶

NOTE 4: Unused inputs must be held high or low to prevent them from floating.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀ ꢂꢃ ꢄ

ꢅ ꢆ ꢆ ꢇꢈꢉ ꢊ ꢁꢋ ꢌꢌ ꢍꢎ ꢍꢏꢐ ꢋꢑ ꢒ ꢀꢒ ꢓ ꢀꢔ ꢕꢖ ꢏꢐ ꢉꢍꢕꢋ ꢗ ꢍꢎꢘ ꢁꢎꢋ ꢙ ꢍ ꢎ ꢌꢓ ꢎ

ꢚꢀ ꢈ ꢓꢐ ꢉꢍ ꢎꢛꢓ ꢑꢎꢁꢕ ꢘꢕ ꢍ ꢎꢙ ꢍꢎ ꢕ

SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

†

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

V

Input clamp voltage

V

= 3.135 V,

I = –18 mA

−1.2

V

IK

DD

I

High-level input

current

All inputs except

SelA, SelB

I

IH

= 3.465 V,

V = V

I DD

5

µA

DD

Low-level input All inputs except

I

IL

V

= 3.465 V,

= 3.465 V

V = GND

I

−5

DD

current

SelA, SelB

3V48/SelA, 3V48/SelB = H,

SEL100/133 = L,

High-impedance

-state output

current

All outputs including

SelA, SelB

I

V

10

25

µA

OZ

V

= V or GND,

O

DD

PWRDWN = H

3V48/SelA, 3V48/SelB = H,

SEL100/133 = L,

PWRDWN = H

‡

I

V

DD

= 3.465 V

19

mA

High-impedance-state supply current

DD(Z)

SelA, SelB = L

= 475 Ω

VDD Supply

43

3.4

47

4.2

mA

DD(PD)

R

(ref)

PWRDWN = L

‡

AI

AVDD Supply

PWRDWN state supply current

DD(PD)

V

R

= 3.465 V,

= 475 Ω,

PWRDWN = H

SSC = ON/OFF

C = MAX

L

100 MHz

133 MHz

173

183

190

200

DD

ref

‡

Dynamic supply current

I

mA

DD(D)

I

O

= 6 x I

ref

100 MHz and SSC off

133 MHz and SSC off

100 MHz and SSC on

133 MHz and SSC on

19

26

24

33

Al

DD

Analog power supply current

V

= 3.465 V

= 3.3 V,

mA

pF

DD

26

33

35

45

§

C

Input capacitance

V = V

I DD

or GND

2

5

I

DD

W

Crystal load capacitance

Effective capacity between C and C

IN OUT

13.5

22.5

(XTAL)

†

‡

All typical values are measured at their respective nominal V

values.

DD

= MAX = 5 pF, RS = 33.2 Ω, Rp = 49.9 Ω at HCLK/HCLK (Type X1)

C

L

= MAX = 20 pF, R = 500 Ω at 48 MHz, REF (Type 3)

= MAX = 30 pF, R = 500 Ω at CLK33 (Type 5)

L

§

¶

These parameters are assured by design and lab characterization, not 100% production tested.

This is the corresponding capacitive load for the XTAL in this oscillator application (Pierce oscillator)

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀꢂ ꢃ ꢄ

ꢅꢆ ꢆꢇꢈ ꢉꢊ ꢁ ꢋ ꢌ ꢌ ꢍꢎꢍ ꢏꢐ ꢋ ꢑꢒ ꢀꢒ ꢓꢀ ꢔ ꢕ ꢖꢏ ꢐꢉ ꢍꢕꢋ ꢗ ꢍꢎꢘ ꢁꢎꢋ ꢙꢍꢎ ꢌ ꢓꢎ

ꢚ ꢀ ꢈ ꢓꢐ ꢉ ꢍꢎ ꢛ ꢓꢑ ꢎꢁ ꢕꢘ ꢕ ꢍ ꢎꢙ ꢍꢎ ꢕ

SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

HCLK/HCLK (Type X1)

†

PARAMETER

Output resistance

Output voltage

TEST CONDITIONS

MIN TYP

MAX

UNIT

Ω

r

3000

o

V

O

1.2

V

−7%

7%

(NOM)

12%

V

= 3.30 V nom

DD

l

(NOM)

I

Output current

All combinations of Table 5, See Note 5

mA

pF

O

−12%

V

= 3.30 V, 5%

= 3.30 V nom

DD

l

(NOM)

C

Output capacitance

V = V

O DD

GND

3.5

O

DD

NOTE 5:

I

is output current (I ) of table 5.

OH

(NOM)

3V48, 3V48REFCLK (Type 3)

†

PARAMETER

TEST CONDITIONS

MIN TYP

– 0.1

DD

MAX UNIT

V

= min to max,

= 3.135 V,

= min to max,

= 3.135 V,

= 3.3 V,

I

= –1 mA

= −14 mA

= 1 mA

V

DD

OH

OL

V

High-level output voltage

Low-level output voltage

OH

V

2.4

V

0.1

OL

= 9 mA

0.18

0.4

V

= 1 V

−29

29

O

= 1.65 V

= 3.135 V

= 1.95 V

= 1.65 V

= 0.4 V

−37

−11

I

High-level output current

OH

= 3.465 V,

= 3.135 V,

= 3.3 V,

−23

mA

39

16

I

Low-level output current

Output capacitance

OL

= 3.465 V,

= 3.3 V,

27

C

= V

DD

or GND

4.5

20

7

60

pF

O

High state

Low state

= 0.5 V

,

/I

O OH

40

O

DD

Z

o

Output impedance

Ω

= 0.5 V

/I

O OL

DD

†

All typical values are measured at their respective nominal V

DD

values.

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀ ꢂꢃ ꢄ

ꢅ ꢆ ꢆ ꢇꢈꢉ ꢊ ꢁꢋ ꢌꢌ ꢍꢎ ꢍꢏꢐ ꢋꢑ ꢒ ꢀꢒ ꢓ ꢀꢔ ꢕꢖ ꢏꢐ ꢉꢍꢕꢋ ꢗ ꢍꢎꢘ ꢁꢎꢋ ꢙ ꢍ ꢎ ꢌꢓ ꢎ

ꢚꢀ ꢈ ꢓꢐ ꢉꢍ ꢎꢛꢓ ꢑꢎꢁꢕ ꢘꢕ ꢍ ꢎꢙ ꢍꢎ ꢕ

SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

CLK33 (Type 5)

†

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

V

= min to max,

= 3.135 V,

= min to max,

= 3.135 V,

= 3.3 V,

I

= –1 mA

= −18 mA

= 1 mA

V

DD

– 0.1

DD

OH

OL

V

High-level output voltage

OH

2.4

V

0.1

0.4

Low-level output voltage

High-level output current

OL

= 12 mA

= 1 V

0.15

V

−33

30

O

= 1.65 V

= 3.135 V

= 1.95 V

= 1.65 V

= 0.4 V

−53

−16

I

OH

= 3.465 V,

= 3.135 V,

= 3.3 V,

−33

mA

51

21

I

Low-level output current

Output capacitance

OL

= 3.465 V,

= 3.3 V,

38

7.5

55

C

= V

DD

or GND

4.5

12

pF

O

High state

Low state

= 0.5 V

,

/I

O OH

35

O

DD

Z

o

Output impedance

Ω

= 0.5 V

/I

O OL

55

DD

†

All typical values are measured at their respective nominal V

DD

values.

switching characteristics, V

= 3.135 V to 3.465 V, T = 0°C to 85°C

A

DD

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

mV

V

†

V

Overshoot

V

OH

+ 200

− 200

(over)

HCLK/HCLK 0.7-V

amplitude

†

Undershoot

V

OL

(under)

(over)

†

Overshoot

Undershoot

GND − 0.7

Other clocks,

†

C

= worst case

V

+ 0.7

10

L

(under)

DD

Output enable time

from low level

SEL100/133 ↑

= 475 Ω

t

All outputs

SEL100/133

PZL

PZH

PHZ

PLZ

R

ref

SEL100/133 ↑

= 475 Ω

Output enable time to

high level

t

10

R

ref

SEL100/133 ↓

= 475 Ω

ns

Output disable time

from high level

R

ref

SEL100/133 ↓

= 475 Ω

Output disable time

from low level

R

ref

V

All outputs

After power up

0.1

ms

DD

PWRDWN

‡

Stabilization time

t

s

From PWRDWN ↑

0.25

†

‡

These parameters are assured by design and lab characterization, not 100% production tested.

Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for

phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at XIN. Until phase lock is obtained, the specifications

for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the

time since V

achieves its nominal operating level (3.3 V) or PWRDWN transition from a low to a high level (2 V) until the output frequency is

stable and operating within specification.

DD

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀꢂ ꢃ ꢄ

ꢅꢆ ꢆꢇꢈ ꢉꢊ ꢁ ꢋ ꢌ ꢌ ꢍꢎꢍ ꢏꢐ ꢋ ꢑꢒ ꢀꢒ ꢓꢀ ꢔ ꢕ ꢖꢏ ꢐꢉ ꢍꢕꢋ ꢗ ꢍꢎꢘ ꢁꢎꢋ ꢙꢍꢎ ꢌ ꢓꢎ

ꢚ ꢀ ꢈ ꢓꢐ ꢉ ꢍꢎ ꢛ ꢓꢑ ꢎꢁ ꢕꢘ ꢕ ꢍ ꢎꢙ ꢍꢎ ꢕ

SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

switching characteristics, V

= 3.135 V to 3.465 V, T = 0°C to 85°C (continued)

A

DD

HCLK/HCLK (Type X1), C = 2 pF, R = 475 Ω, 6 x R

L

ref

PARAMETER

TEST CONDITIONS

MIN

10

TYP

MAX

10.2

7.65

80

UNIT

f

= 100 MHz

= 133 MHz

(HCLK)

‡

HCLK clock period

ns

7.5

(HCLK)

SSC off

SSC on

−80

−110

T

jit(cc)

Cycle-to-cycle jitter

Duty cycle

f

= 100 or 133 MHz

= 100 or 133 MHz,

ps

(HCLK)

110

(HCLK)

t

45%

55%

dc

Crossing point

f

= 100 or 133 MHz,

(HCLK)

Crossing point

HCLK bus skew

70

ps

sk(o)

†

t

Rise time

V

f

= 0.14 V to 0.56 V

175

700

r

O

0.7-V amplitude

ps

V

†

Fall time

f

O

= 100 or 133-MHz

45%

55%

(HCLK)

†

v

Cross point voltages

(cross)

V

OH

V

OH

HCLK and HCLK

†

‡

These parameters are assured by design and lab characterization, not 100% production tested.

The average over any 1-µs period of time is greater than the minimum specified period.

CLK33 (Type 5), C = 30 pF, R = 500 Ω

L

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

30.6

150

55%

2

UNIT

ns

†

f

= 100 or 133 MHz

30 30.06

−150

PCI clock period

(HCLK)

(CLK33)

T

jit(cc)

Cycle-to-cycle jitter

Duty cycle

= 100 or 133 MHz

= 33.3 MHz

ps

t

45%

0.5

(dc)

Rise time

V

= 0.4 V to 2.4 V

r

f

O

ns

Fall time

V

= 0.4 V to 2.4 V

0.5

2

†

The average over any 1-µs period of time is greater than the minimum specified period.

3V48 (Type 3), C = 20 pF, R = 500 Ω

L

PARAMETER

TEST CONDITIONS

= 100 or 133 MHz

MIN

TYP

MAX

UNIT

ns

f

20.83

3V48 clock period

Cycle-to-cycle jitter

Duty cycle

(HCLK)

(3V48)

T

jit(cc)

= 100 or 133 MHz

= 48 MHz

−300

45%

1

300

55%

4

ps

t

dc

Rise time

V

= 0.4 V to 2.4 V

r

f

O

ns

Fall time

V

= 0.4 V to 2.4 V

1

4

REF (Type 3), C = 20 pF, R = 500 Ω

L

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f

= 14.318 MHz

69.84

REF clock period

Cycle-to-cycle jitter

Duty cycle

(REF)

ns

T

= 100 or 133 MHz

−0.5

45%

1

0.5

55%

4

jit(cc)

(HCLK)

t

= 14.318 MHz

= 0.4 V to 2.4 V

(dc)

(REF)

Rise time

V

r

f

O

ns

Fall time

V

1

4

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀ ꢂꢃ ꢄ

ꢅ ꢆ ꢆ ꢇꢈꢉ ꢊ ꢁꢋ ꢌꢌ ꢍꢎ ꢍꢏꢐ ꢋꢑ ꢒ ꢀꢒ ꢓ ꢀꢔ ꢕꢖ ꢏꢐ ꢉꢍꢕꢋ ꢗ ꢍꢎꢘ ꢁꢎꢋ ꢙ ꢍ ꢎ ꢌꢓ ꢎ

ꢚꢀ ꢈ ꢓꢐ ꢉꢍ ꢎꢛꢓ ꢑꢎꢁꢕ ꢘꢕ ꢍ ꢎꢙ ꢍꢎ ꢕ

SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

PARAMETER MEASUREMENT INFORMATION

V

TEST

/t

S1

O(REF)

OPEN

S1

R

= 500 Ω

L

From Output

Under Test

t

Open

PLH PHL

/t

V

PLZ PZL

/t

PHZ PZH

O(REF)

GND

C

R

L

(see Note A)

LOAD CIRCUIT For t and t

pd

sk

t

w

From Output

Under Test

3 V

V

Test Point

IH(REF)

T(REF)

IL(REF)

Input

C

L

0 V

(see Note A)

LOAD CIRCUIT for t and t

VOLTAGE WAVEFORMS

r

f

Output Enable

(High-Level

Enabling)

V

DD

3 V

0 V

Input

V

T(REF)

V

T(REF)

0 V

t

PZL

PLH

PHL

t

Output

Waveform 1

S1 at 6 V

PLZ

≈ 3 V

V

IH(REF)

OH

V

T(REF)

Output

V

T(REF)

IL(REF)

V

OL

+ 0.3 V

− 0.3 V

V

OL

V

OL

(see Note B)

t

f

r

t

PHZ

V

OH

Output

Waveform 2

S1 at GND

PZH

t

w(high)

V

OH

t

w(low)

V

≈ 0 V

T(REF)

(see Note B)

VOLTAGE WAVEFORMS

C includes probe and jig capacitance. C = 2 pF (HCLK, HCLK), C = 20 pF (48 MHz, REF), C = 30 pF (CLK33).

L

NOTES: A.

L

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 14.318 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

O

r

f

D. The outputs are measured one at a time with one transition per measurement.

PARAMETER

3.3-V INTERFACE

UNIT

V

High-level reference voltage

Low-level reference voltage

Input threshold reference voltage

Off-state reference voltage

2.4

0.4

1.5

6

IH(REF)

IL(REF)

T(REF)

O(REF)

V

Figure 1. Load Circuit and Voltage Waveforms

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀꢂ ꢃ ꢄ

ꢅꢆ ꢆꢇꢈ ꢉꢊ ꢁ ꢋ ꢌ ꢌ ꢍꢎꢍ ꢏꢐ ꢋ ꢑꢒ ꢀꢒ ꢓꢀ ꢔ ꢕ ꢖꢏ ꢐꢉ ꢍꢕꢋ ꢗ ꢍꢎꢘ ꢁꢎꢋ ꢙꢍꢎ ꢌ ꢓꢎ

ꢚ ꢀ ꢈ ꢓꢐ ꢉ ꢍꢎ ꢛ ꢓꢑ ꢎꢁ ꢕꢘ ꢕ ꢍ ꢎꢙ ꢍꢎ ꢕ

SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

APPLICATION INFORMATION

V

DD

R

= 33 Ω

(S1)

TLA

HCLK

MultSel0

CDC950

R

= 49.9 Ω

(T1)

MultSel1

R

(S1)

TLB

R

= 475 Ω

R

= 49.9 Ω

(T1)

I(REF)

C

= 2 pF

C = 2 pF

L

C

Represents C

BOARD

and C

jig

L

Z

TLA

= Z = 50 Ω

TLB

Figure 2. Load Circuit for HCLK Bus

spread spectrum clock (SSC) implementation for CDC950

Simultaneously switching at a fixed frequency generates a significant power peak at the selected frequency,

which in turn causes EMI disturbance to the environment. The purpose of the internal frequency modulation of

the CPU-PLL allows energy to be distributed to many different frequencies which reduces the power peak.

A typical characteristic for a single frequency spectrum and a frequency modulated spectrum is shown in

Figure 3.

Maximum Peak

∆

Non-SSC

SSC

δ of f

(nom)

f

(nom)

Figure 3. Frequency Power Spectrum With and Without the Use of SSC

The modulated spectrum has its distribution (left side) associated with the single-frequency spectrum which

indicates a down-spread modulation.

The peak reduction depends on the modulation scheme and modulation profile. System performance and timing

requirements are the limiting factors for actual design implementations. The implementation was driven to keep

the average clock frequency close to its upper specification limit. The modulation amount was set to

approximately –0.6%.

To allow a downstream PLL to follow the frequency modulated signal, the bandwidth of the modulation signal

is limited in order to minimize SSC induced tracking skew jitter. The modulation frequency is approximately

31 kHz.

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀ ꢂꢃ ꢄ

ꢅ ꢆ ꢆ ꢇꢈꢉ ꢊ ꢁꢋ ꢌꢌ ꢍꢎ ꢍꢏꢐ ꢋꢑ ꢒ ꢀꢒ ꢓ ꢀꢔ ꢕꢖ ꢏꢐ ꢉꢍꢕꢋ ꢗ ꢍꢎꢘ ꢁꢎꢋ ꢙ ꢍ ꢎ ꢌꢓ ꢎ

ꢚꢀ ꢈ ꢓꢐ ꢉꢍ ꢎꢛꢓ ꢑꢎꢁꢕ ꢘꢕ ꢍ ꢎꢙ ꢍꢎ ꢕ

SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003

MECHANICAL DATA

DGG (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,27

0,17

M

0,08

0,50

48

25

6,20

6,00

8,30

7,90

0,15 NOM

Gage Plane

0,25

1

24

0°−ā8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

48

56

64

DIM

A MAX

A MIN

12,60

12,40

14,10

13,90

17,10

16,90

4040078/F 12/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

13-Sep-2005

PACKAGING INFORMATION

Orderable Device

CDC950DGG

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TSSOP

DGG

48

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

CDC950DGGG4

CDC950DGGR

CDC950DGGRG4

TSSOP

DGG

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,27

0,17

M

0,08

0,50

48

25

6,20

6,00

8,30

7,90

0,15 NOM

Gage Plane

0,25

1

24

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

48

56

64

DIM

A MAX

12,60

12,40

14,10

13,90

17,10

16,90

A MIN

4040078/F 12/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process

in which TI products or services are used. Information published by TI regarding third-party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for

such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

product or service voids all express and any implied warranties for the associated TI product or service and

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	CDC950
厂家：	TEXAS INSTRUMENTS
描述：	133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS 133 - MHz差分时钟合成器/驱动器，用于PC主板/ SERVERS 驱动器 PC 时钟
文件：	总16页 (文件大小：259K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CDC950 [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E