CDC9841DWR [TI]
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS; PC主板时钟合成器/驱动器，具有三态输出
| 型号： | CDC9841DWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS |
| 文件： | 总9页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC9841
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS458D – DECEMBER 1994 – REVISED APRIL 1996
DW PACKAGE
(TOP VIEW)
Four CPU Clock Outputs With
Programmable Frequency
(50 MHz, 60 MHz, and 66 MHz)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
REF0
REF1
CC
X1
Six Clock Outputs at Half-CPU Frequency
for PCI
2
3
X2
V
CC
One 24-MHz Clock Output
4
GND
OE
PCLK0
PCLK1
CLK12
CLK24
GND
BCLK2
BCLK3
5
One 12-MHz Clock Output
6
Two 14.318-MHz Reference Outputs
7
All Output Clock Frequencies Derived From
a Single 14.31818-MHz Crystal Input
8
V
CC
9
PCLK2
PCLK3
GND
SEL1
SEL0
V
CC
LVTTL-Compatible Inputs and Outputs
10
11
12
13
14
BCLK4
BCLK5
GND
BCLK1
BCLK0
Internal Loop Filters for Phase-Lock Loops
Eliminate the Need for External
Components
Operates at 3.3 V
CC
V
CC
Distributed V
Switching Noise
and Ground Pins Reduce
CC
Packaged in Plastic Small-Outline Package
description
The CDC9841 is a high-performance clock synthesizer/driver that generates all required clock signals
necessary for a high-performance PC motherboard. The four central processing unit (CPU) clock outputs
(PCLKn) are programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1
control inputs. The six peripheral-component-interconnect (PCI) clock outputs (BCLKn) are half the frequency
ofPCLKnandaredelayed1nsto4nsfromtherisingedgeoftheCPUclock. Inaddition, thefourfixed-frequency
outputs provide a 24-MHz clock (CLK24), a 12-MHz clock (CLK12), and two buffered copies of the 14.318-MHz
input reference (REF0, REF1).
The CDC9841 generates all output frequencies from a 14.31818-MHz crystal input. A reference clock can be
provided at X1 instead of a crystal input.
Two phase-lock loops (PLLs) generate the CPU clock frequency and the 24-MHz clock frequency. On-chip loop
filters and internal feedback eliminate the need for external components. The PCI and 12-MHz clock
frequencies are derived from the base CPU and 24-MHz clock frequencies, respectively. The PLL circuit can
be bypassed in the TEST mode (i.e., SEL0 = SEL1 = H) to distribute a test clock provided at the X1 input.
Becausethe CDC9841 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL.
This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal
at the X1 input, as well as following any changes to the SELn inputs.
PCLKn and BCLKn provide low-skew/low-jitter clock signals for reliable clock operation. All outputs are 3 state
and are enabled via OE.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC9841
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS458D – DECEMBER 1994 – REVISED APRIL 1996
FUNCTION TABLE
OE
L
SEL0
SEL1
X1
PCLKn
Hi-Z
BCLKn
Hi-Z
REFn
Hi-Z
CLK24
Hi-Z
CLK12
Hi-Z
X
L
X
L
14.31818 MHz
14.31818 MHz
14.31818 MHz
14.31818 MHz
H
50 MHz
60 MHz
66 MHz
TCLK/2
25 MHz
30 MHz
33 MHz
TCLK/4
14.318 MHz
14.318 MHz
14.318 MHz
TCLK
24 MHz
24 MHz
24 MHz
TCLK/4
12 MHz
12 MHz
12 MHz
TCLK/8
H
L
H
L
H
H
H
†
TCLK
H
H
†
TCLK is a test clock input at the X1 input during test mode.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC9841
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS458D – DECEMBER 1994 – REVISED APRIL 1996
functional block diagram
5
OE
28
REF0
3
X2
OSC
2
27
X1
REF1
24
CLK24
÷2
÷2
25
CLK12
PCLK0
PCLK1
÷2
6
7
24-MHZ
PLL
9
PCLK2
PCLK3
10
CPU CLK
PLL
15
16
÷2
BCLK0
BCLK1
13
SEL0
Select
Logic
22
21
12
BCLK2
BCLK3
SEL1
19
18
BCLK4
BCLK5
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC9841
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS458D – DECEMBER 1994 – REVISED APRIL 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Voltage range applied to any output in the high state or power-off state,
V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
CC
O
Current into any output in the low state, I
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, I
Maximum power dissipation at T = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
I
O
OHmax
IK
OK
I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation,refertothePackageThermalConsiderationsapplicationnoteinthe1994ABTAdvancedBiCMOSTechnology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
MIN
3.135
2
MAX
UNIT
V
CC
V
IH
V
IL
V
I
Supply voltage
3.6
V
V
V
V
High-level input voltage
Low-level input voltage
Input voltage
0.8
0
V
CC
REF0
–12
–8
–6
–12
–4
12
8
REF1
I
High-level output current
PCLKn
mA
OH
OL
BCLKn
CLK24, CLK12
REF0
REF1
I
Low-level output current
PCLKn
6
mA
BCLKn
12
4
CLK24, CLK12
T
A
Operating free-air temperature
0
70
°C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC9841
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS458D – DECEMBER 1994 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN
MAX
UNIT
V
IK
V
= 3.135 V,
–1.2
V
CC
CC
I
I
I
I
I
I
I
I
I
I
I
= –12 mA
= –8 mA
= –6 mA
= –12 mA
= –4 mA
= 12 mA
= 8 mA
REF0
2.5
2.5
2.5
2.5
2.5
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
REF1
PCLKn
V
OH
V
= 3.135 V
V
V
BCLKn
CLK24, CLK12
REF0
0.4
0.4
0.4
0.4
0.4
±1
REF1
= 6 mA
PCLKn
V
OL
V
CC
= 3.135 V
= 12 mA
= 4 mA
BCLKn
CLK24, CLK12
I
I
V
V
= 3.6 V,
= 3.6 V,
V = V
or GND
µA
µA
I
CC
I
CC
= V or GND
CC
V
O
±10
50
OZ
CC
CC
†
Outputs enabled
V
CC
= 3.6 V,
I
O
= 0,
I
mA
V = V
or GND
Outputs disabled
1
I
CC
CC
C
C
C
V = V
I
or GND
pF
pF
pF
i
V
O
= V
or GND
o
CC
V = 3 V or 0
I
pd
†
Device in normal operating mode with no load on outputs
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
After SEL1, SEL0
After OE↑
5
5
5
‡
Stabilization time
ms
After power up
‡
TimerequiredfortheintegratedPLLcircuittoobtainphaselockofitsfeedbacksignaltoitsreferencesignal. Inorderforphaselocktobeobtained,
a fixed-frequency, fixed-phase reference signal must be present at X1. Until phase lock is obtained, the specifications for propagation delay and
skew parameters given in the switching characteristics table are not applicable.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC9841
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS458D – DECEMBER 1994 – REVISED APRIL 1996
switching characteristics (see Figures 1 and 2)
V
= 3.135 V
to 3.6 V,
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
T
A
= 0°C to 70°C
MIN
MAX
200
400
4
PCLKn (C = 20 pF)
L
†
ps
ns
ps
t
skew
BCLKn (C = 30 pF)
L
†
Offset
BCLKn (C = 30 pF)
L
1
PCLKn (C = 20 pF)
L
PCLKn (C = 20 pF)
±250
±350
55%
L
†
Jitter
BCLKn (C = 30 pF)
L
†
Duty cycle
45%
20
Any output
SEL0 = L, SEL1 = L
16.7
15
PCLKn (C = 20 pF)
SEL0 = L, SEL1 = H
SEL0 = H, SEL1 = L
SEL0 = L, SEL1 = L
SEL0 = L, SEL1 = H
SEL0 = H, SEL1 = L
L
ns
t
c
40
33.3
30
BCLKn (C = 30 pF)
L
†‡
PCLKn (C = 20 pF), BCLKn (C = 30 pF)
2
2
ns
ns
t
t
L
L
r
†‡
PCLKn (C = 20 pF), BCLKn (C = 30 pF)
f
L
L
†
‡
Specifications are applicable only after the PLL stabilization time has elapsed.
Rise and fall times are characterized using the load circuits shown in Figure 1.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC9841
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS458D – DECEMBER 1994 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
CLOCK DRIVER CIRCUITS
t
c
From Output
Under Test
Duty Cycle
C
L
500 Ω
(see Note A)
2.4 V
1.5 V
0.4 V
LOAD CIRCUIT
t
t
f
r
VOLTAGE WAVEFORMS
NOTES: A.
C includes probe and jig capacitance.
L
B. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
V
OH
1.5 V
CPU Clock
GND
(PCLK)
V
OH
1.5 V
CPU Clock
(PCLK)
GND
skew
skew
offset
PCLK-to-PCLK Skew
V
OH
1.5 V
PCI Clock
(BCLK)
GND
V
OH
1.5 V
PCI Clock
(BCLK)
GND
BCLK-to-BCLK Skew
V
OH
1.5 V
CPU Clock
(PCLK)
GND
V
OH
1.5 V
PCI Clock
(BCLK)
GND
offset
PCLK-to-BCLK Offset
Figure 2. Waveforms for Calculation of t
and Offset
skew
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
SOIC
Drawing
CDC9841DW
OBSOLETE
OBSOLETE
DW
28
28
TBD
TBD
Call TI
Call TI
Call TI
Call TI
CDC9841DWR
DW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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