CDCDB2000 [TI]
符合 DB2000QL 标准、适用于第 1 代到第 5 代 PCIe® 的 20 路输出时钟缓冲器;
| 型号： | CDCDB2000 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 符合 DB2000QL 标准、适用于第 1 代到第 5 代 PCIe® 的 20 路输出时钟缓冲器 时钟 PC |
| 文件： | 总39页 (文件大小：1504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
CDCDB2000
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
符合 CDCDB2000 DB2000QL 标准的 20 输出时钟缓冲器，适用于 PCIe
第 1 代到第 5 代
1 特性
2 应用
1
•
•
•
具有集成 85Ω 输出终端的 20 LP-HCSL 输出
•
•
•
•
微服务器和塔式服务器
8 硬件输出使能端 (OE#) 控制装置
使用 DB2000QL 滤波器之后的附加相位抖动：
< 0.08ps rms
存储区域网络和主机总线适配器卡
网络附加存储
硬件加速器
•
支持 PCIe 第 4 代和第 5 代常见时钟 (CC) 频率和
单独基准 (IR) 架构
3 说明
–
与扩频兼容
CDCDB2000 是一款符合 DB2000QL 标准的 20 输出
LP-HCSL 时钟缓冲器，能够为 PCIe 第 1 代到第 5
代、QuickPath Interconnect (QPI)、UPI、SAS 和
SATA 接口分配参考时钟。使用 SMBus、SBI 和 8 输
出使能引脚，可以单独配置和控制所有 20 个输出。
CDCDB2000 是一个 DB2000QL 衍生缓冲器，达到或
超过 DB2000QL 规格中的系统参数。CDCDB2000 采
用具有 80 个引线的 6mm × 6mm TLGA/GQFN 封
装。
•
•
•
•
•
•
•
•
•
周期到周期抖动：< 50ps
输出到输出偏斜：< 50ps
输入到输出延迟：< 3ns
3.3V 内核和 IO 电源电压
硬件控制的低功耗模式 (PD#)
用于在 PD# 模式下进行输出控制的边带接口 (SBI)
9 个可选 SMBus 地址
功耗：< 600mW
6mm × 6mm，80 引脚 TLGA/GQFN 封装
器件信息(1)
器件型号
封装
TLGA (80)
封装尺寸（标称值）
CDCDB2000
6.00mm × 6.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
CDCDB2000 系统图
PCIe Device
PCIe Gen 4-5
Clock
Generator
20
LP-HCSL
CDCDB2000
20x LP-HSCL Output Buffer
LP-HCSL
OE#
Control
SMBus
Control
Side-Band
Interface
Control Interface
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNAS787
CDCDB2000
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
目录
7.5 Programming .......................................................... 15
7.6 Register Maps ........................................................ 18
Application and Implementation ........................ 24
8.1 Application Information............................................ 24
8.2 Typical Application ................................................. 24
Power Supply Recommendations...................... 26
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 7
6.1 Absolute Maximum Ratings ...................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information.................................................. 7
6.5 Electrical Characteristics........................................... 7
6.6 Timing Requirements................................................ 9
6.7 Typical Characteristics............................................ 12
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 14
8
9
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Examples................................................... 27
11 器件和文档支持 ..................................................... 30
11.1 器件支持 ............................................................... 30
11.2 接收文档更新通知 ................................................. 30
11.3 支持资源................................................................ 30
11.4 商标....................................................................... 30
11.5 静电放电警告......................................................... 30
11.6 Glossary................................................................ 30
12 机械、封装和可订购信息....................................... 30
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (November 2019) to Revision A
Page
•
Changed maximum input voltage from:VDD+ 0.3 V to: VDD+ 0.5 V .................................................................................... 7
2
Copyright © 2019–2020, Texas Instruments Incorporated
CDCDB2000
www.ti.com.cn
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
5 Pin Configuration and Functions
CDCDB2000 NPP Package
80-Pin TLGA
Top View
1
2
3
4
5
6
7
8
9
10
11
12
CK17 CK16 CK16 CK15 CK15 CK14 CK14 CK13 CK13 CK12 CK12 CK11
_P
A
B
C
D
E
F
A
B
C
D
E
F
_P
_N
_P
_N
_P
_N
_P
_N
_N
_P
_N
CK17
_N
SADR
0
SADR
1
CK11
_P
VDD
NC
NC
VDD
NC
OE12# VDD
OE11#
NC
CK18
_P
CK10
_N
NC
NC
CK10
_P
CK18
_N
NC
OE10#
SHFT OE9#
_LD#
CK19
_P
SBEN
NC
CK9
CK19
_N
NC
_N
DAP = GND
CLKIN
_P
CK9
G
H
J
NC
NC
_P
G
H
J
CLKIN VDD
_A
CK8
OE8#
_N
_N
CK0
_P
CK8
NC
NC
_P
CK0
_N
CK7
OE7#
K
L
NC
K
L
_N
CK1
_P
SMB
DAT
SMB
CLK
OE5#
DATA
OE6#
CLK
CK7
VDD
NC
NC
NC
VDD
_P
NC
CKPW
RGD
_PD#
CK1
_N
CK2
_P
CK2
_N
CK3
_P
CK3
_N
CK4
_P
CK4
_N
CK5
_P
CK5
_N
CK6
_P
CK6
_N
M
M
1
2
3
4
5
6
7
8
9
10
11
12
Pin Functions
PIN
I/O TYPE
DESCRIPTION
NAME
INPUT CLOCK
CLKIN_P
NO.
G1
H1
I
I
LP-HCSL differential clock input. Typically connected directly to the differential
output of clock source.
CLKIN_N
OUTPUT CLOCKS
CK0_P
J1
K1
L1
O
O
O
O
O
O
O
O
O
O
LP-HCSL differential clock output of channel 0. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
CK0_N
CK1_P
LP-HCSL differential clock output of channel 1. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
CK1_N
M1
M2
M3
M4
M5
M7
M8
CK2_P
LP-HCSL differential clock output of channel 2. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
CK2_N
CK3_P
LP-HCSL differential clock output of channel 3. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
CK3_N
CK4_P
LP-HCSL differential clock output of channel 4. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
CK4_N
Copyright © 2019–2020, Texas Instruments Incorporated
3
CDCDB2000
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
Pin Functions (continued)
PIN
I/O TYPE
DESCRIPTION
NAME
CK5_P
NO.
M9
O
O
LP-HCSL differential clock output of channel 5. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect, and pin L8
(OE5# / DATA) is recommended to be either in DATA mode or pulled high.
CK5_N
M10
CK6_P
CK6_N
M11
M12
O
O
LP-HCSL differential clock output of channel 6. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect, and pin L10
(OE6# / CLK) is recommended to be either in CLK mode or pulled high.
CK7_P
CK7_N
L12
K12
O
O
LP-HCSL differential clock output of channel 7. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect, and pin
K11 (OE7#) is recommended to be pulled high to disable channel 7 output.
CK8_P
CK8_N
J12
O
O
LP-HCSL differential clock output of channel 8. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect, and pin
H11 (OE8#) is recommended to be pulled high to disable channel 8 output.
H12
CK9_P
CK9_N
G12
F12
O
O
LP-HCSL differential clock output of channel 9. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect, and pin
E12 (OE9#) is recommended to be pulled high to disable channel 9 output.
CK10_P
CK10_N
D12
C12
O
O
LP-HCSL differential clock output of channel 10. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect, and pin
E11 (OE10# / SHFT_LD#) is recommended to be either in SHFT_LD# mode or
pulled high.
CK11_P
CK11_N
B12
A12
O
O
LP-HCSL differential clock output of channel 11. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect, and pin
C11 (OE11#) is recommended to be pulled high to disable channel 11 output.
CK12_P
CK12_N
A11
A10
O
O
LP-HCSL differential clock output of channel 12. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect, and pin
B10 (OE12#) is recommended to be pulled high to disable channel 12 output.
CK13_P
CK13_N
CK14_P
CK14_N
CK15_P
CK15_N
CK16_P
CK16_N
CK17_P
CK17_N
CK18_P
CK18_N
CK19_P
CK19_N
A9
A8
A7
A6
A5
A4
A3
A2
A1
B1
C1
D1
E1
F1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
LP-HCSL differential clock output of channel 13. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
LP-HCSL differential clock output of channel 14. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
LP-HCSL differential clock output of channel 15. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
LP-HCSL differential clock output of channel 16. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
LP-HCSL differential clock output of channel 17. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
LP-HCSL differential clock output of channel 18. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
LP-HCSL differential clock output of channel 19. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
MANAGEMENT AND CONTROL
Clock Power Good and Power Down multi-function input pin with internal 120-kΩ
pulldown. Typically connected to GPIO of microcontroller. If unused, the pin can be
left no connect.
On first high transition, PWRGD samples the latched SADR[1:0] inputs and starts
up device. After PWRGD has been asserted high for the first time, the pin
becomes a PD# pin and it controls power-down mode:
LOW: Power-down mode, all output channels tri-stated.
HIGH: Normal operation mode.
CKPWRGD_PD#
M6
I, PD
Output enable for channel 5 and Side-Band Interface data multi-function pin with
internal 120-kΩ pulldown. Typically connected to GPIO of microcontroller. If both
modes are unused, the pin can be left no connect.
OE5#
DATA
L8
I, PD
When pin E2 = LOW, OE5# mode. Output enable for channel 5, active low.
LOW: enable output channel 5.
HIGH: disable output channel 5.
When pin E2 = HIGH, DATA mode. Side-Band Interface data pin.
4
Copyright © 2019–2020, Texas Instruments Incorporated
CDCDB2000
www.ti.com.cn
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
Pin Functions (continued)
PIN
I/O TYPE
DESCRIPTION
NAME
NO.
Output enable for channel 6 and Side-Band Interface clock multi-function pin with
internal 120-kΩ pulldown. Typically connected to GPIO of microcontroller. If both
modes are unused, the pin can be left no connect.
OE6#
CLK
L10
I, PD
When pin E2 = LOW, OE6# mode. Output Enable for channel 6, active low.
LOW: enable output channel 6.
HIGH: disable output channel 6.
When pin E2 = HIGH, CLK mode. Side-Band interface clock pin.
Output Enable for channel 7 with internal 120-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 7.
OE7#
OE8#
OE9#
K11
H11
E12
I, PD
I, PD
I, PD
HIGH: disable output channel 7.
Output Enable for channel 8, with internal 120-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 8.
HIGH: disable output channel 8.
Output Enable for channel 9, with internal 120-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 9.
HIGH: disable output channel 9.
Output enable for channel 10 and Side-Band Interface load shift registers multi-
function pin with internal 120-kΩ pulldown. Typically connected to GPIO of
microcontroller. If both modes are unused, the pin can be left no connect.
When pin E2 = LOW, OE10# mode. Output Enable for channel 10, active low.
LOW: enable output channel 10.
HIGH: disable output channel 10.
OE10#
SHFT_LD#
E11
I, PD
When pin E2 = HIGH, SHFT_LD# mode. Side-Band Interface load shift registers
pin.
LOW: disable Side-Band Interface shift register.
HIGH: enable Side-Band Interface shift register.
A falling edge transfers the Side-Band shift register contents to the output register.
Output Enable for channel 11 with internal 120-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 11.
OE11#
OE12#
C11
B10
I, PD
I, PD
HIGH: disable output channel 11.
Output Enable for channel 12 with internal 120-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 12.
HIGH: disable output channel 12.
Side-Band Interface enable input with internal 120-kΩ pulldown. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
This pin disables the Output Enable (OE#) pins when asserted.
LOW: OE# pins and SMBus enable bits control outputs, Side-Band interface
disabled.
SBEN
E2
I, S, PD
HIGH: Side-Band Interface controls outputs, OE# pins and SMBus enable bits are
disabled.
SMBUS AND SMBUS ADDRESS
SMBus address strap bit[0]. This is a 3-level input that is decoded in conjunction
with pin B8 to set SMBus address. It has internal 120-kΩ pullup / pulldown network
biasing to VDD/2 when no connect.
For a high-level input configuration, the pin should be pulled up to 3.3-V VDD
through an external pullup resistor from 1k to 5k with 5% tolerance.
For a low-level input configuration input, the pin should be pulled down to ground
through an external pulldown resistor from 1k to 5k with 5% tolerance.
For a mid-level input configuration, the pin should be left floating and not
connected to VDD or ground.
I, S, PU /
PD
SADR0
B4
Copyright © 2019–2020, Texas Instruments Incorporated
5
CDCDB2000
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
Pin Functions (continued)
PIN
I/O TYPE
DESCRIPTION
NAME
NO.
SMBus address strap bit[1]. This is a 3-level input that is decoded in conjunction
with pin B4 to set SMBus address. It has internal 120-kΩ pullup / pulldown network
biasing to VDD/2 when no connect.
For a high-level input configuration, the pin should be pulled up to 3.3-V VDD
through an external pullup resistor from 1k to 5k with 5% tolerance.
For a low-level input configuration, the pin should be pulled down to ground
through an external pulldown resistor from 1k to 5k with 5% tolerance.
For a mid-level input configuration, the pin should be left floating and not
connected to VDD or ground.
I, S, PU /
PD
SADR1
B8
Clock pin of SMBus interface. Typically pulled up to 3.3-V VDD using external
pullup resistor. The recommended pullup resistor value is > 8.5k.
SMBCLK
SMBDAT
L5
L4
I
Data pin of SMBus interface. Typically pulled up to 3.3-V VDD using external
pullup resistor. The recommended pullup resistor value is > 8.5k.
I / O
SUPPLY VOLTAGE AND GROUND
GND
DAP
G
P
Ground. Connect ground pad to system ground.
Power supply input for LP-HCSL clock output channels. Connect to 3.3-V power
supply rail with decoupling capacitor to GND. Place a 0.1-µF capacitor close to
each supply pin between power supply and ground.
B2, B6, B11, L2,
L11
VDD
Power supply input for differential input clock. Connect to 3.3-V power supply rail
with decoupling capacitor to GND. Place a 0.1-µF capacitor close to pin.
VDD_A
H2
P
NO CONNECT
B3, B5, B7, B9,
C2, D2, D11, F2,
F11, G2, G11, J2,
J11, K2, L3, L6,
L7, L9,
NC
—
Do not connect to GND or VDD.
The “#” symbol at the end of a pin name indicates that the active state occurs when the signal is at a low voltage
level. When “#” is not present, the signal is active high.
The definitions below define the I/O type for each pin.
•
•
•
•
•
•
•
•
I = Input
O = Output
I / O = Input / Output
PU / PD = Internal 120-kΩ Pullup / Pulldown network biasing to VDD/2
PD = Internal 120-kΩ Pulldown
S = Hardware Configuration Pin
P = Power Supply
G = Ground
6
版权 © 2019–2020, Texas Instruments Incorporated
CDCDB2000
www.ti.com.cn
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
GND
MAX
3.6
UNIT
V
VDD, VDD_A
Power supply voltage
IO input voltage
VIN
TJ
VDD + 0.5
125
V
Junction temperature
Storage temperature
°C
°C
Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001, all pins(1)
±3000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
3.135
3.135
–40
NOM
3.3
MAX
3.465
3.465
85
UNIT
V
VDD
VDD_A
TA
IO supply voltage
Core supply voltage
Ambient temperature
Junction temperature
3.3
V
°C
°C
TJ
125
6.4 Thermal Information
CDCDB2000
THERMAL METRIC(1)
NPP (GQFN)
80 PINS
32.7
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
31.2
15.9
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ΨJB
15.8
RθJC(bot)
1.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
VDD, VDD_A = 3.3 V ± 5 %, -40 °C < TA < 85 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise
noted)
PARAMETER
CURRENT CONSUMPTION
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Active mode. CKPWRGD_PD# = 1
12
8
IDD_A
Core supply current
mA
Power down mode. CKPWRGD_PD# = 0
Copyright © 2019–2020, Texas Instruments Incorporated
7
CDCDB2000
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
Electrical Characteristics (continued)
VDD, VDD_A = 3.3 V ± 5 %, -40 °C < TA < 85 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
All-outputs disabled
MIN
TYP
20
MAX
UNIT
IDD
IO supply current per output
All-outputs active, 100MHz
200
8
mA
Power down mode. CKPWRGD_PD# = 0
CLOCK INPUT
fIN
Input frequency
50
200
0.7
100
250
MHz
Differential voltage between CLKIN_P and
CLKIN_N(1)
mVDiff-
peak
VIN
Input voltage swing
2300
dV/dt
Input voltage edge rate
Total variation of VCROSS
Input duty cycle
20% - 80% of input swing
V/ns
DVCROSS
DCIN
Total variation across VCROSS
140
2.2
mV
%
40
60
Differential capacitance between CLKIN_P
and CLKIN_N pins
CIN
Input capacitance(2)
pF
CLOCK OUTPUT
fOUT
Output frequency
50
100
2.2
250
MHz
pF
Differential capacitance between CKx_P
and CKx_N pins
COUT
Output capacitance(1)
VOH
Output high voltage
Output low voltage
Crossing point voltage
225
10
270
150
200
Single-ended(2)(3)
VOL
(3)(4)
VCROSS
Input VCROSS varied by 140 mV.
130
mV
Input VCROSS varied by 140 mV. Variation
of VCROSS
DVCROSS
Total variation of VCROSS
35
(3)(4)
(3)
Vovs
Vuds
ZDIFF
Overshoot voltage
Undershoot voltage
Differential impedance
VOH+75
VOL–75
89
(3)
Measured at VOL/VOH
Measured at VCROSS
81
68
2
85
85
ohm
ZDIFF_CROS
S
Differential impedance
102
tEDGE
Edge rate
Measured at VCROSS
Measured at VCROSS
Measured
20
20
V/ns
%
DtEDGE
Edge rate matching
CKPWRGD_PD# pin
transistions from 0 to 1, fIN
100 MHz
when
Power good assertion to stable clock
output
tSTABLE
=
PWRGD
reaches
0.2V
1.8
ms
µs
Measured
when
PWRGD
reaches
0.2V
CKPWRGD_PD# pin
transistions from 0 to 1, fIN
100 MHz
Power good assertion to outputs
driven high
tDRIVE_PD#
=
300
Output enable assertion to stable
clock output
tOE
tOD
tPD
OEx# pin transistions from 1 to 0
OEx# pin transistions from 0 to 1
10
10
3
Output enable de-assertion to no
clock output
CLKIN
Periods
Power down assertion to no clock
output
CKPWRGD_PD# pin transistions from 1 to
0
tDCD
tDLY
Duty cycle distortion
Propagation delay
Differential; fIN = 100MHz, fin_DC = 50%
–1.0
(5)0.5
1.0
3
%
ns
(1) Voltage swing includes overshoot.
(2) Not tested in production. Ensured by design and characterization.
(3) Measured into DC test load.
(4) VCROSS is single-ended voltage when CKx_P = CKx_N with respect to system ground. Only valid on rising edge of CKx, when CKx_P is
rising.
(5) Measured from rising edge of CLK_IN to any CKx output.
8
Copyright © 2019–2020, Texas Instruments Incorporated
CDCDB2000
www.ti.com.cn
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
Electrical Characteristics (continued)
VDD, VDD_A = 3.3 V ± 5 %, -40 °C < TA < 85 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise
noted)
PARAMETER
Skew between outputs
Additive jitter
TEST CONDITIONS
MIN
TYP
MAX
(6)50
UNIT
tSKEW
ps
DB2000QL filter
0.08 ps, rms
0.03 ps, rms
Additive jitter for PCIe5
PCIe5.0 filter
Input clock
slew rate
≥ 1.8 V/ns
Additive jitter for PCIe4
Additive jitter for PCIe3
0.08 ps, rms
JCKx_PCIE
PLL BW = 2 - 5 MHz; CDR =
10 MHz
Input clock
slew rate
≥ 0.6 V/ns
0.15 ps, rms
0.2 ps, rms
JCKx_PCIE
JCKx_PCIE
Additive jitter for PCIe2
Additive jitter for PCIe1
PCIe2 filter
PCIe1 filter
5
ps, rms
fIN = 100 MHz; slew rate ≥ 3 V/ns; 12 kHz
to 20 MHz integration bandwidth.
JCKx
Additive jitter
155
fs, rms
SMBUS INTERFACE, SIDE-BAND INTERFACE, OEx#, CKPWRGD_PD#, SBEN
VIH
VIL
High-level input voltage
Low-level input voltage
2.0
V
0.8
30
With internal pull up/pull-down
–30
–5
GND < VIN
< VDD
IIL
Input leakage current
uA
Without internal pull up/pull-
down
5
CIN
Input capacitance
Output capacitance
4.5
4.5
pF
pF
COUT
3-LEVEL DIGITAL INTERFACE (SA_0, SA_1)
VIHT
VIMT
VILT
IINT
High-level input voltage
Mid level input voltage
Low-level input voltage
Input high current
2.4
1.3
VDD/2
1.8
0.9
10
V
VIN = VDD, VIN = GND
-10
uA
GND < VIN
< VDD
ILeak
Input leakage current
With internal pull up/pull-down
–30
30
(6) Measured from rising edge of any CKx output to any other CKx output.
6.6 Timing Requirements
VDD, VDD_A = 3.3 V ± 5 %, -40 °C < TA < 85 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise
noted)
MIN
NOM
MAX
UNIT
SMBUS-COMPATIBLE INTERFACE TIMING
fSMB
SMBus operating frequency
10
100
kHz
Bus free time between STOP and
START
tBUF
4.7
tHD_STA
tSU_STA
tSU_STO
tHD_DAT
tSU_DAT
START condition hold time
START condition setup time
STOP condition setup time
SMBDAT hold time
4
4.7
4
µs
300
250
25
ns
ms
µs
SMBDAT setup time
tTIMEOUT Detect SMBCLK low timeout
35
tLOW
SMBCLK low period
4.7
4
tHIGH
SMBCLK high period
50
25
tLOW_SL
Cumulative clock low extend time
ms
Copyright © 2019–2020, Texas Instruments Incorporated
9
CDCDB2000
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
Timing Requirements (continued)
VDD, VDD_A = 3.3 V ± 5 %, -40 °C < TA < 85 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise
noted)
MIN
NOM
MAX
300
UNIT
tF
SMBCLK/SMBDAT fall time(1)
SMBCLK/SMBDAT rise time(2)
ns
tR
1000
SIDE-BAND INTERFACE TIMING
tPERIOD
tSETUP
tDSU
Clock period
40
25
10
5
Setup time to clock
Data set up time
Data hold time
Delay time
ns
tDHOLD
tDELAY
25
CLK
periods
tPDLY
tSLEW
Propagation delay
Clock slew rate
4
10
3
20% - 80%
0.2
V/ns
(1) TF = (VIHMIN + 0.15) to (VILMAX - 0.15)
(2) TR = (VILMAX - 0.15) to (VIHMIN + 0.15)
VDD/VDD_A
CKPWRGD_PD#
CLKIN
ttSTABLE
t
ttPD
t
CKx_P
tDRIVE_PD#
CKx_N
图 1. Start-Up With CLKIN Timing Diagram
10
版权 © 2019–2020, Texas Instruments Incorporated
CDCDB2000
www.ti.com.cn
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
VDD/VDD_A
CKPWRGD_PD#
CLKIN
ttSTABLE
t
CKx_P
CKx_N
tDRIVE_PD#
图 2. Start-Up Without CLKIN Timing Diagram
tLOW
tR
tF
VIH
SMBCLK
VIL
tHD_STA
tHIGH
tSU_STA
tSU_STO
ttBUFt
tHD_DAT
tSU_DAT
VIH
SMBDAT
VIL
P
S
S
P
图 3. SMBus Timing Diagram
ttPERIOD
t
CLK
tDSU
tDHOLD
D1
DATA
D0
D19
tSETUP
tDELAY
SHIFT_LD#
tPDLY
SBI OUTPUT
REGISTER
图 4. Side-Band Interface Timing Diagram
版权 © 2019–2020, Texas Instruments Incorporated
11
CDCDB2000
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
6.7 Typical Characteristics
图 5. CDCDB2000 Clock Out (CK0:19) Phase Noise
12
版权 © 2019–2020, Texas Instruments Incorporated
CDCDB2000
www.ti.com.cn
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
7 Detailed Description
7.1 Overview
The CDCDB2000 is a low additive-jitter, low propagation delay clock buffer designed to meet the strict
performance requirements for PCIe Gen 1-5, QPI and UPI reference clocks. The CDCDB2000 allows buffering
and replication of a single clock source to up to 20 individual outputs in the LP-HCSL format. The outputs of the
CDCDB2000 can be configured before they are enabled using the Side-Band control interface. The CDCDB2000
also includes status and control registers accessible by an SMBus version 2.0 compliant interface. The device
integrates a large amount of external passive components to reduce overall system cost.
7.2 Functional Block Diagram
CK0_P
CK0_N
CLKIN_P
CLKIN_N
CK1_P
CK1_N
CK2_P
CK2_N
SBEN
CK3_P
CK3_N
CLK
DATA
S
B
I
Glitch
Free
Output
Control
Logic
SHFT_LD#
OE[12:5]#
SMB
/OE
CK19_P
CK19_N
SMBDAT
SMBCLK
Control
Logic
SADR0
SADR1
CKPWRGD_PD#
7.3 Feature Description
7.3.1 Output Enable Control
The CDCDB2000 allows two methods to control the state of the output channels: SMBus/OE#, and Side-Band
Interface. Only one of the two methods can be active at any time, and the active interface is selected by the state
of the SBEN pin. Both methods of output control can assign the state of each output individually.
When in SMBus/OE# control is selected, the OE# pins become active. The OE# pins control the state of the
output with the same number. For example, the OE5# pin controls the state of the CK5 output driver. The SMBus
registers may enable/disable the output regardless of the OE# pin state if desired.
7.3.2 SMBus
The CDCDB2000 has an SMBus interface that is active only when CKPWRGD_PD# = 1.The SMBus allows
individual enable/disable of each output when the SMBus mode is selected using the SBEN pin.
When CKPWRGD_PD# = 0, the SMBus pins are placed in a Hi-Z state, but all register settings are retained. The
SMBus register values are only retained while VDD_A remains inside of the recommended operating voltage.
版权 © 2019–2020, Texas Instruments Incorporated
13
CDCDB2000
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
Feature Description (接下页)
7.3.2.1 SMBus Address Assignment
The SMBus address is assigned by configuration of two pins (SADR1 and SADR0) that each support three
levels. This configuration allows the CDCDB2000 to assume 9 different SMBus addresses.
The SMBus address pins are sampled PWRGD is set to 1. See 表 1 for address pin configuration. The address
cannot be changed until the PWRGD state is cleared by powering down the device.
表 1. SMBus Address Assignment
SADR1
SADR0
SMBUS ADDRESS
L
L
0xD8
0xDA
0xDE
0xC2
0xC4
0xC6
0xCA
0xCC
0xCE
L
M
H
L
L
M
M
M
H
H
H
M
H
L
M
H
7.3.3 Side-Band Interface
The Side-Band Interface(SBI) is a basic 3-wire interface that consists of the DATA, CLK and SHFT_LD# pins.
The SBI is used to shift data into a 20-bit long shift register. When the SHFT_LD# pin is high, the rising edge of
CLK can shift DATA into the shift register. After shifting data, the falling edge of SHFT_LD# clocks the shift
register contents to the SBI output register.
While SBI is enabled by the SBEN pin, OE[7:9, 11, 12]# pins are disabled and DATA, CLK and SHFT_LD# are
enabled on the OE5#, OE6# and OE10# pins, respectively.
When power has been applied, and SBEN = 1, the SBI is active regardless of the CKPWRGD_PD# pin state.
This characteristic allows loading the shift register and transferring the contents to the SBI output register before
the first assertion of the CKPWRGD_PD# pin.
7.4 Device Functional Modes
7.4.1 CKPWRGD_PD# Function
The CKPWRGD_PD# pin is used to set 2 state variables inside of the device: PWRGD, and PD#. The PWRGD
and PD# variables control which functions of the device are active at any time, as well as the state of the input
and output pins.
The PWRGD and PD# states are multiplexed on the CKPWRGD_PD# pin. CKPWRGD_PD# must remain below
VOL and not exceed VDD_A + 0.3 V until VDD, VDD_A, and CLKIN are present and within the recommended
operating conditions.
The first rising edge of the CKPWRGD_PD# pin sets PWRGD = 1. After PWRGD is set to 1, the
CKPWRGD_PD# pin is used to assert PD# mode only. PWRGD variable will only be cleared to 0 with the
removal of VDD and VDD_A.
14
版权 © 2019–2020, Texas Instruments Incorporated
CDCDB2000
www.ti.com.cn
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
Device Functional Modes (接下页)
VDD/VDD_A
CKPWRGD_PD#
PWRGD
PD#
图 6. PWRGD and PD# State Changes
7.4.2 OE[12:5]# and SMBus Output Enables
Each output channel, 0 to 19, can be individually enabled or disabled by SMBus control register bits, called SMB
enable bits. Additionally, each output channel from 12 to 5 has a dedicated, corresponding, OE[12:5]# hardware
pin. The OE[12:5]# pins are asynchronously asserted-low signals that may enable or disable the output.
Refer to 表 2 for enabling and disabling outputs through the hardware and software. Note that both the SMB
enable bit must be a ‘1’ and the OEx# pin must be an input low voltage ‘0’ for the output channel to be active.
表 2 is only valid when the SBEN signal is low (SBEN = 0).
表 2. OE[12:5]# Functionality When SBEN = 0
INPUTS
OE[12:5]# HARDWARE PINS AND SMBus CONTROL REGISTER BITS
PWRGD
PD#
CLKIN
SMBus ENABLE BIT OE[12:5]#
(byte[2:0])
CK[12:5]
CK[19:13, 4:0]
0
1
1
1
1
X
0
1
1
1
X
X
X
0
1
1
X
X
X
0
LOW
LOW
X
Tristate
Tristate
0
Running
Running
Running
0
Running
0
Running
Running
1
7.5 Programming
The CDCDB2000 has two methods to program the states of its 20 output drivers: SMBus and SBI.
To select between SMBus and SBI interfaces, the SBEN pin is used. Pulling the SBEN to a high level enables
the SBI. Pulling the SBEN pin to ground enables the SMBus interface. When SBI is enabled, the SMBus Mask
registers are active. The SMBus Mask registers allow the function of the SBI shift registers to be disabled and set
the each individual channel as enabled. See 图 7 for a diagram of how the SMBus Mask registers and SBI shift
register interact to enable or disable each output.
版权 © 2019–2020, Texas Instruments Incorporated
15
CDCDB2000
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
Programming (接下页)
To Output Logic
From SMBus Mask
Registers
. . . . . .
Mask0
Mask1
Mask19
Output
Register
(Default is 1)
. . . . . .
OE19
OE1
OE0
Q0
Q1
DATA
From Q18
Q
Q
D
D
Q
Q
D
Q
Q
Shift
Register
. . . . .
>
>
>
To Q2
CLK
SHFT_LD#
Side-Band Interface
图 7. SMBus Mask Register and SBI Shift Register Logic
7.5.1 SMBus
SMBus programming is described in SMBus, and the registers are described in Register Maps .
7.5.2 SBI
Side-Band Interface (SBI) is a simple 3-wire serial interface. This interface consists of DATA, CLK and
SHFT_LD# pins. When the SHFT_LD# pin is high, the rising edge of CLK clocks DATA into a shift register. After
shifting data, the falling edge of SHFT_LD# loads the shift register contents into the Output Register. Both the
SBI and the traditional SMBus interface feed common output enable/disable synchronization logic, which ensures
glitch-free enable and disable outputs regardless of the method used.
SBI can be configured at a system level in three ways: star topology, daisy chain topology, and directly. The star
topology is shown in 图 8. The daisy chain topology is shown in 图 9.
SHFT_LD# (1)
DATA
CLK
CDCDB2000
(1)
SBI
Controller
CDCDB2000
(2)
SHFT_LD# (2)
图 8. SBI Star Topology
16
版权 © 2019–2020, Texas Instruments Incorporated
CDCDB2000
www.ti.com.cn
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
Programming (接下页)
SHFT_LD#
SBI_IN
CLK
SBI_OUT
DATA
CK440Q
CDCDB2000
SBI
Controller
图 9. SBI Daisy Chain Topology
版权 © 2019–2020, Texas Instruments Incorporated
17
CDCDB2000
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
7.6 Register Maps
7.6.1 CDCDB2000 Registers
Table 3 lists the CDCDB2000 registers. All register locations not listed in Table 3 should be considered as
reserved locations and the register contents should not be modified.
Table 3. CDCDB2000 Registers
Address
0h
Acronym
OECR1
Register Name
Section
Go
Output Enable Control 1
1h
OECR2
Output Enable Control 2
Go
2h
OECR3
Output Enable Control 3
Go
3h
OERDBK
SBRDBK
VDRREVID
DEVID
Output Enable Read Back
SBEN Read Back
Go
4h
Go
5h
Vendor/Revision Identification
Device Identification
Go
6h
Go
7h
BTRDCNT
SBIMSK1
SBIMSK2
SBIMSK3
Byte Read Count Control
Side-Band Interface Override Control 1
Side-Band Interface Override Control 2
Side-Band Interface Override Control 3
Go
8h
Go
9h
Go
Ah
Go
Complex bit access types are encoded to fit into small table cells. Table 4 shows the codes that are used for
access types in this section.
Table 4. CDCDB2000 Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
7.6.1.1 OECR1 Register (Address = 0h) [reset = 78h]
OECR1 is shown in Table 5.
Return to the Summary Table.
The OECR1 register contains bits that enable or disable individual output clock channels [19:16]
Table 5. OECR1 Register Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
RESERVED
Output Enable, CK19
Reserved
6
R/W
1h
This bit controls the output enable signal for output channel
CK19_P/CK19_N.
0h = Output Disabled
1h = Output Enabled
5
Output Enable, CK18
R/W
1h
This bit controls the output enable signal for output channel
CK18_P/CK18_N.
0h = Output Disabled
1h = Output Enabled
18
Copyright © 2019–2020, Texas Instruments Incorporated
CDCDB2000
www.ti.com.cn
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
Table 5. OECR1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
Output Enable, CK17
R/W
1h
This bit controls the output enable signal for output channel
CK17_P/CK17_N.
0h = Output Disabled
1h = Output Enabled
3
Output Enable, CK16
RESERVED
R/W
R
1h
0h
This bit controls the output enable signal for output channel
CK16_P/CK16_N.
0h = Output Disabled
1h = Output Enabled
Reserved
2-0
7.6.1.2 OECR2 Register (Address = 1h) [reset = FFh]
OECR2 is shown in Table 6.
Return to the Summary Table.
The OECR2 register contains bits that enable or disable individual output clock channels [7:0]
Table 6. OECR2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
Output Enable, CK7
R/W
1h
This bit controls the output enable signal for output channel
CK7_P/CK7_N.
0h = Output Disabled
1h = Output Enabled
6
5
4
3
2
1
0
Output Enable, CK6
Output Enable, CK5
Output Enable, CK4
Output Enable, CK3
Output Enable, CK2
Output Enable, CK1
Output Enable, CK0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1h
1h
1h
1h
1h
1h
1h
This bit controls the output enable signal for output channel
CK6_P/CK6_N.
0h = Output Disabled
1h = Output Enabled
This bit controls the output enable signal for output channel
CK5_P/CK5_N.
0h = Output Disabled
1h = Output Enabled
This bit controls the output enable signal for output channel
CK4_P/CK4_N.
0h = Output Disabled
1h = Output Enabled
This bit controls the output enable signal for output channel
CK3_P/CK3_N.
0h = Output Disabled
1h = Output Enabled
This bit controls the output enable signal for output channel
CK2_P/CK2_N.
0h = Output Disabled
1h = Output Enabled
This bit controls the output enable signal for output channel
CK1_P/CK1_N.
0h = Output Disabled
1h = Output Enabled
This bit controls the output enable signal for output channel
CK0_P/CK0_N.
0h = Output Disabled
1h = Output Enabled
Copyright © 2019–2020, Texas Instruments Incorporated
19
CDCDB2000
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
7.6.1.3 OECR3 Register (Address = 2h) [reset = FFh]
OECR3 is shown in Table 7.
Return to the Summary Table.
The OECR3 register contains bits that enable or disable individual output clock channels [15:8]
Table 7. OECR3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
Output Enable, CK15
R/W
1h
This bit controls the output enable signal for output channel
CK15_P/CK15_N.
0h = Output Disabled
1h = Output Enabled
6
5
4
3
2
1
0
Output Enable, CK14
Output Enable, CK13
Output Enable, CK12
Output Enable, CK11
Output Enable, CK10
Output Enable, CK9
Output Enable, CK8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1h
1h
1h
1h
1h
1h
1h
This bit controls the output enable signal for output channel
CK14_P/CK14_N.
0h = Output Disabled
1h = Output Enabled
This bit controls the output enable signal for output channel
CK13_P/CK13_N.
0h = Output Disabled
1h = Output Enabled
This bit controls the output enable signal for output channel
CK12_P/CK12_N.
0h = Output Disabled
1h = Output Enabled
This bit controls the output enable signal for output channel
CK11_P/CK11_N.
0h = Output Disabled
1h = Output Enabled
This bit controls the output enable signal for output channel
CK10_P/CK10_N.
0h = Output Disabled
1h = Output Enabled
This bit controls the output enable signal for output channel
CK9_P/CK9_N.
0h = Output Disabled
1h = Output Enabled
This bit controls the output enable signal for output channel
CK8_P/CK8_N.
0h = Output Disabled
1h = Output Enabled
7.6.1.4 OERDBK Register (Address = 3h) [reset = 0h]
OERDBK is shown in Table 8.
Return to the Summary Table.
The OERDBK register contains bits that report the current state of the OE[12:5]# input pins.
Table 8. OERDBK Register Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
OE12# State
OE11# State
OE10# State
OE9# State
OE8# State
This bit reports the logic level present on the OE12# pin.
This bit reports the logic level present on the OE11# pin.
This bit reports the logic level present on the OE10# pin.
This bit reports the logic level present on the OE9# pin.
This bit reports the logic level present on the OE8# pin.
6
R
0h
5
R
0h
4
R
0h
3
R
0h
20
Copyright © 2019–2020, Texas Instruments Incorporated
CDCDB2000
www.ti.com.cn
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
Table 8. OERDBK Register Field Descriptions (continued)
Bit
2
Field
Type
R
Reset
0h
Description
OE7# State
OE6# State
OE5# State
This bit reports the logic level present on the OE7# pin.
This bit reports the logic level present on the OE6# pin.
This bit reports the logic level present on the OE5# pin.
1
R
0h
0
R
0h
7.6.1.5 SBRDBK Register (Address = 4h) [reset = 1h]
SBRDBK is shown in Table 9.
Return to the Summary Table.
The SBRDBK register contains a bit that report the current state of the SBEN input pin.
Table 9. SBRDBK Register Field Descriptions
Bit
7-1
0
Field
Type
R
Reset
0h
Description
RESERVED
SBEN State
Reserved
R/W
1h
This bit reports the logic level present on the SBEN pin.
7.6.1.6 VDRREVID Register (Address = 5h) [reset = X]
VDRREVID is shown in Table 10.
Return to the Summary Table.
The VDRREVID register contains a vendor identification code and silicon revision code.
Table 10. VDRREVID Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
Revision Code[3:0]
R
X
Silicon revision code.
Silicon revision code bits
[3:0] map to register bits
[7:4] directly.
3-0
Vendor ID[3:0]
R
X
Vendor identification code.
Vendor ID bits
[3:0] map to register bits
[3:0] directly.
7.6.1.7 DEVID Register (Address = 6h) [reset = X]
DEVID is shown in Table 11.
Return to the Summary Table.
The DEVID register contains a device identification code.
Table 11. DEVID Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Device ID[7:0]
R
X
Device ID code.
Device ID bits[7:0] map to register bits[7:0] directly.
7.6.1.8 BTRDCNT Register (Address = 7h) [reset = 8h]
BTRDCNT is shown in Table 12.
Return to the Summary Table.
The BTRDCNT register allows configuration of the number of bytes that will be read back from the SMBus
interface on an issued read command.
Copyright © 2019–2020, Texas Instruments Incorporated
21
CDCDB2000
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
Table 12. BTRDCNT Register Field Descriptions
Bit
7-6
5-0
Field
Type
R
Reset
0h
Description
RESERVED
Read Byte Count[5:0]
Reserved
R/W
8h
Writing to this register configures how many bytes will be read back.
7.6.1.9 SBIMSK1 Register (Address = 8h) [reset = 0h]
SBIMSK1 is shown in Table 13.
Return to the Summary Table.
The SBIMSK1 register allows the SMBus to force enable each output channel individually when the CDCDB2000
is in Side-Band interface mode.
Table 13. SBIMSK1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
SBI Output Mask, CK7
R/W
0h
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK7 Enabled
6
5
4
3
2
1
0
SBI Output Mask, CK6
SBI Output Mask, CK5
SBI Output Mask, CK4
SBI Output Mask, CK3
SBI Output Mask, CK2
SBI Output Mask, CK1
SBI Output Mask, CK0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK6 Enabled
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK5 Enabled
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK4 Enabled
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK3 Enabled
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK2 Enabled
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK1 Enabled
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK0 Enabled
7.6.1.10 SBIMSK2 Register (Address = 9h) [reset = 0h]
SBIMSK2 is shown in Table 14.
Return to the Summary Table.
The SBIMSK2 register allows the SMBus to force enable each output channel individually when the CDCDB2000
is in Side-Band interface mode.
Table 14. SBIMSK2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
SBI Output Mask, CK15
R/W
0h
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK15 Enabled
22
Copyright © 2019–2020, Texas Instruments Incorporated
CDCDB2000
www.ti.com.cn
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
Table 14. SBIMSK2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6
SBI Output Mask, CK14
R/W
0h
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK14 Enabled
5
4
3
2
1
0
SBI Output Mask, CK13
SBI Output Mask, CK12
SBI Output Mask, CK11
SBI Output Mask, CK10
SBI Output Mask, CK9
SBI Output Mask, CK8
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK13 Enabled
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK12 Enabled
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK11 Enabled
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK10 Enabled
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK9 Enabled
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK8 Enabled
7.6.1.11 SBIMSK3 Register (Address = Ah) [reset = 0h]
SBIMSK3 is shown in Table 15.
Return to the Summary Table.
The SBIMSK3 register allows the SMBus to force enable each output channel individually when the CDCDB2000
is in Side-Band interface mode.
Table 15. SBIMSK3 Register Field Descriptions
Bit
7-4
3
Field
Type
R
Reset
0h
Description
RESERVED
Reserved
SBI Output Mask, CK19
R/W
0h
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK19 Enabled
2
1
0
SBI Output Mask, CK18
SBI Output Mask, CK17
SBI Output Mask, CK16
R/W
R/W
R/W
0h
0h
0h
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK18 Enabled
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK17 Enabled
This bit overrides the the SBI output disable when set.
0h = SBI Controls Output
1h = Output CK16 Enabled
版权 © 2019–2020, Texas Instruments Incorporated
23
CDCDB2000
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The CDCDB2000 is a fanout buffer that supports PCIe generation 4 and PCIe generation 5 REFCLK distribution.
It is used to create, and distribute, up to 20 copies of a typically 100-MHz clock.
8.2 Typical Application
图 10 shows a CDCDB2000 typical application. In this application, a clock generator provides a 100-MHz
reference to the CDCDB2000 which then distributes that clock to PCIe endpoints. The clock generator may be a
discrete clock generator like the LMK03328 or it may be integrated in a larger component such as a PCH or
application processor.
PCIe Gen 4-5
Clock
Generator
20
LP-HCSL
PCIe Device
CDCDB2000
20x LP-HSCL Output Buffer
LP-HCSL
OE#
Control
SMBus
Control
Side-Band
Interface
Control Interface
图 10. Typical Application
8.2.1 Design Requirements
Consider a typical server motherboard application which needs to distribute a 100-MHz PCIe reference clock
from the PCH of a processor chipset to multiple endpoints. An example of clock input and output requirements is:
•
Clock Input:
–
100-MHz LP-HCSL
•
Clock Output:
–
–
–
2x 100-MHz to processors, LP-HCSL
2x 100-MHz to riser/retimer, LP-HCSL
2x 100-MHz to DDR memory controller, LP-HCSL
The section below describes the design procedure to configure the CDCDB2000 to output the frequencies for the
above scenario.
8.2.2 Detailed Design Procedure
The following items must be determined before starting design of a CDCDB2000 socket:
•
•
Output Enable Control Method
SMBus address
24
版权 © 2019–2020, Texas Instruments Incorporated
CDCDB2000
www.ti.com.cn
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
Typical Application (接下页)
8.2.2.1 Output Enable Control Method
If the SMBus and OE# pins should be used for controlling output states, the SBEN pin should be tied to a low
potential. This could be selected for hot swapping where pin control by a CPLD or other hot swap controller is
needed to enable/disable the reference clock to safeguard against backdriving a connected device.
8.2.2.2 SMBus Address
An SMBus address should be selected from the listed potential addresses in 表 1. The appropriate pullup or
pulldown resistor should be placed on the SADRx pins as indicated in the table. Ensure the SMBus address is
not already in use to avoid conflict.
8.2.3 Application Curve
The graph listed in 表 16 is used as both an application curve and a typical characteristics plot (see the Typical
Characteristics section).
表 16. Table of Graphs
TITLE
FIGURE
CDCDB2000 Clock Out (CK0:19) Phase Noise
图 5
版权 © 2019–2020, Texas Instruments Incorporated
25
CDCDB2000
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
9 Power Supply Recommendations
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
the jitter and phase noise is critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guards the power supply system
against induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by
the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, they
must be placed very close to the power-supply terminals and laid out with short loops to minimize inductance. TI
recommends to insert a ferrite bead between the board power supply and the chip power supply that isolates the
high-frequency switching noises generated by the clock buffer. These beads prevent the switching noise from
leaking into the board supply. It is imperative to choose an appropriate ferrite bead with very low DC resistance
to provide adequate isolation between the board supply and the chip supply, as well as to maintain a voltage at
the supply terminals that is greater than the minimum voltage required for proper operation.
shows the recommended power supply filtering and decoupling method.
3.3 V
VDD
10 ꢀF
0.1 ꢀF 0.1 ꢀF 0.1 ꢀF 0.1 ꢀF 0.1 ꢀF
3.3 V
VDD_A
2.2 ꢁ
10 ꢀF
0.1 ꢀF
图 11. Power Supply Decoupling
26
版权 © 2019–2020, Texas Instruments Incorporated
CDCDB2000
www.ti.com.cn
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
10 Layout
10.1 Layout Guidelines
The following section provides the layout guidelines to ensure good thermal performance and power supply
connections for the CDCDB2000.
10.2 Layout Examples
图 12 and 图 13 are PCB layout examples that show the application of thermal design practices and a low-
inductance ground connection between the device DAP and the PCB.
The CDCDB2000 has 85-Ω differential output impedance LP-HCSL format drivers. All transmission lines
connected to CKx pins should be 85-Ω differential impedance, 42.5-Ω single-ended impedance to avoid
reflections and increased radiated emissions. Take care to eliminate or reduce stubs on the transmission lines.
All CKx pairs routed
differentially
Recommended ground vias
Vias to escape
inside pins
图 12. PCB Layout Example for CDCDB2000, Top Layer
版权 © 2019–2020, Texas Instruments Incorporated
27
CDCDB2000
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
Layout Examples (接下页)
图 13. PCB Layout Example for CDCDB2000, GND Layer
28
版权 © 2019–2020, Texas Instruments Incorporated
CDCDB2000
www.ti.com.cn
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
Layout Examples (接下页)
100nF decoupling capacitors
must be within 25mm of pin
100nF decoupling capacitors
must be within 25mm of pin
100nF decoupling capacitors
must be within 25mm of pin
图 14. PCB Layout Example for CDCDB2000, Bottom Layer
版权 © 2019–2020, Texas Instruments Incorporated
29
CDCDB2000
ZHCSKG8A –NOVEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 TICS Pro
TICS Pro 是用于 EVM 编程的离线软件工具，也可以用生成寄存器映射，为特定应用的器件配置编程。如需 TICS
Pro，请访问 http://www.ti.com.cn/tool/cn/TICSPRO-SW。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
30
版权 © 2019–2020, Texas Instruments Incorporated
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CDCDB2000NPPR
CDCDB2000NPPT
ACTIVE
TLGA
TLGA
NPP
80
80
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
CDCDB
2000
ACTIVE
NPP
NIPDAU
CDCDB
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Feb-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCDB2000NPPR
CDCDB2000NPPT
TLGA
TLGA
NPP
NPP
80
80
3000
250
330.0
180.0
16.4
16.4
6.3
6.3
6.3
6.3
1.1
1.1
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Feb-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CDCDB2000NPPR
CDCDB2000NPPT
TLGA
TLGA
NPP
NPP
80
80
3000
250
367.0
210.0
367.0
185.0
38.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
NPP0080A
TLGA - 0.9 mm max height
SCALE 2.500
THIN LAND GRID ARRAY
6.1
5.9
B
A
PIN A1
CORNER
6.1
5.9
C
0.9
0.8
SEATING PLANE
5.5 TYP
SYMM
0.08 C
(0.125)
0.05
0.00
M
(0.125)
L
K
J
5.5
TYP
H
G
F
SYMM
(0.725)
2.8 0.1
E
D
0.5
TYP
C
B
(0.725)
0.3
80X
0.2
A
0.1
C A B
C
7
8
9
3
4
5
6
10 11 12
1
2
0.05
PIN 1 ID
(45 X 0.35)
0.5 TYP
4224877/A 03/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
NPP0080A
TLGA - 0.9 mm max height
THIN LAND GRID ARRAY
(0.5) TYP
(1.15)
8
80X ( 0.25)
12
1
2
3
4
5
6
7
9
10
11
A
(0.5) TYP
B
C
D
E
F
(1.15)
SYMM
(
2.8)
G
H
(
0.2) VIA
TYP
J
K
L
M
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MIN
METAL UNDER
SOLDER MASK
0.05 MAX
(
0.25)
METAL
EXPOSED
METAL
(
0.25)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4224877/A 03/2019
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
NPP0080A
TLGA - 0.9 mm max height
THIN LAND GRID ARRAY
(0.5) TYP
(R0.05) TYP
(0.715)
80X ( 0.25)
1
2
4
5
6
7
8
9
10
3
11
12
A
B
(0.5) TYP
C
D
E
F
METAL
TYP
(0.715)
SYMM
G
H
J
4X ( 1.23)
EXPOSED METAL
TYP
K
L
M
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 15X
4224877/A 03/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
©2020 ICPDF网 联系我们和版权申明