CDCDB400RHBR [TI]

适用于 PCIe® 第 1 代到第 5 代的 4 路输出时钟缓冲器 | RHB | 32 | -40 to 105;


型号：	CDCDB400RHBR
厂家：	TEXAS INSTRUMENTS
描述：	适用于 PCIe® 第 1 代到第 5 代的 4 路输出时钟缓冲器 \| RHB \| 32 \| -40 to 105 时钟 PC
文件：	总33页 (文件大小：2272K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CDCDB400

ZHCSOD8A – NOVEMBER 2021 – REVISED MAY 2022

CDCDB400 适用于第 1 代到第 6 代 PCIe、符合 DB800ZL 标准的 4 输出时钟缓冲

器

1 特性

2 应用

•

微服务器和塔式服务器

•

具有可编程集成 85Ω（默认值）或 100Ω 差分输出

存储区域网络和主机总线适配器卡

网络连接存储

终端的 4 个 LP-HCSL 输出

4 硬件输出使能端 (OE#) 控制装置

使用第 6 代 PCIE 滤波器之后的附加相位抖动：

20fs RMS（最大值）

•

硬件加速器

机架式服务器

通信交换机

•

使用第 5 代 PCIE 滤波器之后的附加相位抖动：

25fs RMS（最大值）

模块化计算机

CT 和 PET 扫描仪

加固型 PC 和笔记本电脑

使用 DB2000Q 滤波器之后的附加相位抖动：38fs

RMS（最大值）

支持公共时钟 (CC) 和单独基准 (IR) 架构

– 与扩频兼容

3 说明

CDCDB400 是一款符合 DB800ZL 标准的 4 输出

LP-HCSL 时钟缓冲器，能够为采用 CC、SRNS 或

SRIS 架构的第 1 代到第 6 代 PCIe、QuickPath

Interconnect (QPI)、UPI、SAS 和 SATA 接口分配

基准时钟。使用 SMBus 接口和四输出使能引脚，可

以单独配置和控制所有四个输出。CDCDB400 是一款

DB800ZL 衍生缓冲器，符合或超过 DB800ZL 中的系

统参数规格。该器件还符合或超过了 DB2000Q 规格

中的参数。CDCDB400 采用 5mm × 5mm 32 引脚

VQFN 封装。

•

输出到输出偏斜：< 50ps

输入到输出延迟：< 3ns

失效防护输入

可编程输出转换率控制

3 个可选 SMBus 地址

3.3V 内核和 IO 电源电压

硬件控制的低功耗模式 (PD#)

电流消耗：46mA（最大值）

5mm × 5mm 32 引脚 VQFN 封装

器件信息

器件型号

CDCDB400

封装 ⁽¹⁾

封装尺寸（标称值）

VQFN (32)

5.00mm × 5.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

PCIe PHY

PCIe Device

PCIe Gen 4-5

Clock

Generator

LP-HCSL

CDCDB400

4x LP-HSCL Output Buffer

LP-HCSL

OE#

Control

SMBus

Control

Control Interface

CDCDB400 系统图

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNAS833

CDCDB400

ZHCSOD8A – NOVEMBER 2021 – REVISED MAY 2022

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Table of Contents

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 Timing Requirements..................................................8

6.7 Typical Characteristics................................................9

7 Parameter Measurement Information..........................10

8 Detailed Description......................................................11

8.1 Overview................................................................... 11

8.2 Functional Block Diagram......................................... 11

8.3 Feature Description...................................................11

8.4 Device Functional Modes..........................................12

8.5 Programming............................................................ 13

8.6 Register Maps...........................................................15

9 Application and Implementation..................................19

9.1 Application Information............................................. 19

9.2 Typical Application.................................................... 19

10 Power Supply Recommendations..............................21

11 Layout...........................................................................22

11.1 Layout Guidelines................................................... 22

11.2 Layout Examples.....................................................22

12 Device and Documentation Support..........................24

12.1 Device Support....................................................... 24

12.2 接收文档更新通知................................................... 24

12.3 支持资源..................................................................24

12.4 Trademarks.............................................................24

12.5 Electrostatic Discharge Caution..............................24

12.6 术语表..................................................................... 24

13 Mechanical, Packaging, and Orderable

Information.................................................................... 24

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (November 2021) to Revision A (May 2022)

Page

•

更改了数据表标题...............................................................................................................................................1

在数据表中添加了 PCIe 第 6 代..........................................................................................................................1

Changed the pin description for pin 5.................................................................................................................3

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5 Pin Configuration and Functions

CKPWRGD_PD#

VDDR

OE2#

CK2_N

CK2_P

VDD

CLKIN_P

CLKIN_N

SADR0

GND

CK1_N

CK1_P

OE1#

SMBDAT

SMBCLK

Not to scale

图 5-1. CDCDB400 RHB Package 32-Pin VQFN Top View

表 5-1. Pin Functions

TYPE⁽²⁾

DESCRIPTION

NAME

INPUT CLOCK

CLKIN_P

NO.

LP-HCSL differential clock input. Typically connected directly to the differential

output of clock source.

CLKIN_N

OUTPUT CLOCKS

CK0_P

LP-HCSL differential clock output of channel 0. Typically connected directly to PCIe

differential clock input. If unused, the pins can be left no connect.

CK0_N

CK1_P

LP-HCSL differential clock output of channel 1. Typically connected directly to PCIe

differential clock input. If unused, the pins can be left no connect.

CK1_N

CK2_P

LP-HCSL differential clock output of channel 2. Typically connected directly to PCIe

differential clock input. If unused, the pins can be left no connect.

CK2_N

CK3_P

CK3_N

LP-HCSL differential clock output of channel 3. Typically connected directly to PCIe

differential clock input. If unused, the pins can be left no connect.

MANAGEMENT AND CONTROL ⁽¹⁾

Clock Power Good and Power Down multi-function input pin with internal 180-kΩ

pulldown. Typically connected to GPIO of microcontroller. If unused, the pin can

be left no connect. After PWRGD has been asserted high for the first time, the pin

becomes a PD# pin and it controls power-down mode:

CKPWRGD_PD#

I, S, PD

LOW: Power-down mode, all output channels tri-stated.

HIGH: Normal operation mode.

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表 5-1. Pin Functions (continued)

TYPE⁽²⁾

DESCRIPTION

NAME

NO.

Output Enable for channel 0 with internal 180-kΩ pulldown, active low. Typically

connected to GPIO of microcontroller. If unused, the pin can be left no connect.

LOW: enable output channel 0.

OE0#

OE1#

OE2#

OE3#

I, S, PD

HIGH: disable output channel 0.

Output Enable for channel 1 with internal 180-kΩ pulldown, active low. Typically

connected to GPIO of microcontroller. If unused, the pin can be left no connect.

LOW: enable output channel 1.

HIGH: disable output channel 1.

Output Enable for channel 2 with internal 180-kΩ pulldown, active low. Typically

connected to GPIO of microcontroller. If unused, the pin can be left no connect.

LOW: enable output channel 2.

HIGH: disable output channel 2.

Output Enable for channel 3, with internal 180-kΩ pulldown, active low. Typically

connected to GPIO of microcontroller. If unused, the pin can be left no connect.

LOW: enable output channel 3.

HIGH: disable output channel 3.

SMBUS AND SMBUS ADDRESS

SMBus address strap bit. This is a 3-level input that is decoded in conjunction with

pin B8 to set SMBus address. It has internal 180-kΩ pullup / pulldown network

biasing to GND when no connect.

For a high-level input configuration, the pin should be pulled up to 3.3-V VDD

SADR0

I, S, PU / PD through an external pullup resistor from 1k to 5k with 5% tolerance.

For a low-level input configuration input, the pin should be pulled down to ground

through an external pulldown resistor from 1k to 5k with 5% tolerance.

For a mid-level input configuration, the pin should be left floating and not

connected to VDD or ground.

Data pin of SMBus interface. Typically pulled up to 3.3-V VDD using external pullup

resistor. The recommended pullup resistor value is > 8.5k.

SMBDAT

SMBCLK

I / O

Clock pin of SMBus interface. Typically pulled up to 3.3-V VDD using external

pullup resistor. The recommended pullup resistor value is > 8.5k.

SUPPLY VOLTAGE AND GROUND

Power supply input for input clock receiver. Connect to 3.3-V power supply rail with

VDDR

VDD

decoupling capacitor to GND. Place a 0.1-µF capacitor close to each supply pin

between power supply and ground.

12, 16, 21, 25, 29,

3.3-V power supply for output channels and core voltage.

Ground. Connect ground pad to system ground.

GND

DAP

NO CONNECT

8, 9, 10, 11, 17, 30

—

Do not connect pins to GND or VDD. Leave floating.

Pin may be connected to GND, VDD, or otherwise tied to any potential within the

Supply Voltage range stated in the Absolute Maximum Ratings.

(1) The “#” symbol at the end of a pin name indicates that the active state occurs when the signal is at a low voltage level. When “#” is not

present, the signal is active high.

(2) The definitions below define the I/O type for each pin.

•

I = Input

O = Output

I / O = Input / Output

PU / PD = Internal 180-kΩ Pullup / Pulldown network biasing to VDD/2

PD = Internal 180-kΩ Pulldown

S = Hardware Configuration Pin

P = Power Supply

G = Ground

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

−0.3

MAX

3.6

UNIT

V_DD,V_{DD_R}

Power supply voltage

IO input voltage

V_IN

T_J

3.6

Junction temperature

Storage temperature

125

150

°C

T_stg

−65

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC

JS-001, all pins⁽¹⁾

±3500

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per ANSI/ESDA/

JEDEC JS-002, all pins⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

3.3

MAX

3.6

UNIT

V_DD

V_{DD_R}

T_A

IO, Core supply voltage

Input supply voltage

Ambient temperature

3.3

3.6

−40

105

°C

6.4 Thermal Information

CDCDB400

THERMAL METRIC⁽¹⁾

RHB (QFN)

32 PINS

35.3

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

27.3

16.2

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.6

Ψ_JB

16.2

R_θJC(bot)

6.1

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics

VDD, VDD_R = 3.3 V ± 5 %, −40°C ≤ T_A≤ 85°C. Typical values are at VDD = VDD_R = 3.3 V, 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CURRENT CONSUMPTION

Active mode. CKPWRGD_PD# = 1

Power-down mode. CKPWRGD_PD# = 0

All outputs disabled

8.5

I_{DD_R}

Core supply current

IO supply current

8.5

1.5

I_DD

All outputs active, 100 MHz (per output)

Power-down mode. CKPWRGD_PD# = 0

CLOCK INPUT

f_IN

Input frequency

200

0.7

100

250

MHz

Differential voltage between CLKIN_P and

CLKIN_N⁽¹⁾

mV_Diff-

V_IN

Input voltage swing

2300

peak

dV/dt

Input voltage edge rate

Total variation of V_CROSS

Input duty cycle

20% - 80% of input swing

V/ns

DV_CROSS

DC_IN

Total variation across V_CROSS

140

2.2

Differential capacitance between CLKIN_P

and CLKIN_N pins

C_IN

Input capacitance⁽²⁾

CLOCK OUTPUT

f_OUT

Output frequency

100

250

MHz

Differential capacitance between CKx_P

and CKx_N pins

C_OUT

Output capacitance⁽¹⁾

V_OH

V_OL

Output high voltage

Output low voltage

225

270

150

Single-ended^{(2) (3)}

Measured into an AC load as defined in

DB800ZL

V_HIGH

V_LOW

Output high voltage

Output low voltage

660

850

150

Measured into an AC load as defined in

DB800ZL

–150

Measured into an AC load as defined in

DB800ZL

V_MAX

Output Max voltage

1150

200

550

V_CROSS

Crossing point voltage

See ^{(3) (4)}

130

250

Measured into an AC load as defined in

DB800ZL

V_CROSSACCrossing point voltage (AC load)

(3) (4)

DV_CROSS

V_ovs

Total variation of V_CROSS

Overshoot voltage

Variation of V_CROSS

140

See ⁽³⁾

V_OH+75

Measured into an AC load as defined in

DB800ZL

V_HIGH+30

V_ovs(AC)

V_uds

Overshoot voltage (AC load)

Undershoot voltage

See ⁽³⁾

V_OL–75

Measured into an AC load as defined in

DB800ZL

V_LOW–

V_uds(AC)

Undershoot voltage

300

Measured

into an AC

load as

defined in

Measured into an AC load as

DB800ZL

V_rb

Ringback Voltage

defined in DB800ZL and taken

and taken

-0.2

0.2

from single-ended waveform.

from

single-

ended

waveform.

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VDD, VDD_R = 3.3 V ± 5 %, −40°C ≤ T_A≤ 85°C. Typical values are at VDD = VDD_R = 3.3 V, 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Differential impedance (Default

setting, 85 Ω)

Measured at V_OL/V_OH

Z_DIFF

Differential impedance (Output

impedance selection bit =1, 100 Ω)

Measured at V_OL/V_OH

Measured at V_CROSS

100

105

102

120

Differential impedance (Default

setting, 85 Ω)

Z_{DIFF_CROS}

Differential impedance (Output

impedance selection bit = 1, 100 Ω)

Measured at V_CROSS

100

(7)

t_EDGE

Differential edge rate

Edge rate matching

Measured (±150 mV) around V_CROSS

V/ns

(7)

Dt_EDGE

Measured (±150 mV) V_CROSS

Measured

when

positive

output

reaches

0.2 V

CKPWRGD_PD# pin

transitions from 0 to 1, f_IN

100 MHz

Power good assertion to stable clock

output

t_STABLE

1.8

µs

Measured

when

positive

output

reaches

0.2 V

CKPWRGD_PD# pin

transitions from 0 to 1, f_IN

100 MHz

Power good assertion to outputs

driven high

t_{DRIVE_PD#}

300

Output enable assertion to stable

clock output

t_OE

t_OD

t_PD

OEx# pin transitions from 1 to 0

OEx# pin transitions from 0 to 1

Output enable de-assertion to no

clock output

CLKIN

Periods

Power-down assertion to no clock

output

CKPWRGD_PD# pin transitions from 1 to 0

t_DCD

t_DLY

Duty cycle distortion

Propagation delay

Differential; f_IN= 100 MHz, f_{IN_DC}= 50%

–1

See ⁽⁵⁾

See ⁽⁶⁾

0.5

t_SKEW

Skew between outputs

t_DELAY(IN-

Input-to-output delay variation at 100 MHz

across voltage and temperature

Input to output delay variation

Additive jitter for DB2000QL

–250

250

OUT)

DB2000QL filter, for input of 200-mV

differential swing at 1.5 V/ns

0.038

Input clock

slew rate =

PLL BW: 0.5 - 1 MHz; CDR =

Additive jitter for PCIe6.0

Additive jitter for PCIe5.0

Additive jitter for PCIe4.0

0.02

0.025

0.06

10 MHz

2 V/ns

J_{CKx_PCIE}

PCIe5.0 filter

ps, RMS

(7)

Input clock

slew rate ≥

1.8 V/ns

PLL BW = 2 - 5 MHz; CDR =

10 MHz

Input clock

slew rate ≥

0.6 V/ns

Additive jitter for PCIe3.0

Additive jitter

0.1

f_IN= 100 MHz; slew rate ≥ 3 V/ns; 12 kHz to

20 MHz integration bandwidth.

J_CKx

100

160 fs, RMS

-155 dBc/Hz

Input clock

f_IN= 100 MHz; f_Offset≥ 10 MHz slew rate ≥

3 V/ns

Noise floor

–160

SMBUS INTERFACE, OEx#, CKPWRGD_PD#

V_IH

V_IL

High level input voltage

Low level input voltage

2.0

0.8

GND ≤ V_IN

With internal pullup/pulldown

≤ V_DD

I_IH

Input leakage current

–30

µA

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VDD, VDD_R = 3.3 V ± 5 %, −40°C ≤ T_A≤ 85°C. Typical values are at VDD = VDD_R = 3.3 V, 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

GND ≤ V_IN

≤ V_DD

I_IL

I_IH

I_IL

Input leakage current

With internal pullup/pulldown

–30

µA

Without internal pullup/

pulldown

GND ≤ V_IN

≤ V_DD

Input leakage current

−5

µA

Without internal pullup/

pulldown

GND ≤ V_IN

≤ V_DD

C_IN

Input capacitance

Output capacitance

4.5

C_OUT

3-LEVEL DIGITAL INTERFACE (SADR0)

V_IH

V_IM

V_IL

I_IH

High level input voltage

Mid level input voltage

Low level input voltage

Input leakage current

Input capacitance⁽¹⁾

2.3

1.25

V_DD/2

1.725

0.85

With internal pullup/pulldown

V_IN= V_DD

–30

µA

I_IL

V_IN= GND

C_IN

4.5

(1) Voltage swing includes overshoot.

(2) Not tested in production. Ensured by design and characterization.

(3) Measured into DC test load.

(4) V_CROSSis single-ended voltage when CKx_P = CKx_N with respect to system ground. Only valid on rising edge of CKx, when CKx_P

is rising.

(5) Measured from rising edge of CLK_IN to any CKx output.

(6) Measured from rising edge of any CKx output to any other CKx output.

(7) Measured into AC test load.

6.6 Timing Requirements

VDD, VDD_R = 3.3 V ± 5 %, −40°C ≤ T_A≤ 85°C. Typical values are at VDD = VDD_R = 3.3 V, 25°C (unless otherwise noted)

MIN

NOM

MAX

UNIT

SMBUS COMPATIBLE INTERFACE TIMING

f_SMB

SMBus operating frequency

Bus free time between STOP and START

START condition hold time

START condition setup time

STOP condition setup time

SMBDAT hold time

4.7

400

kHz

t_BUF

t_{HD_STA}

t_{SU_STA}

t_{SU_STO}

t_{HD_DAT}

t_{SU_DAT}

SMBCLK low after SMBDAT low

SMBCLK high before SMBDAT low

µs

4.7

300

250

1e6

4.7

cycles

µs

SMBDAT setup time

t_TIMEOUTDetect SMBCLK low timeout

In terms of device input clock frequency

t_LOW

t_HIGH

t_F

SMBCLK low period

SMBCLK high period

300

SMBCLK/SMBDAT fall time⁽¹⁾

SMBCLK/SMBDAT rise time⁽²⁾

t_R

1000

(1) TF = (VIHMIN + 0.15) to (VILMAX - 0.15)

(2) TR = (VILMAX - 0.15) to (VIHMIN + 0.15)

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6.7 Typical Characteristics

图 6-1 shows both the phase noise of the source as well as the output of the DUT (CDCDB400). It can be seen from the

phase noise plot that the DUT has a very low phase noise profile with total jitter of 81.5 fs, rms. If we rms subtract the clock

reference noise, the additive jitter of CDCDB400 under typical conditions would be lower than 81.5 fs, rms.

图 6-1. CDCDB400 Clock Out (CK0:4) Phase Noise

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7 Parameter Measurement Information

10 inches/ 25.4 cm

< 1 pF

>100 k

GND

CK+

CK-

DUT

Differential impedance 85

High

Impedance

Probe

< 1 pF

GND

2 pF

图 7-1. AC Test Load (Referencing Intel DB2000QL Document)

0.75 V

SMA

CK+

CK-

0.75 V

DUT

GND

42.5

R1 = 47 Ω and R2 = 147 Ω.

图 7-2. DC Simulation Load (Referencing Intel DB2000QL Document)

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8 Detailed Description

8.1 Overview

The CDCDB400 is a low additive-jitter, low propagation delay clock buffer designed to meet the strict

performance requirements for PCIe Gen 1-6, QPI, UPI, SAS, and SATA reference clocks in CC, SRNS, or SRIS

architectures. The CDCDB400 allows buffering and replication of a single clock source to up to four individual

outputs in the LP-HCSL format. The CDCDB400 also includes status and control registers accessible by an

SMBus version 2.0 compliant interface. The device integrates a large amount of external passive components to

reduce overall system cost.

8.2 Functional Block Diagram

CK0_P

CK0_N

CLKIN_P

CLKIN_N

CK1_P

CK1_N

CK2_P

CK2_N

Glitch

Free

Output

Control

Logic

OE[3:0]#

CK3_P

CK3_N

SMBDAT

SMBCLK

SADR0

Control

Logic

CKPWRGD_PD#

8.3 Feature Description

8.3.1 Fail-Safe Input

The CDCDB400 is designed to support fail-safe input operation feature. This feature allows the user to drive the

device inputs before V_DDis applied without damaging the device. Refer to the Absolute Maximum Ratings table

for more information on the maximum input supported by the device.

8.3.2 Output Enable Control

The CDCDB400 uses SMBus and OE# to control the state of the output channels. The OE# pins control the

state of the output with the same number. For example, the OE3# pin controls the state of the CK3 output driver.

The SMBus registers may enable or disable the output when the corresponding OE# pin is held low.

8.3.3 SMBus

The CDCDB400 has an SMBus interface that is active only when CKPWRGD_PD# = 1. The SMBus allows

individual enable/disable of each output.

When CKPWRGD_PD# = 0, the SMBus pins are placed in a Hi-Z state, but all register settings are retained. The

SMBus register values are only retained while V_DDremains inside of the recommended operating voltage.

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8.3.3.1 SMBus Address Assignment

The SMBus address is assigned by configuring the SADR0 pin which is capable of supporting three levels. This

configuration allows the CDCDB400 to assume three different SMBus addresses.

The SMBus address pin is sampled when PWRGD is set to 1. See 表 8-1 for address pin configuration. The

address can only be changed by power cycling the device.

表 8-1. SMBus Address Assignment

SMBus ADDRESS : WRITE OPERATION

(READ/WRITE=0)

SMBus ADDRESS : READ OPERATION

(READ/WRITE=1)

SADR0

0xD8

0xD9

0xDA

0xDE

0xDB

0xDF

8.4 Device Functional Modes

8.4.1 CKPWRGD_PD# Function

The CKPWRGD_PD# pin is used to set two state variables inside of the device: PWRGD and PD#. The PWRGD

and PD# variables control which functions of the device are active at any time, as well as the state of the input

and output pins.

The PWRGD and PD# states are multiplexed on the CKPWRGD_PD# pin. CKPWRGD_PD# must remain below

V_OLand not exceed V_DDR+ 0.3 V until V_DDand V_DDRare present and within the recommended operating

conditions. After CKPWRGD_PD# is set high, a valid CLKIN must be present to use PD#.

The first rising edge of the CKPWRGD_PD# pin sets PWRGD = 1. After PWRGD is set to 1, the

CKPWRGD_PD# pin is used to assert PD# mode only. PWRGD variable will only be cleared to 0 with the

removal of V_DDand V_DDR

VDD/VDDR

CKPWRGD_PD#

PWRGD

PD#

图 8-1. PWRGD and PD# State Changes

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8.4.2 OE[3:0]# and SMBus Output Enables

Each output channel, 0 to 3, can be individually enabled or disabled by a SMBus control register bit, called

SMB enable bits. Additionally, each output channel has a dedicated, corresponding, OE[3:0]# hardware pin. The

OE[3:0]# pins are asynchronously asserted-low signals that may enable or disable the output.

Refer to 表 8-2 for enabling and disabling outputs through the hardware and software. Note that both the SMB

enable bit must be a 1 and the OEx# pin must be an input low voltage 0 for the output channel to be active.

表 8-2. OE[3:0]# Functionality

Power State Variables

(Internal)

OE[3:0]# HARDWARE PINS AND SMBus

CONTROL REGISTER BITS

Control Inputs

CK[3:0]_P/

CK[3:0]_N

CLKIN

CKPWRGD_P

OUT_EN_CLK[ DRIVE_OP_ST

OE[3:0]#

PWRGD

PD#

3:0]

ATE_CTRL

LOW/LOW

TRI-STATE

LOW/LOW

TRI-STATE

Running

X⁽¹⁾

Running⁽¹⁾

X⁽²⁾

LOW/LOW

TRI-STATE

(1) To enter the power-down state, CLKIN must remain active for at least 3 clock cycles after CKPWRGD_PD# transitions from 1 to 0.

(2) To enter the powered-up state with active clock outputs, CLKIN must be active before CKPWRGD_PD# transitions from 0 to 1.

8.4.3 Output Slew Rate Control

The CDCDB400 provides output slew rate control feature which customer can use to compensate for increased

output trace length based on their board design. The slew rate of the 4 outputs, CK0 to CK3, can be changed

within a given range by a SMBus control register called CAPTRIM. Refer to 表 8-16 for more information.

8.4.4 Output Impedance Control

The integrated termination on the CDCDB400 can be programmed either for 85 Ω or 100 Ω. This flexibility

ensures that the customer can use the same device across various applications irrespective of the characteristic

board impedance which is typically either 85 Ω or 100 Ω. This termination resistor can be changed for all the

outputs as whole using bit 5 of a register called OUTSET. Refer to 表 8-14 for more information.

8.5 Programming

The CDCDB400 uses SMBus to program the states of its four output drivers. See SMBus for more information

on the SMBus programming, and Register Maps for information on the registers.

表 8-3. Command Code Definition

BIT

DESCRIPTION

0 = Block Read or Block Write operation

1 = Byte Read or Byte Write operation

(6:0)

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Peripheral Address

Data Byte

R/W

MSB

LSB

MSB

LSB

Start Condition

Sr Repeated Start Condition

1 = Read (Rd); 0 = Write (Wr)

R/W

Acknowledge (ACK = 0 and NACK =1)

Stop Condition

Controller-to-Peripheral Transmission

Peripheral-to-Controller Transmission

图 8-2. Generic Programming Sequence

Peripheral Address

CommandCode

Data Byte

图 8-3. Byte Write Protocol

Peripheral Address

CommandCode

Peripheral Address

Data Byte

图 8-4. Byte Read Protocol

Peripheral Address

CommandCode

Byte Count = N

Data Byte 0

Data Byte 1

…

Data Byte N-1

图 8-5. Block Write Protocol

Peripheral Address

CommandCode

Peripheral Address

Data Byte N-1

Data Byte N

Data Byte 0

图 8-6. Block Read Protocol

t_LOW

t_R

t_F

V_IH

V_IL

SMBCLK

SMBDAT

t_{SU_STO}

t_{HD_STA}

t_HIGH

t_{SU_STA}

tt_BUFt

t_{HD_DAT}

t_{SU_DAT}

V_IH

V_IL

图 8-7. SMBus Timing Diagram

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8.6 Register Maps

8.6.1 CDCDB400 Registers

表 8-4 lists the CDCDB400 registers. All register locations not listed in 表 8-4 should be considered as reserved

locations and the register contents should not be modified.

表 8-4. CDCDB400 Registers

Address

Acronym

RCR1

Section

Reserved Control Register 1

Output Enable Control 1

Output Enable Control 2

Output Enable# Pin Read Back

Reserved Control Register 2

Vendor/Revision Identification

Device Identification

OECR1

OECR2

OERDBK

RCR2

VDRREVID

DEVID

BTRDCNT

OUTSET

CAPTRIM

Byte Read Count Control

Output Setting Control

4Ch

Slew Rate Capacitor Cluster 1 & 2

Complex bit access types are encoded to fit into small table cells. 表 8-5 shows the codes that are used for

access types in this section.

表 8-5. CDCDB400 Access Type Codes

Access Type

Read Type

Code

Description

Read

Write Type

Write

Reset or Default Value

-n

Value after reset or the default

value

8.6.1.1 RCR1 Register (Address = 0h) [reset = 47h]

RCR1 is shown in 表 8-6.

Return to the Summary Table.

The RCR1 register contains reserved bits.

表 8-6. RCR1 Register Field Descriptions

Bit

7-4

3-0

Field

Type

Reset

Description

Reserved

Reserved.

R/W

Writing to these bits will not affect the functionality of the device.

8.6.1.2 OECR1 Register (Address = 1h) [reset = FFh]

OECR1 is shown in 表 8-7.

Return to the Summary Table.

The OECR1 register contains bits that enable or disable individual output clock channels [1:0].

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表 8-7. OECR1 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

Reserved

OUT_EN_CLK1

Writing to this bit will not affect the functionality of the device.

This bit controls the output enable signal for output channel CK1_P/

CK1_N.

0h = Output Disabled

1h = Output Enabled

Reserved

R/W

Writing to this bit will not affect the functionality of the device.

Reserved

OUT_EN_CLK0

This bit controls the output enable signal for output channel CK0_P/

CK0_N.

0h = Output Disabled

1h = Output Enabled

Reserved

R/W

Writing to this bit will not affect the functionality of the device.

8.6.1.3 OECR2 Register (Address = 2h) [reset = 0Fh]

OECR2 is shown in 表 8-8.

Return to the Summary Table.

The OECR2 register contains bits that enable or disable individual output clock channels [3:2].

表 8-8. OECR2 Register Field Descriptions

Bit

7-4

Field

Type

R/W

Reset

Description

Reserved

OUT_EN_CLK3

Writing to these bits will not affect the functionality of the device.

Writing to this bit will not affect the functionality of the device.

This bit controls the output enable signal for output channel CK3_P/

CK3_N.

0h = Output Disabled

1h = Output Enabled

Reserved

R/W

Writing to this bit will not affect the functionality of the device.

OUT_EN_CLK2

This bit controls the output enable signal for output channel CK2_P/

CK2_N.

0h = Output Disabled

1h = Output Enabled

8.6.1.4 OERDBK Register (Address = 3h) [reset = 0h]

OERDBK is shown in 表 8-9 .

Return to the Summary Table.

The OERDBK register contains bits that report the current state of the OE[3:0]# input pins.

表 8-9. OERDBK Register Field Descriptions

Bit

Field

Type

Reset

Description

RB_OEZ3

RB_OEZ2

Reserved

RB_OEZ1

Reserved

This bit reports the logic level present on the OE3# pin.

This bit reports the logic level present on the OE2# pin.

Reserved.

5-4

This bit reports the logic level present on the OE1# pin.

Reserved.

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表 8-9. OERDBK Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

RB_OEZ0

Reserved

This bit reports the logic level present on the OE0# pin.

Reserved.

8.6.1.5 RCR2 Register (Address = 4h) [reset = 0h]

RCR2 is shown in 表 8-10.

Return to the Summary Table.

The RCR2 register contains reserved bits.

表 8-10. RCR2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

Reserved.

8.6.1.6 VDRREVID Register (Address = 5h) [reset = 0Ah]

VDRREVID is shown in 表 8-11.

Return to the Summary Table.

The VDRREVID register contains a vendor identification code and silicon revision code.

表 8-11. VDRREVID Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

REV_ID

Silicon revision code.

Silicon revision code bits

[3:0] map to register bits

[7:4] directly.

3-0

VENDOR_ID

Vendor identification code.

Vendor ID bits

[3:0] map to register bits

[3:0] directly.

8.6.1.7 DEVID Register (Address = 6h) [reset = E7h]

DEVID is shown in 表 8-12.

Return to the Summary Table.

The DEVID register contains a device identification code.

表 8-12. DEVID Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DEV_ID

E7h

Device ID code.

Device ID bits[7:0] map to register bits[7:0] directly.

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8.6.1.8 BTRDCNT Register (Address = 7h) [reset = 8h]

BTRDCNT is shown in 表 8-13.

Return to the Summary Table.

The BTRDCNT register contains bits [4:0] which configure the number of bytes which will be read back.

表 8-13. BTRDCNT Register Field Descriptions

Bit

7-5

Field

Type

R/W

Reset

Description

Reserved

Writing to these bits will not affect the functionality of the device.

BYTE_COUNTER

Writing to this register configures how many bytes will be read back.

3-0

8.6.1.9 OUTSET Register (Address = 8h) [reset = 0h]

OUTSET is shown in 表 8-14.

Return to the Summary Table.

Bit5 of the OUTSET register sets the termination for all the outputs while bit4 can be used to set the power-down

state for all outputs. The remaining bits for this register are reserved.

表 8-14. OUTSET Register Field Descriptions

Bit

7-6

Field

Type

Reset

Description

Reserved

Reserved.

CH_ZOUT_SEL

d_DRIVE_OP_STATE_CTRL

R/W

Select between 85 Ω (0) and 100 Ω (1) Output impedance

Power-down state of all output clocks.

0: LOW/LOW

1: TRI_STATE

3-0

Reserved

R/W

will affect device functionality.

8.6.1.10 CAPTRIM Register (Address = 4Ch) [reset = 66h]

CAPTRIM is shown in 表 8-16.

Return to the Summary Table.

Bits [7:4] of the CAPTRIM register is used to control the slew rate for output channel cluster 2. Bits [3:0] control

the slew rate for output channel cluster 1. Refer below for cluster identification.

表 8-15. Cluster Identification

Cluster

Outputs

CK1, CK0

CK3, CK2

表 8-16. CAPTRIM Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

CLUSTER2_CAP_TRIM

R/W

Slew Rate Reduction Cap Trim for Cluster 2 Default value of 6h.

0: minimum

F: maximum

3-0

CLUSTER1_CAP_TRIM

R/W

Slew Rate Reduction Cap Trim for Cluster 1. Default value of 6h.

0: minimum

F: maximum

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9 Application and Implementation

备注

以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The CDCDB400 is a fanout buffer that supports PCIe generation 4 and PCIe generation 5 REFCLK distribution.

The device is used to distribute up to four copies of a typically 100-MHz clock.

9.2 Typical Application

图 9-1 shows a CDCDB400 typical application. In this application, a clock generator provides a 100-MHz

reference to the CDCDB400 which then distributes that clock to PCIe endpoints. The clock generator may be

a discrete clock generator like the CDCI6214 or it may be integrated in a larger component such as a Platform

Controller Hub (PCH) or application processor.

PCIe PHY

PCIe Device

PCIe Gen 4-5

Clock

Generator

LP-HCSL

CDCDB400

4x LP-HSCL Output Buffer

LP-HCSL

OE#

Control

SMBus

Control

Control Interface

图 9-1. Typical Application

9.2.1 Design Requirements

Consider a typical server motherboard application which must distribute a 100-MHz PCIe reference clock from

the PCH of a processor chipset to multiple endpoints. An example of clock input and output requirements is:

•

Clock Input:

– 100-MHz LP-HCSL

•

Clock Output:

– 2x 100-MHz to processors, LP-HCSL

– 1x 100-MHz to riser/retimer, LP-HCSL

– 1x 100-MHz to DDR memory controller, LP-HCSL

9.2.2 Detailed Design Procedure

The following items must be determined before starting design of a CDCDB400 socket:

•

Output Enable Control Method

SMBus address

9.2.2.1 Output Enable Control Method

The device provides an option to either use SMBus programmed registers (software) to control the outputs or

by using the hardware OE# pins. When using software to control the outputs, the hardware OE# pins can be

left floating as each of these pins have a pulldown to ground. Refer to 表 8-2 and Register Maps for more

information on programming the register.

When the user wants to control the outputs with the hardware OE# pins, they can connect these pins to a GPIO

controller and set the outputs to HIGH/LOW (see 表 5-1). Registers OECR1 (表 8-7) and OECR2 (表 8-8) show

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the OUT_EN_CLK3 to OUT_EN_CLK0 bits used to control the outputs. These register bits are set to 1 by default

to ensure that the outputs are "software enabled" and their state is therefore set by hardware OE# pins.

9.2.2.2 SMBus Address

Select a SMBus address from the list of potential addresses in 表 8-1. Place the appropriate pullup or pulldown

resistor on the SADR0 pin as indicated in the table. Ensure the SMBus address is not already in use to avoid

conflict.

9.2.3 Application Curves

图 6-1 in the Typical Characteristics section can be used as both an application curve and a typical

characteristics plot in this example.

The 图 9-2 and 图 9-3 show characterization data for the Output slew rate for various CAPTRIM codes and

across temperature. Customers can use these plots as reference for choosing the appropriate output slew rate

based on their system requirement.

0 - 3.3 V

1 - 3.3 V

2 - 3.3 V

3 - 3.3 V

4 - 3.3 V

5 - 3.3 V

6 - 3.3 V

7 - 3.3 V

8 - 3.3 V

9 - 3.3 V

10 - 3.3 V

11 - 3.3 V

12 - 3.3 V

13 - 3.3 V

120 100

-20

-40

-60

Temperature (èC)

D002

图 9-3. Slew Rate Variation Across Temperature for

图 9-2. Output Slew Rate vs. CAPTRIM Code

Different CAPTRIM Code

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10 Power Supply Recommendations

High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the

additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when

the jitter and phase noise is critical to applications.

Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass

capacitors provide the very low impedance path for high-frequency noise and guards the power-supply system

against induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by

the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, place

the capacitors very close to the power-supply terminals and lay out with short loops to minimize inductance. TI

recommends to insert a ferrite bead between the board power supply and the chip power supply that isolates the

high-frequency switching noises generated by the clock buffer. These beads prevent the switching noise from

leaking into the board supply. It is imperative to choose an appropriate ferrite bead with very low DC resistance

to provide adequate isolation between the board supply and the chip supply, as well as to maintain a voltage at

the supply terminals that is greater than the minimum voltage required for proper operation.

图 10-1 shows the recommended power supply filtering and decoupling method.

3.3 V

VDD

10 ꢀF

0.1 ꢀF 0.1 ꢀF 0.1 ꢀF 0.1 ꢀF 0.1 ꢀF

3.3 V

VDDR

2.2 ꢁ

10 ꢀF

0.1 ꢀF

图 10-1. Power Supply Decoupling

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11 Layout

11.1 Layout Guidelines

The following section provides the layout guidelines to ensure good thermal performance and power supply

connections for the CDCDB400.

In Layout Examples, the CDCDB400 has 85-Ω differential output impedance LP-HCSL format drivers as per

42.5-Ω single-ended impedance to avoid reflections and increased radiated emissions. If 100-Ω output

impedance is enabled, the transmission lines connected to CKx pins should be 100-Ω differential impedance,

50-Ω single-ended impedance. Take care to eliminate or reduce stubs on the transmission lines.

11.2 Layout Examples

图 11-1 through 图 11-3 are printed circuit board (PCB) layout examples that show the application of thermal

design practices and a low-inductance ground connection between the device DAP and the PCB.

图 11-1. PCB Layout Example for CDCDB400, Top layer

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图 11-2. PCB Layout Example for CDCDB400, GND Layer

图 11-3. PCB Layout Example for CDCDB400, Bottom Layer

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12 Device and Documentation Support

12.1 Device Support

12.1.1 TICS Pro

TICS Pro is an offline software tool for EVM programming and also for register map generation to program a

device configuration for a specific application. For TICS Pro, go to https://www.ti.com/tool/TICSPRO-SW.

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI

的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

CDCDB400RHBR

CDCDB400RHBT

ACTIVE

VQFN

RHB

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 105

CDCB400

Samples

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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Addendum-Page 2

PACKAGE MATERIALS INFORMATION

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3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CDCDB400RHBR

CDCDB400RHBT

VQFN

RHB

3000

250

330.0

180.0

12.4

5.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

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3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

CDCDB400RHBR

CDCDB400RHBT

VQFN

RHB

3000

250

367.0

210.0

367.0

185.0

35.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RHB 32

5 x 5, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224745/A

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PACKAGE OUTLINE

RHB0032T

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

5.15

4.85

PIN 1 INDEX AREA

5.15

4.85

0.13 MIN

(0.15)

SECTION A-A

TYPICAL

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

(0.2) TYP

3.45 0.1

EXPOSED

THERMAL PAD

28X 0.5

(0.16) TYP

SYMM

3.5

0.3

0.2

32X

0.1

C A B

0.05

PIN 1 ID

(OPTIONAL)

SYMM

0.52

0.32

(0.355)

TYP

32X

4224744/A 01/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RHB0032T

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.45)

SYMM

32X (0.62)

32X (0.25)

(1.475)

28X (0.5)

SYMM

(4.78)

(

0.2) TYP

VIA

(R0.05)

TYP

(1.475)

(4.78)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL EDGE

EXPOSED METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224744/A 01/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RHB0032T

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.49)

(0.845)

(R0.05) TYP

32X (0.62)

32X (0.25)

28X (0.5)

(0.845)

SYMM

(4.78)

METAL

TYP

SYMM

(4.78)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4224744/A 01/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

CDCDB400RHBR [TI]

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