CDCE72010RGCTG4_技术文档

CDCE72010

www.ti.com.............................................................................................................................................................. SCAS858A–JUNE 2008–REVISED JULY 2009

Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

1

FEATURES

•

Wide Charge-Pump Current Range From

200µA to 3mA

•

High Performance LVPECL, LVDS, LVCMOS

PLL Clock Synchronizer

Dedicated Charge-Pump Supply for Wide

Tuning Voltage Range VCOs

•

Two Reference Clock Inputs (Primary and

Secondary Clock) for Redundancy Support

with Manual or Automatic Selection

Presets Charge-Pump to V_{CC_CP}/2 for Fast

Center-Frequency Setting of VC(X)O,

Controlled Via the SPI Bus

•

Accepts Two Differential Input (LVPECL or

LVDS) References up to 500MHz (or Two

LVCMOS Inputs up to 250MHz) as PLL

Reference

•

SERDES Startup Mode (Depending on VCXO

Range)

Auxiliary Input: Output 9 can Serve as 2nd

VCXO Input to Drive All Outputs or to Serve as

PLL Feedback Signal

•

VCXO_IN Clock is Synchronized to One of Two

Reference Clocks

VCXO_IN Frequencies up to 1.5GHz (LVPECL)

800Mhz for LVDS and 250MHz for LVCMOS

Level Signaling

•

RESET or HOLD Input Pin to Serve as Reset or

Hold Functions

REFERENCE SELECT for Manual Select

Between Primary and Secondary Reference

Clocks

•

Outputs Can be a Combination of LVPECL,

LVDS, and LVCMOS (Up to 10 Differential

LVPECL or LVDS Outputs or up to 20 LVCMOS

Outputs), Output 9 can be Converted to an

Auxiliary Input as a 2nd VC(X)O.

•

POWER DOWN (PD) to Put Device in Standby

Mode

•

Analog and Digital PLL Lock Indicator

Output Divider is Selectable to Divide by 1, 2,

3, 4, 5, 6, 8, 10, 12, 16, 18, 20, 24, 28, 30, 32, 36,

40, 42, 48, 50, 56, 60, 64, 70, or 80 On Each

Output Individually up to Eight Dividers.

(Except for Output 0 and 9, Output 0 Follows

Output 1 Divider and Output 9 Follows Output

8 Divider)

Internally Generated VBB Bias Voltages for

Single-Ended Input Signals

•

Frequency Hold-Over Mode Activated by

HOLD Pin or SPI Bus to Improve Fail-Safe

Operation

•

Input to All Outputs Skew Control

Individual Skew Control for Each Output with

Each Output Divider

•

SPI Controllable Device Setting

Individual Output Enable Control via SPI

Interface

•

Packaged in a QFN-64 Package

ESD Protection Exceeds 2kV HBM

Industrial Temperature Range of –40°C to 85°

•

Integrated On-Chip Non-Volatile Memory

(EEPROM) to Store Settings without the Need

to Apply High Voltage to the Device

APPLICATIONS

•

Optional Configuration Pins to Select Between

Two Default Settings Stored in EEPROM

•

Low Jitter Clock Driver for High-End Telecom

and Wireless Applications

Efficient Jitter Cleaning from Low PLL Loop

Bandwidth

•

High Precision Test Equipment

•

Very Low Phase Noise PLL Core

Programmable Phase Offset (Input Reference

to Outputs)

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CDCE72010

SCAS858A–JUNE 2008–REVISED JULY 2009.............................................................................................................................................................. www.ti.com

DESCRIPTION

The CDCE72010 is a high-performance, low phase noise, and low skew clock synchronizer that synchronizes a

VCXO (Voltage Controlled Crystal Oscillator) or VCO (Voltage Controlled Oscillator) frequency to one of two

reference clocks. The clock path is fully programmable providing the user with a high degree of flexibility. The

following relationship applies to the dividers:

Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (P*N)/(R*M)

The VC(X)O_IN clock operates up to 1.5GHz through the selection of external VC(X)O and loop filter

components. The PLL loop bandwidth and damping factor can be adjusted to meet different system

requirements.

The CDCE72010 can lock to one of two reference clock inputs (PRI_REF and SEC_REF) and supports

frequency hold-over mode for fail-safe and system redundancy. The outputs of the CDCE72010 are user

definable and can be any combination of up to 10 LVPECL/LVDS outputs or up to 20 LVCMOS outputs. The

built-in synchronization latches ensure that all outputs are synchronized for very low output skew.

All device settings, including output signaling, divider value selection, input selection, and many more, are

programmable with the SPI (4-wire Serial Peripheral Interface). The SPI allows individual control of the device

settings.

The device operates in a 3.3V environment and is characterized for operation from –40°C to +85°C.

U0P

U0N

U1P

Output Divider 1

U1N

PRI_IN

Feedback

Divider

U2P

U2N

PFD

Output Divider 2

Output Divider 3

Output Divider 4

SEC_IN

U3P

U3N

Charge

Pump

U4P

U4N

VCXO/ VCO IN

U5P

U5N

Output Divider 5

Output Divider 6

Output Divider 7

Output Divider 8

PLL_LOCK

REF_SEL

POWER DOWN

RESET or HOLD

U6P

U6N

Interface

& Control

MODE_SEL

AUX_SEL

U7P

U7N

EEPROM

SPI_MISO

SPI_LE (CD1)

SPI_CLK (CD2)

U8P

U8N

SPI_MOSI (CD3)

U9P or AUX IN+

Auxiliary Input

U9N or AUX IN–

Figure 1. High Level Block Diagram of the CDCE72010

2

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CDCE72010

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PACKAGE

The CDCE72010 is available in a 64-pin lead-free “green” plastic quad flatpack package with enhanced bottom

thermal pad for heat dissipation. The Texas Instruments package designator is RGC (S-PQFP-N64).

48

33

32

49

Bottom View

Top View

64

17

1

16

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

5,8,11,14,19

22,25,28,31

34,37,40, and

43

3.3V supply for the output buffers. There is no internal connection between V_CCand AV_CC

It is recommended that each V_CCuses its own supply filter.

.

VCC

Power

VCC_PLL

VCC_IN

4, 63

57, 60

51, 54

32

A. Power 3.3V PLL supply voltage for the PLL circuitry.

A. Power 3.3V reference input buffers and circuitry supply voltage.

A. Power 3.3V VCXO input buffer and circuitry supply voltage.

Ground Ground connected to thermal pad internally.

VCC_VCXO

GND

PAD

Ground Ground on thermal pad. See layout recommendations.

A. Power 3.3V for internal analog circuitry power supply

VCCA

48, 49

A.

GND_CP

VCC_CP

SPI_MISO

2

Analog ground for charge pump

Ground

Charge pump power supply pin used to have the same supply as the external VCO/VCXO.

It can be set from 2.3V to 3.6V.

64

15

A. Power

DO

In SPI mode it is an open drain output and it functions as a master and in slave out as a

serial control data output from the CDCE72010.

LVCMOS input, control latch enable for the Serial Programmable Interface (SPI), with

hysteresis in SPI mode.

In configuration default mode this pin becomes CD1.

SPI_LE

or CD1

45

46

44

I

SPI_CLK

or CD2

LVCMOS input, serial control clock input for the SPI bus interface, with hysteresis. In

configuration default mode this pin becomes CD2.

LVCMOS input, master out slave in as a serial control data input to CDCE72010 for the SPI

bus interface. In configuration default mode this pin becomes CD3 and it should be tied to

GND.

SPI_MOSI

or CD3

SPI MODE = H; when driven high or left unconnected, it defaults to SPI bus interface mode.

CD MODE = L; If tied low the device goes into configuration default mode which is

configured by CD1, CD2, CD3, and AUX_SEL (CTRL_LE, CTRL_CLK, and CTRL_MOSI).

In configuration default mode the device loads various configuration defaults from the

EEPROM into memory at start-up.

MODE_SEL

16

I

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TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

This pin is used in CD mode only. If set to “1” or left unconnected, it disables output 9 and

enables the AUXILIARY input to drive all outputs from output0 to output8 depending on the

EEPROM configuration. If driven low in CD mode, it enables output 9 and makes all outputs

driven by the VCXO Input depending on the internal EEPROM configuration.

AUX_SEL

18

I

If Auto Reference Select mode is OFF, this pin acts as an External Input Reference Select

Pin;

The REF_SEL signal selects one of two input clocks:

REF_SEL [1]: PRI_REF is selected;

REF_SEL [0]: SEC_REF is selected;

The input has an internal 150-kΩ pullup resistor and if left unconnected it will default to

logic level “1”.

If Auto Reference Select mode in ON, this pin not used.

REF_SEL

47

17

I

This pin is active low and can be activated externally or by the corresponding bit in the SPI

register (in case of logic high, the SPI setting is valid).

This pin switches the device into powerdown mode

POWER_DOWN

The input has an internal 150-kΩ pullup resistor and if left unconnected it will default to

logic level “1”.

This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET is the

default function. This pin is active low and can be activated external or via the

corresponding bit in the SPI register.

In the case of RESET, the CP (Charge Pump) is switched to 3-state and all counters are

reset to zero. The LVPECL outputs are static low (N) and high (P) respectively, and the

LVCMOS outputs are all low or high if inverted. In the case of HOLD, the CP (Charge

Pump) is switched into 3-state mode only. After HOLD is released and with the next valid

reference clock cycle, the charge pump is switched back into normal operation (CP stays in

3-state as long as no reference clock is valid). During HOLD, all outputs are at normal

operation. This mode allows external control of “frequency hold-over” mode. The input has

an internal 150-kΩ pullup resistor.

RESET or HOLD

33

I

VCXO IN+

VCXO IN–

53

52

I

VCXO input (+) for LVPECL+, LVDS+, and LVCMOS level inputs.

Complementary VCXO input for LVPECL-, LVDS- inputs. In the case of a LVCMOS level

input on VCXO IN+, ground this pin.

Universal input buffer (LVPECL, LVDS, LVCMOS) positive input for the Primary Reference

Clock.

PRI REF+

PRI REF–

SEC REF+

SEC REF–

TESTOUTA

STATUS

59

58

62

61

1

I

Universal input buffer (LVPECL, LVDS) negative input for the Primary Reference Clock. In

the case of LVCMOS signaling, ground this pin.

I

Universal input buffer (LVPECL, LVDS, LVCMOS) positive input for the Secondary

Reference Clock.

I

Universal input buffer (LVPECL, LVDS,) negative input for the Secondary Reference Clock.

In the case of LVCMOS signaling, ground this pin.

I

A

Analog Test Point for TI internal testing. Connect a 1kΩ pull-down resistor or leave

unconnected.

LVCMOS output for TI internal testing. Leave unconnected unless it is configured as the

IREF_CP pin. In this case it should be connected to a 12-kΩ resistor to GND.

55

AO/O

CP_OUT

VBB

3

AO

Charge pump output

56

Internal voltage bias analog output

LVCMOS output for PLL_LOCK information. This pin is set high if the PLL is in lock. This

output can be programmed to be a digital lock detect or analog lock detect (see description

of Analog Lock). The PLL is locked (set high), if the rising edge of either the PRI_REF or

SEC_REF clock and the VCXO_IN clock at the PFD (Phase Frequency Detector) are inside

the lock detect window for a predefined number of successive clock cycles.

The PLL is out-of-lock (set low), if the rising edge of either the PRI_REF or SEC_REF clock

and the VCXO_IN clock at the PFD are outside the lock detect window.

PLL_LOCK

50

AI/O

The lock detect window and the number of successive clock cycles are user definable (via

the SPI interface).

4

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TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

U0P:U0N

U1P:U1N

U2P:U2N

U3P:U3N

U4P:U4N

U5P:U5N

U6P:U6N

U7P:U7N

U8P:U8N

7,6

10,9

13,12

21,20

24,23

27,26

30,29

36,35

39,38

The main outputs of the CDCE72010 are user definable and can be any combination of up

to 9 LVPECL outputs, 9 LVDS outputs, or up to 18 LVCMOS outputs. The outputs are

selectable via the SPI interface. The power-up setting is EEPROM configurable.

O

Positive universal output buffer 9 can be 3-stated and used as a positive universal auxiliary

input buffer (It requires external termination). The auxiliary input signal can be routed to

drive the outputs or the feedback loop to the PLL.

U9P or AUXINP

U9N or AUXINN

42

41

I/O

Negative universal output buffer 9 can be 3-stated and used as a negative universal

auxiliary input buffer (It requires external termination). The auxiliary input signal can be

routed to drive the outputs or the feedback loop to the PLL.

PACKAGE THERMAL RESISTANCE FOR QFN (RGZ) PACKAGE⁽¹⁾⁽²⁾

AIRFLOW

(LFM)

θ_JP(°C/W)⁽³⁾

θ_JA(°C/W)

0

JEDEC compliant board (6×6 VIAs on PAD)

Recommended layout (10×10 VIAs on PAD)

1.5

28

100

0

17.6

22.8

13.8

100

(1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

(2) Connected to GND with 9 thermal vias (0.3 mm diameter).

(3) θ_JP(Junction – Pad) is used for the QFN package, because the main heat flow is from the junction to the GND-pad of the QFN.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

MIN

–0.5

MAX

4.6

UNIT

V_CC

AV_CC

V_{CC_CP}

,

Supply voltage range⁽¹⁾

V

V_I

Input voltage range⁽²⁾

Output voltage range⁽²⁾

–0.5 V_CC+ 0.5

V

V_O

–0.5 V_CC+ 0.5

Input current

V_I< 0, V_I> V_CC

0 < V_O< V_CC

±20

±50

125

mA

°C

Output current for LVPECL/LVCMOS Outputs

Junction temperature

T_J

T_stg

Storage temperature range

–65

150

(1) All supply voltages have to be supplied simultaneously.

(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

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CDCE72010

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RECOMMENDED OPERATING CONDITIONS

for the CDCE72010 device for under the specified industrial temperature range of –40°C to 85°C

MIN

NOM

3.3

MAX

3.6

UNIT

Power Supply

V_CC

Supply voltage

3

V

V_{CC_PLL}

V_{CC_IN}

V_{CC_VCXO}

V_CCA

,

Analog supply voltage

3

3.3

3.6

,

V_{CC_CP}

2.3

V_CC

V

REF at 30.72MHz VCXO at

491.52MHz Outputs are

LVPECL-HS

Divider 1 set to divide by 8 (DCR

30%) Divider 2 set to divide by 4

(DCR 30%) Divider 3 set to divide

by 2 (DCR 30%) Divider 4 set to

divide by 2 (DCR 30%) Divider 5

set to divide by 1 (DCR 30%)

Divider 6 set to divide by 1 (DCR

0%) Divider 7 set to divide by 1

(DCR 0%) Divider 8 set to divide by

1 (DCR 0%) DCR: Divider Current

Reduction Setting

P _LVPECL

2.9

2.0

W

REF at 30.72MHz VCXO at

491.52MHz Outputs are LVDS-HS

P _LVDS

W

REF at 30.72MHz VCXO at

122.88MHz Outputs are LVCMOS

P _LVCMOS

2.2

REF at 30.72MHz VCXO at

491.52MHz

Dividers are disabled. Outputs are

disabled.

P _OFF

P _PD

775

30

mW

Device is powered down

Typical Operating Conditions at V_CC=3.3V and 25°C unless otherwise specified.

Differential Input Mode (PRI_REF, SEC_REF, VCXO_IN and AUX_IN)

V_INPP

V_ICM

Input amplitude⁽¹⁾

(V_{_INP}– V_INN

)

0.1

1.0

1.3

V

Common-mode input voltage

V_CC– 0.3

Differential input current high ( No

internal termination)

I_IH

I_IL

V_I= V_CC, V_CC= 3.6 V

V_I= 0 V, V_CC= 3.6 V

20

µA

Differential input current low( No

internal termination)

–20

Input capacitance on PRI_REF, SEC_REF and VCXO_REF

Input capacitance on AUX_IN

3

7

pF

LVCMOS Input Mode (SPI_CLK, SPI_MOSI, SPI_LE, PD, RESET, REF_SEL, MOD_SEL)

V_IL

V_IH

V_IK

I_IH

Low-level input voltage LVCMOS⁽²⁾

High-level input voltage LVCMOS⁽²⁾

LVCMOS input clamp voltage

LVCMOS input current

0

0.3 V_CC

V_CC

V

0.7 V_CC

V_CC= 3 V, II = –18 mA

V_I= V_CC, V_CC= 3.6 V

V_I= 0 V, V_CC= 3.6 V

–1.2

20

V

µA

I_IL

LVCMOS input

–10

–40

C_I

Input capacitance (LVCMOS

signals)

V_I= 0 V or V_CC

3

pF

(1) V_INPPminimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum V_INPPof

150mV.

(2) V_ILand V_IHare required to maintain ac specifications; the actual device function tolerates a smaller input level of 1V, if an AC coupling

to V_CC/2 is provided.

6

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TIMING REQUIREMENTS

over recommended ranges of supply voltage, load, and operating free-air temperature^(1)(2)(3)(4)

PARAMETER

MIN

TYP

MAX

UNIT

PRI_REF/SEC_REFIN

f_{REF - Single}

For single-ended inputs ( LVCMOS) on PRI_REF and SEC_REF

250

500

MHz

For differential inputs (LVDS and LVPECL) on PRI_REF and

SEC_REF

f_{REF - Diff}

(R divider set to DIV2)

Duty Cycle

Single

60%

Duty cycle of PRI_REF or SEC_REF at V_CC/2

40%

Duty Cycle

Diff

60%

VCXO_IN, AUX_IN

f_{REF - Single}For single-ended inputs ( LVCMOS)

f_{REF - Diff}

250

1500

60%

MHz

For differential inputs (LVDS and LVPECL)

Duty cycle of PRI_REF or SEC_REF at V_CC/2

Duty Cycle

Single

40%

Duty Cycle

Diff

Duty cycle of PRI_REF or SEC_REF at V_CC/2

60%

20

SPI/Control (SPI Bus Timing)

f_{CTRL_CLK}

CTRL_CLK frequency

MHz

ns

t2

t3

t4

t5

t1

t6

t7

t8

SPI_MOSI to SPI_CLK setup time

SPI_MOSI to SPI_CLK hold time

SPI_CLK high duration

10

25

10

20

10

ns

SPI_CLK low duration

ns

SPI_LE to SPI_CLK setup time

SPI_CLK to SPI_LE setup time

SPI_LE pulse width

ns

SPI_MISO to SPI_CLK data valid (first valid bit after LE)

ns

PD, RESET, Hold, REF_SEL

Rise and fall time of the PD, RESET, Hold, REF_SEL signal from 20%

to 80% of V_CC

(1) From 250MHz to 500MHz is achieved by setting the divide by 2 in P’

t_r/t_f

4

ns

(2) If the feedback clock (derived from the VCXO input) is less than 2MHz, the device stays in normal operation mode but the frequency

detection circuitry resets the STATUS_VCXO signal and PLL_LOCK signal to low. Both status signals are no longer relevant. This

affects the HOLD-Over-Function as well as the PLL_LOCK signal is no longer valid.

(3) Use a square wave for lower frequencies (< 80 MHz).

(4) Slew rate requirement

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AC/DC CHARACTERISTICS

over the specified industrial temperature range of –40°C to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX UNIT

SPI Output (MISO) / PLL Digital (Output Mode)

I_OH

I_OL

High-level output current

Low-level output current

V_CC= 3.3 V

V_O= 1.65 V

–30

33

mA

High-level output voltage

for LVCMOS outputs

V_OH

V_OL

C_O

V_CC= 3 V

I_OH= –100 µA

I_OL= 100 µA

V_CC–0.5

V

Low-level output voltage

for LVCMOS outputs

0.3

V

Output capacitance on

MISO

V_CC= 3.3 V; VO = 0 V or V_CC

3

pF

I_OZH

I_OZL

3-state output current

5

µA

V_O= V_CC

V_O= 0V

–5

PLL Analog (Input Mode)

High-impedance state

I_OZHLOCK output current for PLL

V_O= 3.3 V (PD is set low)

V_O= 0 V (PD is set low)

22

µA

(2)

LOCK output

High-impedance state

I_OZLLOCK output current for PLL

LOCK output

–22

Positive input threshold

voltage

V_T+

V_CC= min to max

V_CC× 0.55

V_CC× 0.35

V

Negative input threshold

voltage

V_T–

VBB

VCXO termination voltage

depends on the settings

of the VCXO/AUX_IN

IBB = –0.2mA

Depending on the setting

VBB

0.9

1.9

V

input buffers

Input Buffers Internal Termination Resistors (VCXO_IN,PRI_REF and SEC_REF)

Termination resistance⁽³⁾Single ended

Phase Detector

53

Ω

Maximum charge pump

frequency

f_CPmax

Default PFD pulse width delay

100

MHz

Charge Pump

Charge pump 3-state

current

ICP3St

0.5 V < VCP < V_{CC_CP}– 0.5 V

15

20

5

nA

%

ICPA

ICP absolute accuracy

V_CP= 0.5 V_{CC_CP}; internal reference resistor

VCP = 0.5 V_{CC_CP}; external reference resistor

12kΩ (1%)

ICPA

ICP absolute accuracy

%

Sink/source current

matching

0.5 V < VCP < V_{CC_CP}– 0.5 V, SPI default

settings

ICPM

4

6

%

IVCPM

ICP vs VCP matching

0.5 V < VCP < V_{CC_CP}– 0.5 V

Voltage on STATUS PIN 12-kΩ resitor to GND

V_{I_REF_CP}

when configured as

I_REF_CP

(External current path for accurate charge

pump current)

1.24

V

(1) All typical values are at V_CC= 3.3 V, T_A= 25°C.

(2) 160-kΩ pull-down resistor

(3) Termination resistor can vary by 20%.

8

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AC/DC CHARACTERISTICS (CONTINUED)

over the specified industrial temperature range of –40°C to 85°C

PARAMETER

LVCMOS Output

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX UNIT

Output frequency (see

Figure 2 )

f_clk

Load = 5 pF to GND

250

0.3

MHz

V

High-level output voltage

for LVCMOS outputs

V_OH

V_OL

V_CC= min to max

I_OH= –100 µA

I_OL=100 µA

V_CC– 0.5

Low-level output voltage

for LVCMOS outputs

V

I_OH

I_OL

High-level output current

Low-level output current

V_CC= 3.3 V

V_CC= 3.3 V,

V_O= 1.65 V

–30

33

mA

Phase offset without

using available delay

adjustment

VCXO at 491.52MHz, Output 1 is divide by

16 and reference at 30.72MHz, M and N

delays are fixed to one value (set to 0).

t_pho

13

ns

t_pd(LH)

tpd(HL)

/

Propagation delay from

VCXO_IN to Outputs

Crosspoint to V_CC/2, load = 5 pF, (PLL

bypass mode)

3.3

Divide by 1 for all dividers

Divide by 16 for all dividers

75

Skew, output-to-output

LVCMOS single-ended

output

t_sk(o)

ps

Divide by 1 for divider 1 divide by 16 for all

other dividers

1400

Output capacitance on Y0

to Y8

C_O

V_CC= 3.3 V; V_O= 0 V or V_CC

5

pF

µA

C_O

Output capacitance on Y9 V_CC= 3.3 V; V_O= 0 V or V_CC

3-state LVCMOS output

V_O= V_CC

I_OZH

current

3-state LVCMOS output

V_O= 0V

I_OZL

–5

µA

current

Power-down output

V_O= V_CC

I_OPDH

I_OPDL

25

5

current

Power-down output

V_O= 0V

current

Duty cycle

t_slew-rate

LVCMOS

50% to 50%

45

55

%

Output rise/fall slew rate

3.6

5.2

V/ns

(1) All typical values are at V_CC= 3.3 V, T_A= 25°C.

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AC/DC CHARACTERISTICS (CONTINUED)

over the specified industrial temperature range of –40°C to 85°C

PARAMETER

LVDS Output

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX UNIT

f_clk

Output frequency

Open loop config. load, See Figure 2

0

800

270

MHz

mV

|V_OD

|

Differential output voltage R_L= 100 Ω

160

LVDS VOD magnitude

change

Δ_VOD

50

mV

V_OS

Offset voltage

–40°C to 85°C

V_OUT= 0

1.24

40

V

ΔV_OS

V_OSmagnitude change

mV

Short circuit V_OUT+to

ground

27

mA

Short circuit V_OUT–to

ground

V_OUT= 0

Reference to output

VCXO at 491.52MHz, Output 1 is divide by

phase offset without using 16 and reference at 30.72MHz, M and N

(2)

t_pho

14

ns

available delay

adjustment

delays are fixed to one value (set to 0), PFD:

240kHz, (M and N = 128)

t_pd(LH)

/

Propagation delay time,

VCXO_IN to output

Crosspoint to crosspoint, load, see Figure 2

3.0

t_pd(HL)

Divide by 1 for all dividers

Divide by 16 for all dividers

45

50

Skew, output to output

LVDS output

tsk(o)⁽³⁾

ps

Divide by 1 for divider 1

Divide by 16 for all other dividers

2800

Output capacitance on Y0

to Y8

C_O

V_CC= 3.3 V; V_O= 0 V or V_CC

5

7

pF

µA

C_O

Output capacitance on Y9 V_CC= 3.3 V; V_O= 0 V or V_CC5

Power-down output

V_O= V_CC

I_OPDH

25

5

current

Power-down output

V_O= 0V

I_OPDL

µA

current

Duty cycle

45

55

%

t_r/t_f

LVCMOS-TO-LVDS⁽⁴⁾

Output skew between

Rise and fall time

20% to 80% of V_outpp

Crosspoint to V_CC/2

110

140

1.4

160

ps

tsk_{P_C}

LVCMOS and LVDS

outputs

0.9

1.9

ns

(1) All typical values are at V_CC= 3.3 V, T_A= 25°C.

(2) This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M and

VCXO delay N).

(3) The tsk(o) specification is only valid for equal loading of all outputs.

(4) Operating the LVCMOS or LVDS outputs above the maximum frequency will not cause a malfunction to the device, but the output signal

swing may no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS.

10

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AC/DC CHARACTERISTICS (CONTINUED)

over the specified industrial temperature range of –40°C to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX UNIT

LVDS Hi Swing Output

f_clk

Output frequency

Open loop config. load, seeFigure 3

0

800

550

MHz

mV

|V_OD

|

Differential output voltage R_L=100 Ω

270

LVDS VOD magnitude

change

Δ_VOD

50

mV

V_OS

Offset voltage

–40°C to 85°C

1.24

40

V

ΔV_OS

V_OSmagnitude change

mV

Short Circuit V_OUT+to

ground

V_OUT= 0

27

mA

Short Circuit V_OUT–to

ground

V_OUT= 0

Reference to output

VCXO at 491.52MHz, Output 1 is divide by

phase offset without using 16 and reference at 30.72MHz. M and N

(2)

t_pho

14

ns

available delay

adjustment

delays are fixed to one value. (Set to 0) PFD:

240kHz, (M and N = 128)

t_pd(LH)

t_pd(HL)

/

Propagation delay time,

VCXO_IN to output

Crosspoint to crosspoint, load Figure 3

3.0

Divide by 1 for all dividers

Divide by 16 for all dividers

45

50

(3)

t_sk(o)

LVDS output skew

ps

Divide by 1 for divider 1

Divide by 16 for all other dividers

2800

Output capacitance on Y0

to Y8

C_O

V_CC= 3.3 V; V_O= 0 V or V_CC

5

7

pF

µA

Output capacitance on Y9 V_CC= 3.3 V; V_O= 0 V or V_CC

Power-down output

V_O= V_CC

IOPDH

IOPDL

25

5

current

Power-down output

V_O= 0V

µA

current

Duty cycle

t_r/t_f

LVCMOS-TO-LVDS⁽⁴⁾

45

55

%

Rise and fall time

20% to 80% of V_outpp

Crosspoint to V_CC/2

110

160

1.4

190

ps

Output skew between

LVCMOS and LVDS

outputs

tsk_{P_C}

0.9

1.9

ns

(1) All typical values are at V_CC= 3.3 V, T_A= 25°C.

(2) This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M and

VCXO delay N).

(3) The tsk(o) specification is only valid for equal loading of all outputs.

(4) Operating the LVCMOS or LVPECL outputs above the maximum frequency will not cause a malfunction to the device, but the output

signal swing may no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS.

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AC/DC CHARACTERISTICS (CONTINUED)

over the specified industrial temperature range of –40°C to 85°C

PARAMETER

LVPECL Output

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX UNIT

f_clk

Output frequency

Open loop config.

0

1500

MHz

V

LVPECL high-level output

voltage

V_OH

Load, see Figure 5

V_CC– 1.06

V_CC– 0.88

LVPECL low-level output

voltage

V_OL

V_CC– 2.02

610

V_CC– 1.58

970

V

|VOD|

Differential output voltage Load, see Figure 5

mV

Reference to output

VCXO at 491.52MHz, Output 1 is divide by

phase offset without using 16 and reference at 30.72MHz, M and N

(2)

t_pho

14

ns

available delay

adjustment

delays are fixed to one value (set to 0), PFD:

240kHz, (M and N = 128)

t_pd(LH)

t_pd(HL)

/

Propagation delay time,

VCXO_IN to output

Crosspoint to crosspoint, load, see Figure 5

3.4

Divide by 1 for all dividers

Divide by 16 for all dividers

45

50

(3)

t_sk(o)

LVPECL output skew

ps

Divide by 1 for divider 1

Divide by 16 for all other dividers

2700

Output capacitance on Y0

to Y8

C_O

V_CC= 3.3 V; V_O= 0 V or V_CC

5

7

pF

µA

C_O

Output capacitance on Y9 V_CC= 3.3 V; V_O= 0 V or V_CC

Power-down output

V_O= V_CC

IOPDH

25

5

current

Power-down output

V_O= 0 V

IOPDL

µA

current

Duty cycle

45

55

%

t_r/t_f

Rise and fall time

20% to 80% of V_outpp

Crosspoint to V_CC/2;

75

135

ps

LVDS-TO-LVPECL

Output skew between

tsk_{P_C}

LVDS and LVPECL

outputs

0.9

1.1

1.3

ns

ps

LVCMOS-TO-LVPECL

Output skew between

tsk_{P_C}

LVCMOS and LVPECL

Crosspoint to V_CC/2;

–150

260

700

outputs⁽⁴⁾

(1) All typical values are at V_CC= 3.3 V, T_A= 25°C.

(2) This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M and

VCXO delay N).

(3) The tsk(o) specification is only valid for equal loading of all outputs. :

(4) Operating the LVCMOS or LVPECL outputs above the maximum frequency will not cause a malfunction to the device, but the output

signal swing might no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS.

12

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AC/DC CHARACTERISTICS (CONTINUED)

over the specified industrial temperature range of –40°C to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

UNIT

LVPECL Hi Swing Output

f_clk

Output frequency

Open loop config.

0

1500

MHz

V

LVPECL high-level

output voltage

V_OH

Load, see Figure 5

V_CC– 1.11

V_CC– 0.87

LVPECL low-level output

voltage

V_OL

V_CC– 2.06

760

V_CC– 1.73

1160

V

Differential output

voltage

|VOD|

mV

Reference to output

phase offset without

using available delay

adjustment

VCXO at 491.52MHz, Output 1 is divide by 16

and reference at 30.72MHz, M and N delays

are fixed to one value (set to 0), PFD:

240kHz, (M and N = 128)

(2)

t_pho

14

ns

t_pd(LH)

/

Propagation delay time,

VCXO_IN to output

Crosspoint to crosspoint, load, see Figure 5

3.4

t_pd(HL)

Divide by 1 for all dividers

Divide by 16 for all dividers

45

50

(3)

t_sk(o)

LVPECL output skew

ps

Divide by 1 for divider 1

Divide by 16 for all other dividers

2700

Output capacitance on

Y0 to Y8

C_O

V_CC= 3.3 V; V_O= 0 V or V_CC

V_O= V_CC

5

7

pF

µA

Output capacitance on

Y9

Power-down output

current

IOPDH

IOPDL

25

5

Power-down output

current

V_O= 0V

Duty cycle

45

55

%

t_r/t_f

Rise and fall time

20% to 80% of V_outpp

Crosspoint to V_CC/2

75

135

ps

LVDS-TO-LVPECL

Output skew between

tsk_{P_C}

LVDS and LVPECL

outputs

0.9

1.1

1.3

ns

ps

LVCMOS-TO-LVPECL

Output skew between

tsk_{P_C}

LVCMOS and LVPECL

Crosspoint to V_CC/2

–150

260

700

outputs⁽⁴⁾

(1) All typical values are at V_CC= 3.3 V, T_A= 25°C.

(2) This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M and

VCXO delay N).

(3) The tsk(o) specification is only valid for equal loading of all outputs.

(4) Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output

signal swing might no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS and

LVPECL.

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PARAMETER MEASUREMENT INFORMATION

100 W

Oscilloscope

5 pf

LVCMOS

Figure 2. LVCMOS Output Termination Setup

Figure 3. LVDS DC Termination Setup

Oscilloscope

50 W

Oscilloscope

50 W

150 W

50 W

VCC-2

Figure 4. LVPECL AC Termination Setup

Figure 5. LVPECL DC Termination Setup

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TYPICAL CHARACTERISTICS

LVPECL OUTPUT SWING

Hi Swing LVPECL OUTPUT SWING

vs

FREQUENCY

(mV)

1100

(mV)

1250

V_CC= 3.6V

T_A= 25 ºC

Load 50 W to

_CC-2C

T_A= 25 ºC

Load 50 W to

V_CC– 2V

1050

1000

950

900

850

800

750

700

650

600

550

1200

1150

1100

1050

1000

950

V_CC= 3.6V

V

V_CC= 3.3V

V_CC= 3.0V

900

850

V_CC= 3.0V

800

750

Frequency - MHz

200 400 600 800

Figure 6.

Frequency - MHz

700

1000

1200 1400 1600 1800

200 400 600 800 1000

1200 1400 1600 1800

Figure 7.

LVDS OUTPUT SWING

Hi Swing LVDS OUTPUT SWING

vs

FREQUENCY

(mV)

320

(mV)

500

T_A= 25 ºC

Load 100 W

460

420

380

340

300

260

220

180

140

100

60

300

280

260

240

220

V_CC= 3.6V

V_CC= 3.3V

V_CC= 3.6V

200

180

160

140

120

V_CC= 3.0V

T_A= 25 ºC

Load 100 W

Frequency - MHz

100

0

100 200 300 400 500 600 700 800 900

0

Figure 8.

Figure 9.

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TYPICAL CHARACTERISTICS (continued)

LVCMOS OUTPUT WING

vs

FREQUENCY

(V)

4.0

V_C_C= 3.6V

T_A= 25 ºC

Load 5pF

3.8

3.6

V_CC= 3.3V

3.4

3.2

3.0

2.8

2.6

2.4

2.2

V_CC= 3.0V

2.0

Frequency - MHz

1.8

100

200

300

400

500

Figure 10.

16

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APPLICATION INFORMATION

PHASE NOISE ANALYSIS

Phase noise is measured in a closed loop mode of 491.52MHz VCXO and 30.72MHz reference and a 100Hz

loop. Output 1 is measured for divide by one, output 6 for divide by 4, and output 9 for divide by 16.

Table 1. Phase Noise for LVPECL High Swing

Phase Noise Specifications under following configuration: VCXO = 491.52MHz, REF = 30.72MHz, Divide by = 491.52MHz, Divide by

4 = 122.88MHz, Divide by 16 = 30.72MHz, PFD Frequency = 240KHz, Charge Pump Current = 2mA, Loop BW = 100Hz, Output 1 =

491.52 MHZ, Output Buffer: LVPECL-HS

PHASE NOISE

AT OFFSET

VCXO OPEN

LOOP

REFERENCE

30.72MHz

LVPECL-HS

DIVIDE BY 1

LVPECL-HS

DIVIDE BY 4

LVPECL-HS

DIVIDE BY 16

UNIT

10Hz

–64

–99

–107

–123

–134

–153

–156

–158

–80

–92

–105

–116

–139

–158

–162

dBc/Hz

100Hz

1kHz

–104

–127

–145

–155

–156

–113

–135

–148

–149

–115

–135

–146

–147

10kHz

100kHz

1MHz

10MHz

Table 2. Phase Noise for LVDS High Swing

Phase Noise Specifications under following configuration: VCXO = 491.52MHz, REF = 30.72MHz, Divide by = 491.52MHz, Divide by

4 = 122.88MHz, DIvide by 16 = 30.72MHz, PFD Frequency = 240KHz, Charge Pump Current = 2mA Loop BW = 100Hz, Output 1 =

491.52 MHZ, Output Buffer: LVDS-HS

VCXO OPEN

LOOP

LVDS–HS

DIVIDE BY 1

LVDS-HS

DIVIDE BY 4

LVDS-HS

DIVIDE BY 16

PARAMETER

REFERENCE

UNIT

10Hz

–64

–99

–107

–123

–134

–153

–156

–158

–82

–92

–94

–104

–117

–139

–151

–153

dBc/Hz

100Hz

1kHz

–105

–127

–145

–152

–113

–135

–148

–149

–114

–135

–145

–146

10kHz

100kHz

1MHz

10MHz

Table 3. Phase Noise for LVCMOS

Phase Noise Specifications under following configuration: VCXO = 491.52MHz, REF = 30.72MHz, Divide by = 491.52MHz, Divide by

4 = 122.88MHz, DIvide by 16 = 30.72MHz, PFD Frequency = 240KHz, Charge Pump Current = 2mA, Loop BW = 100Hz, Output 1 =

491.52 MHZ, Output Buffer: LVCMOS

VCXO OPEN

LOOP

LVCMOS

DIVIDE BY 4

LVCMOS

DIVIDE BY 16

PARAMETER

REFERENCE

N/A

UNIT

10Hz

–64

–99

–107

–123

–134

–153

–156

–158

–91

–105

–116

–139

–151

–159

–160

dBc/Hz

100Hz

1kHz

–104

–127

–140

–151

–153

–154

–113

–135

–148

–149

10kHz

100kHz

1MHz

10MHz

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SPI CONTROL INTERFACE

The serial interface of the CDCE72010 is a simple bidirectional SPI interface for writing and reading to and from

the registers of the device. It consists of four control lines: SPI_CLK, SPI_MOSI, SPI_MISO, and SPI_LE. There

are twelve 28-bit wide registers that can be saved to the EEPROM on-chip, and one status register that is a read

only register. Those registers can be addressed by the four LSBs of a transferred word (bit 0, 1, 2, and bit 3).

Every transmitted word must have 32 bits, starting with LSB first. Each word can be written separately. The

transfer is initiated with the falling edge of SPI_LE; as long as SPI_LE is high, no data can be transferred. During

SPI_LE low, data can be written. The data has to be applied at SPI_MOSI and has to be stable before the rising

edge of SPI_CLK. The transmission is finished by a rising edge of SPI_LE.

t4

t5

SPI_CLK

SPI_MOSI

SPI_LE

t2

t3

Bit0

Bit1

……

Bit29

Bit30

Bit31

t7

t6

t1

Figure 11. Timing Diagram for SPI Write Command

SPI_CLK

t3

t2

Bit30

Bit31

SPI_MOSI

SPI_MISO

SPI_LE

Bit0

Bit1

Bit2

t7

t6

t8

Figure 12. Timing Diagram for SPI Read Command

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Table 4. Register Map

REGISTER

COMMENTS

WRITE PAYLOAD ( DATA)

ADDRESS

WRITE COMMAND ON MOSI

31,30,29,28….…………..…………………………………….………4,3,2,1,0

Register0

Configuration

Status/Control

Reserved

RAM/EEPROM

XXXX XXXX XXXX XXXX XXXX XXXX XXXX

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

Register1

Register2

Register3

Register4

Register5

Register6

Register7

Register8

Register9

Register10

Register11

Register12

Register13

RAM/EEPROM

RAM Only

Read command (address on 4 LSBs of

payload)

Instruction

XXXX XXXX XXXX XXXX XXXX XXXX AAAA

1110

Instruction

Write configuration to EEPROM - UNLOCKED XXXX XXXX XXXX XXXX XXXX XXXX 0001

1111

Write configuration to EEPROM – LOCKED

XXXX XXXX XXXX XXXX 1010 XXXX 0011

DATA PAYLOAD IN READ COMMAND

READ COMMAND ON MISO

Payload after issuing a read command on

MOSI

DDDD DDDD DDDD DDDD DDDD DDDD DDDD

XXXX⁽¹⁾

(1) During a SPI READ instruction the address field of the payload should be ignored since it does not represent the address of the read

register.

The SPI serial protocol accepts Word Write operation only. The 12 words include the register settings of the

programmable functions of the device that can be modified to the customer application by changing one or more

bits.

At powerup or if the Power Down (PD) control signal is applied, the EEPROM loads its content into the registers.

When issuing an EEPROM programming (LOCKED or UNLOCKED) instruction, a wait period of 50ms has to be

inserted before another instruction is written to the device or power is removed.

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CDCE72010 Default Configuration

The CDCE72010 on-board EEPROM has been factory preset to the default settings listed in Table 5

Table 5. CDCE72010 Default Configuration Settings

REGISTER

REG0000

REG0001

REG0002

REG0003

REG0004

REG0005

REG0006

DEFAULT SETTING

002C0040

REGISTER

REG0007

REG0008

REG0009

REG0010

REG0011

REG0012

DEFAULT SETTING

EB040717

83840051

010C0158

83400002

01000049

83400003

0BFC07CA

C000058B

81800004

81800005

61E09B0C

EB040006

The default configuration programmed in the EEPROM is: a 10MHz primary reference single-ended, a

491.52MHz LVPECL VCXO running at 80kHz, and PFD with a 10Hz external loop filter. Reference Auto Select is

off, M divider is set for 125, N divider is set to 768, charge pump current is set to 2.2mA, and feedback divider is

set to divide by 8. Divider 1 is set to divide by 4, Dividers 2 and 3 are set to divide by 1, Dividers 4 and 5 are set

to divide by 2, Dividers 6 and 7 are set to divide by 8, and Divider 8 is set to divide by 16.Output0:LVCMOS,

Output1:Hi-LVPECL, Output2: Hi-LVPECL, Output3:Hi_LVPECL, Output4:LVPECL, Output5:LVPECL,

Output6:Hi-LVDS, Output7:Hi-LVDS, Output8:LVCMOS and Output9:LVCMOS.

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Register 0: SPI Mode

SPI

BIT

RAM

Bit

POWER UP

CONDITION

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

0

1

2

3

4

5

6

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

0

1

2

INBUFSELX

INBUFSELY

PRISEL

Reference Input

Buffers

Primary and secondary Buffer Type Select (LVPECL,LVDS or LVCMOS)

XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive pin

EEPROM

When REFSELCNTRL is set to 1, the following settings apply:

If RAM Bits (2,3): 00 – No input buffer is selected/active

If RAM Bits (2,3): 10 – PRI_BUF is selected, SEC_BUF is powered down

If RAM Bits (2,3): 01 – SEC_BUF is selected, PRI_BUF is powered down⁽¹⁾

If RAM Bits (2,3): 11 – Auto Select (PRI then SEC).

Reference Input

Buffer

EEPROM

7

8

3

4

SECSEL

When set to 0, PRI- or SEC-clock is selected, depending on bits 2 and 3

(default)

When set to 1, VCXO/AUX-clock is selected, overwrites bits 2 and 3

Divider START

DETERM-Block

VCXOSEL

EEPROM

Reference Select Control to select if the control of the reference is from the

internal bit in Register 0 RAM bits 2 and 3 or from the external select pin.

- When set to 0: the external pin REF_SEL takes over the selection between

PRI and SEC. Autoselect is not available.

- When set to 1: The external pin REF_SEL is ignored. The table in (Register 0

<2 and 3> ) describes which reference input clock is selected and available

(none, PRI, SEC or Autoselect). In autoselect mode, refer to the timing

diagram.

Reference

Selection

Control

9

5

REFSELCNTRL

EEPROM

10

11

12

6

7

8

DELAY_PFD0

DELAY_PFD1

CP_MODE

PFD pulse width PFD bit 0

PFD pulse width PFD bit 1

PFD

Selects 3V option [0] or 5V option [1]

EEPROM

Charge Pump

Determines which direction CP current will regulate (Reference Clock leads to

Feedback Clock, Positive CP output current [0], Negative CP output current [1])

13

14

9

CP_DIR

Switches the current source in the charge pump on when set to 1 (TI

Test-GTME)

10

CP_SRC

EEPROM

Charge Pump

Diagnostics

15

16

17

18

19

20

21

22

23

11

12

13

14

15

16

17

18

19

CP_SNK

CP_OPA

CP_PRE

ICP0

Switches the current sink in the charge pump on when set to 1 (TI Test-GTME)

Switches the charge pump op-amp off when set to 1 (TI Test-GTME)

Preset charge pump output voltage to V_{CC_CP}/2, on [1], off [0]

CP current setting bit 0

EEPROM

ICP1

Charge Pump

CP current setting bit 1

ICP2

CP current setting bit 2

ICP3

CP current setting bit 3

RESERVED

Charge Pump

Diagnostics

Enables the 12-kΩ pull-down resistor at I_REF_CP pin when set to 1 (TI

Test-GTME)

24

20

IREFRES

EEPROM

25

26

27

28

29

21

22

23

24

25

PECL0HISWING

CMOSMODE0PX

CMOSMODE0PY

CMOSMODE0NX

CMOSMODE0NY

Output 0

High output voltage swing in LVPECL mode if set to 1

LVCMOS mode select for OUTPUT 0 positive pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

Output 0

EEPROM

LVCMOS mode select for OUTPUT 0 negative pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

Output 0

RAM BITS

OUTPUT TYPE

30

31

26

27

OUTBUFSEL0X

OUTBUFSEL0Y

22

0

23

0

24

0

25

0

26

0

27

1

EEPROM

LVPECL

LVDS

0

1

0

1

Output 0

LVCMOS

See Settings Above⁽²⁾

0

All Outputs Disabled

0

1

0

1

0

(1) This setting is only available if the Register 11 Bit 2 is set to 0 (Feedback Divider clock is set to CMOS type).

(2) Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs.

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Register 1: SPI Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

0

1

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

1

0

2

0

3

0

4

0

1

ACDCSEL

Input Buffers

If set to 0 AC Termination, If set to 1 DC termination

If set to 1 Input Buffers Hysteresis enabled

EEPROM

5

HYSTEN

6

2

TERMSEL

If set to 0 Input Buffer Internal Termination enabled

7

3

PRIINVBB

If set to 1 Primary Input Negative pin biased with internal VBB voltage

If set to 1 Secondary Input Negative pin biased with internal VBB voltage

If set to 1 Fail Safe is enabled for all input buffers

8

4

SECINVBB

9

5

FAILSAFE

10

11

12

13

14

15

16

17

18

19

20

21

22

23

6

PH1ADJC0

7

PH1ADJC1

8

PH1ADJC2

9

PH1ADJC3

Output 0 and 1

Coarse phase adjust select for Output Divider 1

EEPROM

10

11

12

13

14

15

16

17

18

19

PH1ADJC4

PH1ADJC5

PH1ADJC6

OUT1DIVRSEL0

OUT1DIVRSEL1

OUT1DIVRSEL2

OUT1DIVRSEL3

OUT1DIVRSEL4

OUT1DIVRSEL5

OUT1DIVRSEL6

Output Divider 1 ratio select

(seeTable 7)

Output 0 and 1

EEPROM

When set to 0, the divider is disabled

When set to 1, the divider is enabled

24

20

EN01DIV

Output 0 and 1

Output 1

EEPROM

25

26

27

28

29

21

22

23

24

25

PECL1HISWING

CMOSMODE1PX

CMOSMODE1PY

CMOSMODE1NX

CMOSMODE1NY

High Output Voltage Swing in LVPECL Mode if set to 1

LVCMOS mode select for OUTPUT 1 Positive Pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

Output 1

EEPROM

LVCMOS mode select for OUTPUT 1 Negative Pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

RAM BITS

OUTPUT TYPE

30

31

26

27

OUTBUFSEL1X

OUTBUFSEL1Y

Output 1

22

0

23

0

24

0

25

0

26

0

27

1

EEPROM

LVPECL

LVDS

0

1

0

1

LVCMOS

See Settings Above⁽¹⁾

0

All Outputs Disabled

0

1

0

1

0

(1) Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs.

22

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Register 2: SPI Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

0

1

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

0

1

0

2

3

4

0

1

DLYM0

Reference phase delay M bit0

Reference phase delay M bit1

Reference phase delay M bit2

Feedback phase delay N bit0

Feedback phase delay N bit1

Feedback phase delay N bit2

5

DLYM1

DELAY M

DELAY N

EEPROM

6

2

DLYM2

7

3

DLYN0

8

4

DLYN1

9

5

DLYN2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

6

PH2ADJC0

PH2ADJC1

PH2ADJC2

PH2ADJC3

PH2ADJC4

PH2ADJC5

PH2ADJC6

OUT2DIVRSEL0

OUT2DIVRSEL1

OUT2DIVRSEL2

OUT2DIVRSEL3

OUT2DIVRSEL4

OUT2DIVRSEL5

OUT2DIVRSEL6

7

8

9

Output 2

Coarse phase adjust select for output divider 2

EEPROM

10

11

12

13

14

15

16

17

18

19

Output Divider 2 ratio select

(seeTable 7)

Output 2

EEPROM

When set to 0, the divider is disabled

When set to 1, the divider is enabled

24

20

EN2DIV

Output 2

EEPROM

25

26

27

28

29

21

22

23

24

25

PECL2HISWING

CMOSMODE2PX

CMOSMODE2PY

CMOSMODE2NX

CMOSMODE2NY

High Output Voltage Swing in LVPECL Mode if set to 1

LVCMOS mode select for OUTPUT 2 Positive Pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

Output 2

EEPROM

LVCMOS mode select for OUTPUT 2 Negative Pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

RAM BITS

OUTPUT TYPE

30

31

26

27

OUTBUFSEL2X

OUTBUFSEL2Y

Output 2

22

0

23

0

24

0

25

0

26

0

27

1

EEPROM

LVPECL

LVDS

0

1

0

1

LVCMOS

See Settings Above⁽¹⁾

0

All Outputs Disabled

0

1

0

1

0

(1) Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs.

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Register 3: SPI Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

0

1

2

3

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

1

0

When set to 0, the REF-clock frequency detector is ON

When set to 1, it is switched OFF

4

0

DIS_FDET_REF

PLL Freq. Detect

Diagnostics

EEPROM

When set to 1, the feedback path frequency detector is switched OFF

(TI Test-GTME)

5

6

1

2

DIS_FDET_FB

BIAS_DIV01<0>

When BIAS_DIV01<1:0> =

Output Divider

0 and 1

00, No current reduction for all output-divider

01, Current reduction for all output-divider by about 20%

10, Current reduction for all output-divider by about 30%

EEPROM

7

8

9

3

4

5

BIAS_DIV01<1>

BIAS_DIV23<0>

BIAS_DIV23<1>

When BIAS_DIV23<1:0> =

Output Divider

2 and 3

00, No current reduction for all output-divider

01, Current reduction for all output-divider by about 20%

10, Current reduction for all output-divider by about 30%

10

11

12

13

14

15

16

17

18

19

20

21

22

23

6

PH3ADJC0

7

PH3ADJC1

8

PH3ADJC2

9

PH3ADJC3

Output 3

Coarse phase adjust select for Output Divider 3

EEPROM

10

11

12

13

14

15

16

17

18

19

PH3ADJC4

PH3ADJC5

PH3ADJC6

OUT3DIVRSEL0

OUT3DIVRSEL1

OUT3DIVRSEL2

OUT3DIVRSEL3

OUT3DIVRSEL4

OUT3DIVRSEL5

OUT3DIVRSEL6

Output Divider 3 ratio select

(seeTable 7)

Output 3

EEPROM

When set to 0, the divider is disabled

When set to 1, the divider is enabled

24

20

EN3DIV

Output 3

EEPROM

25

26

27

28

29

21

22

23

24

25

PECL3HISWING

CMOSMODE3PX

CMOSMODE3PY

CMOSMODE3NX

CMOSMODE3NY

High Output Voltage Swing in LVPECL Mode if set to 1

LVCMOS mode select for OUTPUT 3 Positive Pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

Output 3

EEPROM

LVCMOS mode select for OUTPUT 3 Negative Pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

RAM BITS

OUTPUT TYPE

30

31

26

27

OUTBUFSEL3X

OUTBUFSEL3Y

Output 3

22

0

23

0

24

0

25

0

26

0

27

1

EEPROM

LVPECL

LVDS

0

1

0

1

LVCMOS

See Settings Above⁽¹⁾

0

All Outputs Disabled

0

1

0

1

0

(1) Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs

24

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Register 4: SPI Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

0

1

2

3

4

5

6

7

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

0

1

0

1

2

3

RESERVED

EEPROM

If set to 1 it will 3-state the charge pump to act as a HOLD on Loss of

Reference Clocks ( Primary and Secondary)

8

4

HOLDONLOR

HOLD-Over

EEPROM

9

5

RESERVED

10

11

12

13

14

15

16

17

18

19

20

21

22

23

6

PH4ADJC0

7

PH4ADJC1

8

PH4ADJC2

9

PH4ADJC3

Output 4

Coarse phase adjust select for Output Divider 4

EEPROM

10

11

12

13

14

15

16

17

18

19

PH4ADJC4

PH4ADJC5

PH4ADJC6

OUT4DIVRSEL0

OUT4DIVRSEL1

OUT4DIVRSEL2

OUT4DIVRSEL3

OUT4DIVRSEL4

OUT4DIVRSEL5

OUT4DIVRSEL6

Output Divider 4 ratio select

(seeTable 7)

Output 4

EEPROM

When set to 0, the divider is disabled

When set to 1, the divider is enabled

24

20

EN4DIV

Output 4

EEPROM

25

26

27

28

29

21

22

23

24

25

PECL4HISWING

CMOSMODE4PX

CMOSMODE4PY

CMOSMODE4NX

CMOSMODE4NY

High Output Voltage Swing in LVPECL Mode if set to 1

LVCMOS mode select for OUTPUT 4 Positive Pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

Output 4

EEPROM

LVCMOS mode select for OUTPUT 4 Negative Pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

RAM BITS

OUTPUT TYPE

30

31

26

27

OUTBUFSEL4X

OUTBUFSEL4Y

Output 4

22

0

23

0

24

0

25

0

26

0

27

1

EEPROM

LVPECL

LVDS

0

1

0

1

LVCMOS

See Settings Above⁽¹⁾

0

All Outputs Disabled

0

1

0

1

0

(1) Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs

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Register 5: SPI Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

0

1

2

3

4

A0

A1

A2

A3

Address 0

1

0

1

0

Address 1

Address 2

Address 3

0

1

2

3

BIAS_DIV45<0>

BIAS_DIV45<1>

BIAS_DIV67<0>

BIAS_DIV67<1>

When BIAS_DIV45<1:0> =

00, No current reduction for all output-divider

01, Current reduction for all output-divider by about 20%

10, Current reduction for all output-divider by about 30%

Output Divider

4 and 5

EEPROM

5

6

7

When BIAS_DIV67<1:0> =

Output Divider

6 and 7

00, No current reduction for all output-divider

01, Current reduction for all output-divider by about 20%

10, Current reduction for all output-divider by about 30%

8

4

5

RESERVED

EEPROM

9

RESERVED

10

11

12

13

14

15

16

17

18

19

20

21

22

23

6

PH5ADJC0

7

PH5ADJC1

8

PH5ADJC2

9

PH5ADJC3

Output 5

Coarse phase adjust select for Output Divider 5

EEPROM

10

11

12

13

14

15

16

17

18

19

PH5ADJC4

PH5ADJC5

PH5ADJC6

OUT5DIVRSEL0

OUT5DIVRSEL1

OUT5DIVRSEL2

OUT5DIVRSEL3

OUT5DIVRSEL4

OUT5DIVRSEL5

OUT5DIVRSEL6

Output Divider 5 ratio select

(seeTable 7)

Output 5

EEPROM

When set to 0, the divider is disabled

When set to 1, the divider is enabled

24

20

EN5DIV

Output 5

EEPROM

25

26

27

28

29

21

22

23

24

25

PECL5HISWING

CMOSMODE5PX

CMOSMODE5PY

CMOSMODE5NX

CMOSMODE5NY

High Output Voltage Swing in LVPECL Mode if set to 1

LVCMOS mode select for OUTPUT 5 Positive Pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

Output 5

EEPROM

LVCMOS mode select for OUTPUT 5 Negative Pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

RAM BITS

OUTPUT TYPE

30

31

26

27

OUTBUFSEL5X

OUTBUFSEL5Y

Output 5

22 23

24

0

25

26

0

27

1

EEPROM

LVPECL

LVDS

0

1

0

1

LVCMOS

See Settings Above⁽¹⁾

0

All Outputs Disabled

0

1

0

1

0

(1) Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs

26

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Register 6: SPI Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

0

1

2

3

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

0

1

0

0 Feedback Frequency Detector is connected to the Lock Detector

1 Feedback Frequency Detector is disconnected from the Lock Detector

4

5

6

0

1

2

FB_FD_DESEL

RESERVED

LOCK-DET

FB-

EEPROM

Set to 0

0 FB-Deterministic Clock divided by 1

1 FB- Deterministic Clock divided by 2

FBDETERM_DIV_SEL

0 FB-Deterministic-DIV2-Block in normal operation

1 FB-Deterministic-DIV2 reset (here REG6_RB<2> == 0)

7

8

9

3

4

5

FBDETERM_DIV2_DIS Divider/Deterministi

c Blocks

EEPROM

0 FB-Divider started with delay block (RC), normal operation

1 FB-Divider can be started with external REF_SEL-signal (pin)

FB_START_BYPASS

All Output Dividers 0 Output-Dividers started with delay block (RC), normal operation

1 Output-Dividers can be started with external NRESET-signal (pin)

DET_START_BYPASS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

6

PH6ADJC0

Output 6

7

PH6ADJC1

8

PH6ADJC2

9

PH6ADJC3

Coarse phase adjust select for Output Divider 6

EEPROM

10

11

12

13

14

15

16

17

18

19

PH6ADJC4

PH6ADJC5

PH6ADJC6

OUT6DIVRSEL0

OUT6DIVRSEL1

OUT6DIVRSEL2

OUT6DIVRSEL3

OUT6DIVRSEL4

OUT6DIVRSEL5

OUT6DIVRSEL6

Output Divider 6 ratio select

(seeTable 7)

Output 6

EEPROM

When set to 0, the divider is disabled

Output 6

24

20

EN6DIV

EEPROM

When set to 1, the divider is enabled

25

26

27

28

29

21

22

23

24

25

PECL6HISWING

CMOSMODE6PX

CMOSMODE6PY

CMOSMODE6NX

CMOSMODE6NY

Output 6

High Output Voltage Swing in LVPECL Mode if set to 1

LVCMOS mode select for OUTPUT 6 Positive Pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

EEPROM

LVCMOS mode select for OUTPUT 6 Negative Pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

Output 6

RAM BITS

OUTPUT TYPE

30

31

26

27

OUTBUFSEL6X

OUTBUFSEL6Y

22

0

23

0

24

0

25

0

26

0

27

1

EEPROM

LVPECL

LVDS

0

1

0

1

Output 6

LVCMOS

See Settings Above⁽¹⁾

0

All Outputs Disabled

0

1

0

1

0

(1) Use description for bits 22,23,24, and 25 for setting the LVCMOS outputs

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Register 7: SPI Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

0

1

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

1

2

1

0

3

4

0

1

LOCKW 0

Lock-detect window Bit 0 (Refer to Reg 9 RAM Bits 6 and 7)

Lock-detect window Bit 1 (Refer to Reg 9 RAM Bits 6 and 7)

Set to 0

EEPROM

5

LOCKW 1

6

2

RESERVED

LOCKC0

LOCK-DET

7

3

Number of coherent lock events Bit 0

EEPROM

8

4

LOCKC1

Number of coherent lock events Bit 1

9

5

ADLOCK

Selects Digital PLL_LOCK 0, Selects Analog PLL_LOCK 1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

6

PH7ADJC0

7

PH7ADJC1

8

PH7ADJC2

9

PH7ADJC3

Output 7

Coarse phase adjust select for Output Divider 7

EEPROM

10

11

12

13

14

15

16

17

18

19

PH7ADJC4

PH7ADJC5

PH7ADJC6

OUT7DIVRSEL0

OUT7DIVRSEL1

OUT7DIVRSEL2

OUT7DIVRSEL3

OUT7DIVRSEL4

OUT7DIVRSEL5

OUT7DIVRSEL6

Output Divider 7 ratio select

(seeTable 7)

Output 7

EEPROM

When set to 0, the divider is disabled

When set to 1, the divider is enabled

24

20

EN7DIV

Output 7

EEPROM

25

26

27

28

29

21

22

23

24

25

PECL7HISWING

CMOSMODE7PX

CMOSMODE7PY

CMOSMODE7NX

CMOSMODE7NY

High Output Voltage Swing in LVPECL Mode if set to 1

LVCMOS mode select for OUTPUT 7 Positive Pin

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

Output 7

EEPROM

LVCMOS mode select for OUTPUT 7 Negative Pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

RAM BITS

OUTPUT TYPE

30

31

26

27

OUTBUFSEL7X

OUTBUFSEL7Y

Output 7

22

0

23

0

24

0

25

26

0

27

1

EEPROM

LVPECL

LVDS

0

1

0

1

LVCMOS

See Settings Above⁽¹⁾

0

All Outputs Disabled

0

1

0

1

0

(1) Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs

28

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Register 8: SPI Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

0

1

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

0

1

2

3

4

0

1

VCXOBUFSELX

VCXOBUFSELY

VCXOACDCSEL

VCXOHYSTEN

VCXOTERMSEL

VCXOINVBB

VCXO and AUX Input Buffer Type Select (LVPECL,LVDS or LVCMOS)

XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin

5

VCXO and AUX

Input Buffers

6

2

If Set to 0 AC Termination, If set to 1 DC Termination

If Set to 1 Input Buffers Hysteresis enabled

EEPROM

7

3

8

4

If Set to 0 Input Buffer Internal Termination enabled

9

5

VCXO Input Buffer If Set to 1 It Biases VCXO Input negative pin with internal VCXOVBB Voltage

10

11

12

13

14

15

16

17

18

19

20

21

22

23

6

PH8ADJC0

7

PH8ADJC1

8

PH8ADJC2

9

PH8ADJC3

Output 8 and 9

Coarse phase adjust select for Output Divider 8

EEPROM

10

11

12

13

14

15

16

17

18

19

PH8ADJC4

PH8ADJC5

PH8ADJC6

OUT8DIVRSEL0

OUT8DIVRSEL1

OUT8DIVRSEL2

OUT8DIVRSEL3

OUT8DIVRSEL4

OUT8DIVRSEL5

OUT8DIVRSEL6

Output Divider 8 ratio select

(seeTable 7)

Output 8 and 9

EEPROM

When set to 0, the divider is disabled

When set to 1, the divider is enabled

24

20

EN89DIV

Output 8 and 9

Output 8

EEPROM

25

26

27

28

29

21

22

23

24

25

PECL8HISWING

CMOSMODE8PX

CMOSMODE8PY

CMOSMODE8NX

CMOSMODE8NY

High Output Voltage Swing in LVPECL Mode if set to 1

LVCMOS mode select for OUTPUT 8 Positive Pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

Output 8

EEPROM

LVCMOS mode select for OUTPUT 8 Negative Pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

RAM BITS

OUTPUT TYPE

30

31

26

27

OUTBUFSEL8X

OUTBUFSEL8Y

Output 8

22

0

23

0

24

0

25

0

26

0

27

1

EEPROM

LVPECL

LVDS

0

1

0

1

LVCMOS

See Settings Above⁽¹⁾

0

All Outputs Disabled

0

1

0

1

0

(1) Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs

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Register 9: SPI Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

DESCRIPTION/FUNCTION

0

1

2

3

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

1

0

1

Enables the Frequency Hold-Over (External Hold Over Function based on the

external circuitry) on 1, off 0

4

0

HOLDF

5

6

1

2

RESERVED

HOLD

3-State Charge Pump 0 - (equal to HOLD pin function)

HOLD function always activated 1 (recommended for test purposes, only)

Triggered by analog PLL Lock detect outputs

If analog PLL Lock Signal is [1] (PLL locked), HOLD is activated

If analog PLL Lock Signal is [0] (PLL not lock), HOLD is deactivated

HOLD-Over

EEPROM

7

3

HOLDTR

8

9

4

5

HOLD_CNT0

HOLD_CNT1

HOLD1 Function is reactivated after X Ref Clock Cycles. Defined by

(HOLD_CNT0,HOLD_CNT1) : X = Number of Clock Cycles.

For (00) : X = 64, (01) : X = 128, (10) : X = 256, (11) : X = 512 Clock Cycles

10

11

6

7

LOCKW 2

LOCKW 3

Extended Lock-detect window Bit 2 (also refer to Reg 7 RAM Bits 0 and 1)

Extended Lock-detect window Bit 3 (also refer to Reg 7 RAM Bits 0 and 1)

LOCK-DET

Chip CORE

EEPROM

When set to 0, SPI/HOLD_INT and SPI/RESET_INT inverted (default)

When set to 1, SPI/HOLD_INT and SPI/RESET_INT not inverted

12

13

8

9

NOINV_RESHOL_INT

DIVSYNC_DIS

When GTME = 0, this Bit has no functionality, But when GTME = 1, then:

When set to 0, START-Signal is synchronized to N/M Divider Input Clocks

When set to 1, START-Sync N/M Divider in PLL are bypassed

Diagnostic: PLL

N/M Divider

EEPROM

Divider START When set to 0, START-Signal is synchronized to VCXO-Clock

DETERM-Block When set to 1, START-Sync Block is bypassed

14

15

16

10

11

12

START_BYPASS

INDET_BP

EEPROM

Divider START When set to 0, Sync Logic active when VCXO/AUX-Clocks are available

DETERM-Block When set to 1, Sync Logic is independent from VCXO- and/or AUX-Clocks

Divider START When set to 0, Sync Logic waits for 1st PLL_LOCK state

DETERM-Block When set to 1, Sync Logic independent from 1st PLL_LOCK

PLL_LOCK_BP

When set to 0, Sync Logic is independent from VCXO/DIV_FB freq. (PLL-FD)

When set to 1, Sync Logic is started for VCXO/DIV_FB > ~600KHz, stopped for

VCXO/DIV_FB < ~600KHz

Divider START

DETERM-Block

17

13

LOW_FD_FB_EN

EEPROM

PLL

M/FB-Divider

When set to 0, M-Divider uses NHOLD as NPRESET

When set to 1, M-Divider NOT preseted by NHOLD

18

19

14

15

NPRESET_MDIV

BIAS_DIV_FB<0>

When BIAS_DIV_FB<1:0> =

Feedback

Divider

00, No current reduction for FB-Divider

01, Current reduction for FB-Divider by about 20%

10, Current reduction for FB-Divider by about 30%

EEPROM

20

21

22

16

17

18

BIAS_DIV_FB<1>

BIAS_DIV89<0>

BIAS_DIV89<1>

When BIAS_DIV89<1:0> =

Output Divider 00, No current reduction for all output-rivider

EEPROM

8 and 9

01, Current reduction for all output-divider by about 20%

10, Current reduction for all output-divider by about 30%

23

24

19

20

AUXINVBB

If set to 1 it biases AUX Input Negative pin with internal VCXOVBB voltage.

AUX Input

Buffer

If set to 1 AUX in Input Mode Buffer Is disabled. If set to 0 it follows the behavior of

FB_MUX_SEL and OUT_MUX_SEL bits settings.

DIS_AUX_Y9

25

26

27

28

29

21

22

23

24

25

PECL9HISWING

CMOSMODE9PX

CMOSMODE9PY

CMOSMODE9NX

CMOSMODE9NY

Output 9

High output voltage swing in LVPECL Mode if set to 1

EEPROM

LVCMOS mode select for OUTPUT 9 Positive pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

LVCMOS mode select for OUTPUT 9 Negative pin.

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

Output 9

EEPROM

RAM BITS

OUTPUT TYPE

30

31

26

27

OUTBUFSEL9X

OUTBUFSEL9Y

22

0

23

0

24

0

25

0

26

0

27

1

LVPECL

LVDS

0

1

0

1

Output 9

LVCMOS

See Settings Above⁽¹⁾

0

EEPROM

All Outputs Disabled

0

1

0

1

0

(1) Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs

30

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Register 10: SPI Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

DESCRIPTION/FUNCTION

0

A0

Address 0

0

1

0

1

A1

Address 1

2

A2

Address 2

3

A3

Address 3

4

0

1

M0

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

M13

N0

Reference Divider M Bit 0

Reference Divider M Bit 1

Reference Divider M Bit 2

Reference Divider M Bit 3

Reference Divider M Bit 4

Reference Divider M Bit 5

Reference Divider M Bit 6

Reference Divider M Bit 7

Reference Divider M Bit 8

Reference Divider M Bit 9

Reference Divider M Bit 10

Reference Divider M Bit 11

Reference Divider M Bit 12

Reference Divider M Bit 13

VCXO Divider N Bit 0

VCXO Divider N Bit 1

VCXO Divider N Bit 2

VCXO Divider N Bit 3

VCXO Divider N Bit 4

VCXO Divider N Bit 5

VCXO Divider N Bit 6

VCXO Divider N Bit 7

VCXO Divider N Bit 8

VCXO Divider N Bit 9

VCXO Divider N Bit 10

VCXO Divider N Bit 11

VCXO Divider N Bit 12

VCXO Divider N Bit 13

5

6

2

7

3

8

4

9

5

Reference

(PRI/SEC) Divider

M

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

6

EEPROM

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

N1

N2

N3

N4

N5

N6

VCXO/AUX/SEC

Divider N

EEPROM

N7

N8

N9

N10

N11

N12

N13

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Register 11: SPI Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

DESCRIPTION/FUNCTION

0

1

2

3

4

5

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

1

0

1

0

1

PRI_DIV2

SEC_DIV2

Input Buffers

If set to 1 enables Primary Reference Divide by 2

If set to 1 enables Secondary Reference Divide by 2

EEPROM

FB Path Integer

Counter 32

When set to 0, FB divider is active

When set to 1, FB divider is disabled

When set to 0, FB clock is CMOS type⁽¹⁾

6

7

2

3

FB_DIS

EEPROM

FB Path Integer

Counter 32

FB_CML_SEL

When set to 1, FB clock is CML type and uses CML2CMOS converter in PLL

FB-Divider/

Deterministic

Blocks

When set to 0, Input clock for FB not inverted (normal mode, low speed)

When set to 1, Input clock for FB inverted (higher speed mode)

8

4

FB_INCLK_INV

EEPROM

9

5

FB_COUNT32_0

FB_COUNT32_1

FB_COUNT32_2

FB_COUNT32_3

FB_COUNT32_4

FB_COUNT32_5

FB_COUNT32_6

FB_PHASE0

Feedback Counter Bit0

10

11

12

13

14

15

16

17

18

19

20

21

22

6

Feedback Counter Bit1

7

Feedback Counter Bit2

FB Path Integer

Counter 32

8

Feedback Counter Bit3

EEPROM

9

Feedback Counter Bit4

10

11

12

13

14

15

16

17

18

Feedback Counter Bit5

Feedback Counter Bit6

Feedback Phase Adjust Bit0

Feedback Phase Adjust Bit1

Feedback Phase Adjust Bit2

Feedback Phase Adjust Bit3

Feedback Phase Adjust Bit4

Feedback Phase Adjust Bit5

Feedback Phase Adjust Bit6

FB_PHASE1

FB_PHASE2

FB Path Integer

Counter 32

FB_PHASE3

EEPROM

FB_PHASE4

FB_PHASE5

FB_PHASE6

If set to 0, PLL is in normal mode

If set to 1, PLL is powered down

23

24

25

19

20

21

PD_PLL

PLL

EEPROM

When set to 0, the VCXO Clock is selected for the Clock Tree and FB-Div and

Det

When set to 1, the AUX Clock is selected for the Clock Tree and FB-Div and

Det

Clock Tree and

Deterministic

Block

FB_MUX_SEL

See Table 6

OUT_MUX_SEL

See Table 6

Clock Tree

If Set to 0 it selects the VCXO Clock and if Set to 1 it selects the AUX Clock

Feed Back Path Selects FB/VCXO-Path when set to 0 (TI Test-GTME)

The Secondary Reference clock input is selected when set to 1 (TI Test-GTME)

26

27

28

29

30

31

22

23

24

25

26

27

FB_SEL

Diagnostics

EEPROM

NRESHAPE1

SEL_DEL1

RESET_HOLD

EPLOCK

Reshapes the Reference Clock Signal 0, Disable Reshape 1

Reference

Selection Control

If set to 0 it enables short delay for fast operation

If Set to 1 Long Delay recommended for Input References below 150Mhz

Reset Circuitry

Status

If set to 1 the RESET or HOLD pin acts as HOLD, set to 0 it acts as RESET

Read only. If EPLOCK reads a 0, the EEPROM is unlocked. If EPLOCK reads a

1, then the EEPROM is locked.

EPSTATUS

Status

EEPROM Status

(1) When Feedback Divider clock is set to CMOS type, only feedback divider values greater than 5 are available.

Table 6. Output Buffers Source Feed, PLL Source Feed, and AUX IN/OUTPUT 9 Selection

FB_MUX_SEL

OUT_MUX_SEL

PLL FEED AND OUTPUTS FEED

AUX INPUT OR OUTPUT 9

0

1

0

1

0

1

VCXO::PLL, VCXO::Y0…Y9 and Deterministic Block

AUXIN::PLL, VCXO::Y0…Y8 and Deterministic Block

VCXO::PLL, AUXIN::Y0…Y8 and Deterministic Block

AUXIN::PLL, AUXIN::Y0…Y8 and Deterministic Block

OUTPUT 9 is enabled

AUX IN is enabled

32

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Register 12: SPI Mode (RAM only Register)

SPI

BIT

RAM

BIT

POR

DEFAULT

BIT NAME

A0

DESCRIPTION/FUNCTION

0

1

2

3

4

5

6

7

Address 0

Address 1

Address 2

Address 3

0

A1

A2

1

A3

1

0

1

2

3

RESERVED

RAM

Status

(Read Only)

8

9

4

5

INDET_AUX

It indicates that a clock is present at AUX-input (Y9) , when set to 1

It indicates that a clock is present at VCXO-input , when set to 1

RAM

Status

(Read Only)

INDET_VCXO

Status

(Read Only)

10

11

6

7

PLL_LOCK

PD

It indicates that the PLL is locked when set to 1

RAM

Power Down

Power-down mode on when set to 0, Off when set to 1

1

If set to 0 this bit forces “RESET or HOLD” depending on the setting of

RESET_HOLD bit in Register 11. If set to 0 RESET or HOLD are asserted.

Set for 1 for normal operation.

RESET or

HOLD

12

13

8

9

Reset

RAM

General Test Mode Enable, Test Mode is only enabled, if this bit is set to 1

This bit controls many test modes on the device.

GTME

Diagnostics

0

14

15

16

10

11

12

REVISION0

REVISION1

REVISION2

Status

Read only: Revision Control Bit 0

Read only: Revision Control Bit 1

Read only: Revision Control Bit 2

RAM

When set to 0, all blocks are on. (TI Test-GTME)

When set to 1, the VCXO Input, AUX Input and all output buffers and divider

blocks are disabled. This test is done to measure the effect of the I/O circuitry

on the Charge Pump. (TI Test-GTME)

17

18

13

14

PD_IO

Diagnostics

0

RAM

If set to 0 that Status pin is used as CMOS output to enable TI test modes.

Set to 1 when IREFRES is set to 1 and 12-KΩ resistor is connected. (TI

Test-GTME)

SXOIREF

Diagnostics

19

20

21

22

23

24

25

26

27

28

29

30

31

15

16

17

18

19

20

21

22

23

24

25

26

27

SHOLD

Routes the HOLD signal to the PLL_LOCK pin when set to 1 (TI Test-GTME)

0

RAM

RESERVED

STATUS0

TI test registers. For TI use only

Route internal signals to external STATUS pin.

STATUS3, STATUS2, STATUS1, STATUS0 (S3, S2, S1, S0) will select that

internal status signal that will be routed to the external STATUS pin.

STATUS1

Diagnostics

1

RAM

STATUS2

STATUS3

TITSTCFG0

TITSTCFG1

TITSTCFG2

TITSTCFG3

PRIACTIVITY

SECACTIVITY

RESERVED

Diagnostics

Status

TI test registers. For TI use only

0

RAM

TI test registers. For TI use only

It indicates activity on the Primary when set to - (read only bit)

It indicates activity on the Secondary when set to - (read only bit)

Status

NOTE:

If TI test bits (Register 12< RAM bits 17,18,19, 20> are set to 1000, Reference Select

from the Smart Mux will show on the STATUS pin ( High = Primary REF is selected

and Low = Secondary REF is selected).

When TI test bits are set to 0000 the Reference Clock Frequency Detector shows up

on the STATUS pin. In this mode the STATUS pin goes high if a clock is detected and

low if a clock is not detected. In this configuration Register 3 Bit 0 should be set to 0.

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OUTPUT DIVIDERS SETTINGS

The CDCE72010 has a complex multi stage output divider. The table below describes the setting of Bits 13:19 of

Register 1 to 8 and the setting for the feedback divider bits 5:11 of register 11. The table below describes divider

settings and the phase relation of the outputs with respect to divide by one clock. To calculate the phase relation

between 2 different dividers see Output Divider and Phase Adjust Section in this document.

Table 7. Output Dividers and Feedback Divide Settings and Phase Output

FOR REGISTER 1 TO 8 RAM BITS {19[BIT6] TO

DIVIDE BY

TOTAL

13[BIT0]}

PHASE LAG FROM DIVIDE BY 1

FOR REGISTER 11 RAM BITS {11[BIT6] TO 5[BIT0]}

[Bit 6] [Bit 5] [Bit 4] [Bit 3] [Bit 2] [Bit 1] [Bit 0]

Cycle

0

Degree

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

0.5

0

180

3

0

4

0.5

0

180

5

0

4'

14.5

21

5220

7560

10260

12600

5940

8640

11700

14400

6660

9720

13140

16200

7380

10800

14580

18000

8100

11880

16020

19800

8820

12960

17460

21600

9540

14040

18900

23400

10260

15120

20340

25200

6

8

28.5

35

10

8'

16.5

24

12

16

20

12'

18

24

30

16'

24'

32

40

20'

30'

40'

50

24'

36

48

60

28

42

56

70

32'

48'

64

80

32.5

40

18.5

27

36.5

45

20.5

30

40.5

50

22.5

33

44.5

55

24.5

36

48.5

60

26.5

39

52.5

65

28.5

42

56.5

70

34

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CONFIGURATION DEFAULT MODE

The CDCE72010 has two modes of operation, SPI Interface and Configuration Default Mode. The Configuration

Default mode is selected when MODE_SELECT Pin is driven low and it is used where SPI interface is not

available. In the CD Mode configuration, the SPI interface Pins become static control pins CD1, CD2, CD3 and

AUX_SEL as shown in the Pin description. The CD Mode signals are sampled only at power up or after Power

Down are asserted.

In CD Mode BYPASS, CD1 and CD2 are used to switch between EEPROM saved configurations. -CD1 allows

swapping Divider and Phase Adjust value between output couples.

•

CD2 allows changing the output type for each output.

AUX_SEL Controls the Output Mux between VCXO and AUX Input.

CD3 must be grounded in CD Mode.

Without any interface a single device with a single program can have multiple configurations that can be

implemented on more than one socket.

RAM Resistors

PLL_LOCK

REF_SEL

PLL_LOCK

REF_SEL

POWER DOWN

RESET or HOLD

MODE_SEL

POWER DOWN

RESET or HOLD

MODE_SEL

Interface

& Control

Interface

& Control

AUX_SEL

EEPROM

SPI_MISO

SPI_LE (CD1)

SPI_CLK (CD2)

SPI_MOSI (CD3)

CD1

CD2

CD3

Figure 13. Writing to EEPROM via SPI Bus in

Manufacutring,

Figure 14. Using CD1, CD2 to Control What is Copied

From EEPROM Into RAM Registers at Power Up

3rd Party Vendor or at TI Test

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Register 0: CD Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

DESCRIPTION/FUNCTION

0

1

2

3

4

5

6

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

0

1

2

INBUFSELX

INBUFSELY

PRISEL

Reference Input

Buffers

Primary and Secondary Buffer Type Select (LVPECL,LVDS or LVCMOS)

XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin

EEPROM

When REFSELCNTRL is set to 1 the following settings apply:

If RAM Bit (2,3): 00 – no Input Buffer is selected/active

If RAM Bit (2,3): 10 – PRI_BUF is selected, SEC_BUF is powered down

If RAM Bit (2,3): 01 – SEC_BUF is selected, PRI_BUF is powered down⁽¹⁾

If RAM Bit (2,3): 11 – Auto Select (PRI then SEC).

Reference Input

Buffer

EEPROM

7

8

3

4

SECSEL

When set to 0, PRI- or SEC-Clocks are selected, depending on Bits 2 and 3

(default)

When set to 1, VCXO/AUX-clock selected, overwrites Bits 2 and 3

Divider START

DETERM-Block

VCXOSEL

EEPROM

Reference Select Control to select if the control of the reference is from the

internal bit in Register 0 RAM bits 2 and 3 or from the external select pin.

- When set to 0: The external pin REF_SEL takes over the selection between

PRI and SEC. Autoselect is not available.

- When set to 1: The external pin REF_SEL is ignored. The Table in (Register 0

<2 and 3> ) describes, which reference input clock is selected and available at

(none, PRI, SEC or Autoselect). In autoselect mode, refer to the timing diagram

Reference

Selection Control

9

5

REFSELCNTRL

10

11

12

6

7

8

DELAY_PFD0

DELAY_PFD1

CP_MODE

PFD

PFD Pulse Width PFD Bit 0

EEPROM

PFD Pulse Width PFD Bit 1

Selects 3V option [0] or 5V option [1]

Charge Pump

Determines in which direction CP current will regulate (Reference Clock leads to

Feedback Clock; Positive CP output current [0]; Negative CP output current [1]

13

14

9

CP_DIR

EEPROM

Switches the current source in the Charge Pump on when set to 1 (TI

Test-GTME)

10

CP_SRC

Diagnostics

15

16

17

18

19

20

21

22

23

11

12

13

14

15

16

17

18

19

CP_SNK

CP_OPA

CP_PRE

ICP0

Switches the current sink in the Charge Pump on when set to 1 (TI Test-GTME)

Switches the Charge Pump op-amp off when set to 1 (TI Test-GTME)

Preset Charge Pump output voltage to V_{CC_CP}/2, on [1], off [0]

CP Current Setting Bit 0

EEPROM

ICP1

Charge Pump

CP Current Setting Bit 1

ICP2

CP Current Setting Bit 2

ICP3

CP Current Setting Bit 3

RESERVED

Enables the 12k pull-down resistor at I_REF_CP Pin when set to 1 (TI

Test-GTME)

24

20

IREFRES

Diagnostics

EEPROM

25

26

27

28

29

30

31

21

22

23

24

25

26

27

PECL0HISWING

RESERVED

Output 0

High output voltage swing in LVPECL Mode if set to 1

EEPROM

RESERVED

OUTBUF0CD2LX

OUTBUF0CD2LY

OUTBUF0CD2HX

OUTBUF0CD2HY

Output Buffer 0 Signaling Selection when CD2 In low

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

CD2 Low

CD2 High

EEPROM

Output Buffer 0 Signaling Selection when CD2 in high

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: output disable

(1) This setting is only avaiable if the Register 11 Bit 2 is set to 0 (Feedback Divider clock is set to CMOS type).

36

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Register 1: CD Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

DESCRIPTION/FUNCTION

0

1

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

1

0

2

0

3

0

4

0

1

ACDCSEL

Input Buffers

If Set to 0 AC Termination, If set to 1 DC termination

If Set to 1 Input Buffers Hysteresis enabled

EEPROM

5

HYSTEN

6

2

TERMSEL

If Set to 0 Input Buffer Internal Termination enabled

7

3

PRIINVBB

If Set to 1 Primary Input Negative Pin biased with internal VBB voltage.

If Set to 1 Secondary Input Negative Pin biased with internal VBB voltage

If Set to 1 Fail Safe is enabled for all input buffers.

8

4

SECINVBB

9

5

FAILSAFE

10

11

12

13

14

15

16

17

18

19

20

21

22

23

6

PH1ADJC0

7

PH1ADJC1

8

PH1ADJC2

9

PH1ADJC3

Output 0 and 1

Coarse phase adjust select for output divider 1

EEPROM

10

11

12

13

14

15

16

17

18

19

PH1ADJC4

PH1ADJC5

PH1ADJC6

OUT1DIVRSEL0

OUT1DIVRSEL1

OUT1DIVRSEL2

OUT1DIVRSEL3

OUT1DIVRSEL4

OUT1DIVRSEL5

OUT1DIVRSEL6

OUTPUT DIVIDER 1 Ratio Select

(See Table 7)

Output 0 and 1

EEPROM

When set to 0, the divider is disabled

When set to 1, the divider is enabled

24

25

20

21

EN01DIV

Output 0 and 1

Output 1

EEPROM

PECL1HISWING

High output voltage swing in LVPECL Mode if set to 1

CD1 PIN is high and DIVPHA1CD1H is set to low

Loads Output Divider 1 and Phase Adjust 1 into OUTPUT 1

CD1 PIN is high and DIVPHA1CD1H is set to high

Loads Output Divider 2 and Phase Adjust 2 into OUTPUT 1

26

27

22

23

DIVPHA1CD1H

DIVPHA1CD1L

CD1 High

CD1 Low

EEPROM

CD1 PIN is low and DIVPHA1CD1L is set to low

Loads Output Divider 1 and Phase Adjust 1 into OUTPUT 1

CD1 PIN is low and DIVPHA1CD1L is set to high

EEPROM

Loads Output Divider 2 and Phase Adjust 2 into OUTPUT 1

28

29

30

31

24

25

26

27

OUTBUF1CD2LX

OUTBUF1CD2LY

OUTBUF1CD2HX

OUTBUF1CD2HY

Output Buffer 1 Signaling Selection when CD2 in low

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

CD2 Low

CD2 High

Output Buffer 1 Signaling Selection when CD2 in high

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

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Register 2: CD Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

DESCRIPTION/FUNCTION

0

1

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

0

1

0

2

3

4

0

1

DLYM0

Reference Phase Delay M Bit0

Reference Phase Delay M Bit1

Reference Phase Delay M Bit2

Feedback Phase Delay N Bit0

Feedback Phase Delay N Bit1

Feedback Phase Delay N Bit2

5

DLYM1

DELAY M

DELAY N

EEPROM

6

2

DLYM2

7

3

DLYN0

8

4

DLYN1

9

5

DLYN2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

6

PH2ADJC0

PH2ADJC1

PH2ADJC2

PH2ADJC3

PH2ADJC4

PH2ADJC5

PH2ADJC6

OUT2DIVRSEL0

OUT2DIVRSEL1

OUT2DIVRSEL2

OUT2DIVRSEL3

OUT2DIVRSEL4

OUT2DIVRSEL5

OUT2DIVRSEL6

7

8

9

Output 2

Coarse phase adjust select for output divider 2

EEPROM

10

11

12

13

14

15

16

17

18

19

OUTPUT DIVIDER 2 Ratio Select

(See Table 7)

Output 2

EEPROM

When set to 0, the divider is disabled

When set to 1, the divider is enabled

24

25

20

21

EN2DIV

Output 2

EEPROM

PECL2HISWING

High output voltage swing in LVPECL Mode if set to 1

CD1 PIN is high and DIVPHA2CD1H is set to low

Loads Output Divider 2 and Phase Adjust 2 into OUTPUT 2

CD1 PIN is high and DIVPHA2CD1H is set to high

Loads Output Divider 1 and Phase Adjust 1 into OUTPUT 2

26

27

22

23

DIVPHA2CD1H

DIVPHA2CD1L

CD1 High

CD1 Low

EEPROM

CD1 PIN is low and DIVPHA2CD1L is set to low

Loads Output Divider 2 and Phase Adjust 2 into OUTPUT 2

CD1 PIN is low and DIVPHA2CD1L is set to high

Loads Output Divider 1 and Phase Adjust 1 into OUTPUT 2

28

29

30

31

24

25

26

27

OUTBUF2CD2LX

OUTBUF2CD2LY

OUTBUF2CD2HX

OUTBUF2CD2HY

Output Buffer 2 Signaling Selection when CD2 in low

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

CD2 Low

CD2 High

EEPROM

Output Buffer 2 Signaling Selection when CD2 in high

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

38

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Register 3: CD Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

DESCRIPTION/FUNCTION

0

1

2

3

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

1

0

When set to 0, the REF-clock frequency detector is ON

When set to 1, it is switched OFF

4

0

DIS_FDET_REF

PLL Freq. Detect

EEPROM

When set to 1, the feedback path frequency detector is switched OFF

(TI Test-GTME)

5

6

1

2

DIS_FDET_FB

Diagnostics

EEPROM

BIAS_DIV01<0>

When BIAS_DIV01<1:0> =

Output Divider

0 and 1

00, No current reduction for all output-divider

01, Current reduction for all output-divider by about 20%

10, Current reduction for all output-divider by about 30%

7

8

9

3

4

5

BIAS_DIV01<1>

BIAS_DIV23<0>

BIAS_DIV23<1>

EEPROM

When BIAS_DIV23<1:0> =

Output Divider

2 and 3

00, No current reduction for all output-divider

01, Current reduction for all output-divider by about 20%

10, Current reduction for all output-divider by about 30%

10

11

12

13

14

15

16

17

18

19

20

21

22

23

6

PH3ADJC0

7

PH3ADJC1

8

PH3ADJC2

9

PH3ADJC3

Output 3

Coarse phase adjust select for output divider 3

EEPROM

10

11

12

13

14

15

16

17

18

19

PH3ADJC4

PH3ADJC5

PH3ADJC6

OUT3DIVRSEL0

OUT3DIVRSEL1

OUT3DIVRSEL2

OUT3DIVRSEL3

OUT3DIVRSEL4

OUT3DIVRSEL5

OUT3DIVRSEL6

OUTPUT DIVIDER 3 Ratio Select

(See Table 7)

Output 3

EEPROM

When set to 0, the divider is disabled

When set to 1, the divider is enabled

24

25

20

21

EN3DIV

Output 3

EEPROM

PECL3HISWING

High Output Voltage Swing in LVPECL Mode if set to 1

CD1 PIN is high and DIVPHA3CD1H is set to low

Loads Output Divider 3 and Phase Adjust 3 into OUTPUT 3

CD1 PIN is high and DIVPHA3CD1H is set to high

Loads Output Divider 4 and Phase Adjust 4 into OUTPUT 3

26

27

22

23

DIVPHA3CD1H

DIVPHA3CD1L

CD1 High

CD1 Low

EEPROM

CD1 PIN is Low and DIVPHA3CD1L is set to low

Loads Output Divider 3 and Phase Adjust 3 into OUTPUT 3

CD1 PIN is Low and DIVPHA3CD1L is set to high

Loads Output Divider 4 and Phase Adjust 4 into OUTPUT 3

28

29

30

31

24

25

26

27

OUTBUF3CD2LX

OUTBUF3CD2LY

OUTBUF3CD2HX

OUTBUF3CD2HY

Output Buffer 3 Signaling Selection when CD2 in low

(X,Y) = 01:LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

CD2 Low

CD2 High

EEPROM

Output Buffer 3 Signaling Selection when CD2 in high

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

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Register 4: CD Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

DESCRIPTION/FUNCTION

0

1

2

3

4

5

6

7

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

0

1

0

1

2

3

RESERVED

EEPROM

If set to 1 it will 3-state the charge pump to act as a HOLD on Loss of Reference

Clocks ( Primary and Secondary)

8

4

HOLDONLOR

HOLD- Over

EEPROM

9

5

RESERVED

10

11

12

13

14

15

16

17

18

19

20

21

22

23

6

PH4ADJC0

7

PH4ADJC1

8

PH4ADJC2

9

PH4ADJC3

Output 4

Coarse phase adjust select for output divider 4

EEPROM

10

11

12

13

14

15

16

17

18

19

PH4ADJC4

PH4ADJC5

PH4ADJC6

OUT4DIVRSEL0

OUT4DIVRSEL1

OUT4DIVRSEL2

OUT4DIVRSEL3

OUT4DIVRSEL4

OUT4DIVRSEL5

OUT4DIVRSEL6

OUTPUT DIVIDER 4 Ratio Select

(See Table 7)

Output 4

EEPROM

When set to 0, the divider is disabled

When set to 1, the divider is enabled

24

25

20

21

EN4DIV

Output 4

EEPROM

PECL4HISWING

High Output Voltage Swing in LVPECL Mode if set to 1

CD1 PIN is high and DIVPHA4CD1H is set to low

Loads Output Divider 4 and Phase Adjust 4 into OUTPUT 4

CD1 PIN is high and DIVPHA4CD1H is set to high

Loads Output Divider 3 and Phase Adjust 3 into OUTPUT 4

26

27

22

23

DIVPHA4CD1H

DIVPHA4CD1L

CD1 High

CD1 Low

EEPROM

CD1 PIN is low and DIVPHA4CD1L is set to low

Loads Output Divider 4 and Phase Adjust 4 into OUTPUT 4

CD1 PIN is low and DIVPHA4CD1L is set to high

Loads Output Divider 3 and Phase Adjust 3 into OUTPUT 4

28

29

30

31

24

25

26

27

OUTBUF4CD2LX

OUTBUF4CD2LY

OUTBUF4CD2HX

OUTBUF4CD2HY

Output Buffer 4 Signaling Selection when CD2 in low

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

CD2 Low

CD2 High

EEPROM

Output Buffer 4 Signaling Selection when CD2 in high

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

40

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Register 5: CD Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

DESCRIPTION/FUNCTION

0

1

2

3

4

A0

A1

A2

A3

Address 0

1

0

1

0

Address 1

Address 2

Address 3

0

1

2

3

BIAS_DIV45<0>

BIAS_DIV45<1>

BIAS_DIV67<0>

BIAS_DIV67<1>

When BIAS_DIV45<1:0> =

00, No current reduction for all output-divider

01, Current reduction for all output-divider by about 20%

10, Current reduction for all output-divider by about 30%

Output Divider

4 and 5

EEPROM

5

6

7

When BIAS_DIV67<1:0> =

Output Divider

6 and 7

00, No current reduction for all output-divider

01, Current reduction for all output-divider by about 20%

10, Current reduction for all output-divider by about 30%

8

4

5

RESERVED

EEPROM

9

RESERVED

10

11

12

13

14

15

16

17

18

19

20

21

22

23

6

PH5ADJC0

7

PH5ADJC1

8

PH5ADJC2

9

PH5ADJC3

Output 5

Coarse phase adjust select for output divider 5

EEPROM

10

11

12

13

14

15

16

17

18

19

PH5ADJC4

PH5ADJC5

PH5ADJC6

OUT5DIVRSEL0

OUT5DIVRSEL1

OUT5DIVRSEL2

OUT5DIVRSEL3

OUT5DIVRSEL4

OUT5DIVRSEL5

OUT5DIVRSEL6

OUTPUT DIVIDER 5 Ratio Select

(See Table 7)

Output 5

EEPROM

When set to 0, the divider is disabled

When set to 1, the divider is enabled

24

25

20

21

EN5DIV

Output 5

EEPROM

PECL5HISWING

High Output Voltage Swing in LVPECL Mode if set to 1

CD1 PIN is high and DIVPHA5CD1H is set to low

Loads Output Divider 5 and Phase Adjust 5 into OUTPUT 5

CD1 PIN is high and DIVPHA5CD1H is set to high

Loads Output Divider 6 and Phase Adjust 6 into OUTPUT 5

26

27

22

23

DIVPHA5CD1H

DIVPHA5CD1L

CD1 High

CD1 Low

EEPROM

CD1 PIN is low and DIVPHA5CD1L is set to low

Loads Output Divider 5 and Phase Adjust 5 into OUTPUT 5

CD1 PIN is low and DIVPHA5CD1L is set to high

Loads Output Divider 6 and Phase Adjust 6 into OUTPUT 5

28

29

30

31

24

25

26

27

OUTBUF5CD2LX

OUTBUF5CD2LY

OUTBUF5CD2HX

OUTBUF5CD2HY

Output Buffer 5 Signaling Selection when CD2 in low

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

CD2 Low

CD2 High

EEPROM

Output Buffer 5 Signaling Selection when CD2 in high

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

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Register 6: CD Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

DESCRIPTION/FUNCTION

0

1

2

3

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

0

1

0

0 Feedback Frequency Detector is connected to the Lock Detector

1 Feedback Frequency Detector is disconnected from the Lock Detector

4

5

6

0

1

2

FB_FD_DESEL

RESERVED

LOCK-DET

EEPROM

Set to “0”

0 FB-Deterministic Clock divided by 1

1 FB- Deterministic Clock divided by 2

FBDETERM_DIV_SEL

FB-Divider /

Deterministic

Blocks

0 FB-Deterministic-DIV2-Block in normal operation

1 FB-Deterministic-DIV2 reset (here REG6_RB<2> == “0”)

7

8

9

3

4

5

FBDETERM_DIV2_DIS

FB_START_BYPASS

DET_START_BYPASS

EEPROM

0 FB-Divider started with delay block (RC), normal operation

1 FB-Divider can be started with external REF_SEL-signal (pin)

All Output

Dividers

0 Output-Dividers started with delay block (RC), normal operation

1 Output-Dividers can be started with external NRESET-signal (pin)

10

11

12

13

14

15

16

17

18

19

20

21

22

23

6

PH6ADJC0

7

PH6ADJC1

8

PH6ADJC2

9

PH6ADJC3

Output 6

Coarse phase adjust select for output divider 6

EEPROM

10

11

12

13

14

15

16

17

18

19

PH6ADJC4

PH6ADJC5

PH6ADJC6

OUT6DIVRSEL0

OUT6DIVRSEL1

OUT6DIVRSEL2

OUT6DIVRSEL3

OUT6DIVRSEL4

OUT6DIVRSEL5

OUT6DIVRSEL6

OUTPUT DIVIDER 6 Ratio Select

(See Table 7)

Output 6

EEPROM

When set to 0, the divider is disabled

When set to 1, the divider is enabled

24

25

20

21

EN6DIV

Output 6

EEPROM

PECL6HISWING

High Output Voltage Swing in LVPECL Mode if set to 1

CD1 PIN is high and DIVPHA6CD1H is set to low

Loads Output Divider 6 and Phase Adjust 6 into OUTPUT 6

CD1 PIN is high and DIVPHA6CD1H is set to high

Loads Output Divider 5 and Phase Adjust 5 into OUTPUT 6

26

27

22

23

DIVPHA6CD1H

DIVPHA6CD1L

CD1 High

CD1 Low

EEPROM

CD1 PIN is low and DIVPHA6CD1L is set to low

Loads Output Divider 6 and Phase Adjust 6 into OUTPUT 6

CD1 PIN is low and DIVPHA6CD1L is set to high

Loads Output Divider 5 and Phase Adjust 5 into OUTPUT 6

28

29

30

31

24

25

26

27

OUTBUF6CD2LX

OUTBUF6CD2LY

OUTBUF6CD2HX

OUTBUF6CD2HY

Output Buffer 6 Signaling Selection when CD2 in low

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

CD2 Low

CD2 High

EEPROM

Output Buffer 6 Signaling Selection when CD2 in high

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

42

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Register 7: CD Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

DESCRIPTION/FUNCTION

0

1

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

1

0

2

3

4

0

1

LOCKW 0

Lock-detect window bit 0 (Refer to Reg 9 RAM Bits 6 and 7)

Lock-detect window bit 1 (Refer to Reg 9 RAM Bits 6 and 7)

Set to 0

5

LOCKW 1

6

2

RESERVED

LOCKC0

LOCK-DET

EEPROM

7

3

Number of coherent lock events bit 0

8

4

LOCKC1

Number of coherent lock events bit 1

9

5

ADLOCK

Selects Digital PLL_LOCK 0 ,Selects Analog PLL_LOCK 1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

6

PH7ADJC0

7

PH7ADJC1

8

PH7ADJC2

9

PH7ADJC3

Output 7

Coarse phase adjust select for output divider 7

EEPROM

10

11

12

13

14

15

16

17

18

19

PH7ADJC4

PH7ADJC5

PH7ADJC6

OUT7DIVRSEL0

OUT7DIVRSEL1

OUT7DIVRSEL2

OUT7DIVRSEL3

OUT7DIVRSEL4

OUT7DIVRSEL5

OUT7DIVRSEL6

OUTPUT DIVIDER 7 Ratio Select

(See Table 7)

Output 7

EEPROM

When set to 0, the divider is disabled

When set to 1, the divider is enabled

24

25

20

21

EN7DIV

Output 7

EEPROM

PECL7HISWING

High Output Voltage Swing in LVPECL Mode if set to 1

CD1 PIN is high and DIVPHA7CD1H is set to low

Loads Output Divider 7 and Phase Adjust 7 into OUTPUT 7

CD1 PIN is high and DIVPHA7CD1H is set to high

Loads Output Divider 8 and Phase Adjust 8 into OUTPUT 7

26

27

22

23

DIVPHA7CD1H

DIVPHA7CD1L

CD1 High

CD1 Low

EEPROM

CD1 PIN is low and DIVPHA7CD1L is set to low

Loads Output Divider 7 and Phase Adjust 7 into OUTPUT 7

CD1 PIN is low and DIVPHA7CD1L is set to high

Loads Output Divider 8 and Phase Adjust 8 into OUTPUT 7

28

29

30

31

24

25

26

27

OUTBUF7CD2LX

OUTBUF7CD2LY

OUTBUF7CD2HX

OUTBUF7CD2HY

Output Buffer 7 Signaling Selection when CD2 in low

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

CD2 Low

CD2 High

EEPROM

Output Buffer 7 Signaling Selection when CD2 in high

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

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Register 8: CD Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

DESCRIPTION/FUNCTION

0

1

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

0

1

2

3

4

0

1

VCXOBUFSELX

VCXOBUFSELY

VCXOACDCSEL

VCXOHYSTEN

VCXOTERMSEL

VCXOINVBB

VCXO and AUX Input Buffer Type Select (LVPECL,LVDS or LVCMOS)

XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin

If Set to 0 AC Termination, If set to 1 DC Termination

If Set to 1 Input Buffers Hysteresis enabled

5

VCXO and AUX

Input Buffers

VCXO Input Buffer

6

2

EEPROM

7

3

8

4

If Set to 0 Input Buffer Internal Termination enabled

9

5

VCXO Input Buffer If Set to 1 It biases VCXO Input negative pin with internal VCXOVBB voltage

10

11

12

13

14

15

16

17

18

19

20

21

22

23

6

PH8ADJC0

7

PH8ADJC1

8

PH8ADJC2

9

PH8ADJC3

Output 8 and 9

Coarse phase adjust select for output divider 8 and 9

EEPROM

10

11

12

13

14

15

16

17

18

19

PH8ADJC4

PH8ADJC5

PH8ADJC6

OUT8DIVRSEL0

OUT8DIVRSEL1

OUT8DIVRSEL2

OUT8DIVRSEL3

OUT8DIVRSEL4

OUT8DIVRSEL5

OUT8DIVRSEL6

OUTPUT DIVIDER 8 and 9 Ratio Select

(See Table 7)

Output 8 and 9

EEPROM

When set to 0, the divider is disabled

When set to 1, the divider is enabled

24

25

20

21

EN89DIV

Output 8 and 9

Output 8

EEPROM

PECL8HISWING

High Output Voltage Swing in LVPECL Mode if set to 1

CD1 PIN is high and DIVPHA8CD1H is set to low

Loads Output Divider 8 and Phase Adjust 8 into OUTPUT 8

CD1 PIN is high and DIVPHA8CD1H is set to high

Loads Output Divider 7 and Phase Adjust 7 into OUTPUT 8

26

27

22

23

DIVPHA8CD1H

DIVPHA8CD1L

CD1 High

CD1 Low

EEPROM

CD1 PIN is low and DIVPHA8CD1L is set to low

Loads Output Divider 8 and Phase Adjust 8 into OUTPUT 8

CD1 PIN is low and DIVPHA8CD1L is set to high

Loads Output Divider 7 and Phase Adjust 7 into OUTPUT 8

28

29

30

31

24

25

26

27

OUTBUF8CD2LX

OUTBUF8CD2LY

OUTBUF8CD2HX

OUTBUF8CD2HY

Output Buffer 8 Signaling Selection when CD2 in low

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

CD2 Low

CD2 High

EEPROM

Output Buffer 8 Signaling Selection when CD2 in high

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

44

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Register 9: CD Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

DESCRIPTION/FUNCTION

0

1

2

3

4

5

6

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

1

0

1

0

1

2

HOLDF1

HOLDF2

HOLD

Enables the Frequency Hold-Over Function 1 on 1, off 0

Enables the Frequency Hold-Over Function 2 on 1, off 0

3-State Charge Pump 0 - (equal to HOLD-Pin function)

HOLD function always activated “1” (recommended for test purposes, only)

Triggered by analog PLL Lock detect outputs

If analog PLL Lock Signal is [1] (PLL locked), HOLD is activated

If analog PLL Lock Signal is [0] (PLL not lock), HOLD is deactivated

HOLD- Over

EEPROM

7

3

HOLDTR

8

9

4

5

HOLD_CNT0

HOLD_CNT1

HOLD1 Function is reactivated after X Ref Clock Cycles. Defined by

(HOLD_CNT0,HOLD_CNT1)::X= Number of Clock Cycles.

For (00)::X=64, (01) ::X=128, (10)::X=256, (11)::X=512 Clock Cycles.

10

11

6

7

LOCKW 2

LOCKW 3

Extended Lock-detect window Bit 2 (Also refer to Reg 7 RAM Bits 0 and 1)

Extended Lock-detect window Bit 3 (Also refer to Reg 7 RAM Bits 0 and 1)

LOCK-DET

Chip CORE

EEPROM

NOINV_RESHOL_IN

T

When set to 0, SPI/HOLD_INT and SPI/RESET_INT inverted (default)

When set to 1, SPI/HOLD_INT and SPI/RESET_INT not inverted

12

13

8

9

When GTME = 0, this bit has no functionality, But when GTME = 1, then:

When set to 0, START-Signal is synchronized to N/M Divider Input Clocks

When set to 1, START-Sync N/M Divider in PLL are bypassed

Diagnostic: PLL

N/M Divider

DIVSYNC_DIS

EEPROM

Divider START When set to 0, START-Signal is synchronized to VCXO-Clock

DETERM-Block When set to 1, START-Sync Block is bypassed

14

15

16

10

11

12

START_BYPASS

INDET_BP

EEPROM

Divider START When set to 0, Sync Logic active when VCXO/AUX-Clocks are available

DETERM-Block When set to 1, Sync Logic is independent from VCXO- and/or AUX-Clocks

Divider START When set to 0, Sync Logic waits for 1st PLL_LOCK state

DETERM-Block When set to 1, Sync Logic independent from 1st PLL_LOCK

PLL_LOCK_BP

When set to 0, Sync Logic is independent from VCXO/DIV_FB freq. (PLL-FD)

When set to 1, Sync Logic is started for VCXO/DIV_FB > ~600KHz,

stopped for VCXO/DIV_FB < ~600KHz

Divider START

DETERM-Block

17

13

LOW_FD_FB_EN

EEPROM

PLL

M/FB-Divider

When set to 0, M-Divider uses NHOLD1 as NPRESET

When set to 1, M-Divider NOT preseted by NHOLD1

18

19

14

15

NPRESET_MDIV

BIAS_DIV_FB<0>

When BIAS_DIV_FB<1:0> =

Feedback

Divider

00, No current reduction for FB-Divider

01, Current reduction for FB-Divider by about 20%

10, Current reduction for FB-Divider by about 30%

EEPROM

20

21

22

16

17

18

BIAS_DIV_FB<1>

BIAS_DIV89<0>

BIAS_DIV89<1>

When BIAS_DIV89<1:0> =

Output Divider

8 and 9

00, No current reduction for all output-divider

01, Current reduction for all output-divider by about 20%

10, Current reduction for all output-divider by about 30%

EEPROM

23

24

19

20

AUXINVBB

If Set to 1 it Biases AUX Input Negative Pin with internal VCXOVBB voltage.

AUX Buffer

Output 9

If Set to 1 AUX in input Mode Buffer is disabled. If Set to 0 it follows the

behavior of FB_MUX_SEL and OUT_MUX_SEL bits settings.

DIS_AUX_Y9

25

26

27

28

29

30

31

21

22

23

24

25

26

27

PECL9HISWING

RESERVED

High Output Voltage Swing in LVPECL Mode if set to 1

EEPROM

RESERVED

OUTBUF9CD2LX

OUTBUF9CD2LY

OUTBUF9CD2HX

OUTBUF9CD2HY

Output Buffer 9 Signaling Selection when CD2 in low

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

CD2 Low

CD2 High

EEPROM

Output Buffer 9 Signaling Selection when CD2 in high

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

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CDCE72010

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Register 10: CD Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

DESCRIPTION/FUNCTION

0

A0

Address 0

0

1

0

1

A1

Address 1

2

A2

Address 2

3

A3

Address 3

4

0

M0

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

M13

N0

Reference Divider M bit 0

Reference Divider M bit 1

Reference Divider M bit 2

Reference Divider M bit 3

Reference Divider M bit 4

Reference Divider M bit 5

Reference Divider M bit 6

Reference Divider M bit 7

Reference Divider M bit 8

Reference Divider M bit 9

Reference Divider M bit 10

Reference Divider M bit 11

Reference Divider M bit 12

Reference Divider M bit 13

VCXO Divider N bit 0

VCXO Divider N bit 1

VCXO Divider N bit 2

VCXO Divider N bit 3

VCXO Divider N bit 4

VCXO Divider N Bit 5

VCXO Divider N Bit 6

VCXO Divider N Bit 7

VCXO Divider N Bit 8

VCXO Divider N Bit 9

VCXO Divider N Bit 10

VCXO Divider N Bit 11

VCXO Divider N Bit 12

VCXO Divider N Bit 13

5

1

6

2

7

3

8

4

9

5

Reference

(PRI/SEC)

Divider M

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

6

EEPROM

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

N1

N2

N3

N4

N5

N6

VCXO/AUX/SEC

Divider N

EEPROM

N7

N8

N9

N10

N11

N12

N13

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Register11: CD Mode

SPI

BIT

RAM

BIT

POWER UP

CONDITION

BIT NAME

DESCRIPTION/FUNCTION

0

1

2

3

4

5

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

1

0

1

0

1

PRI_DIV2

SEC_DIV2

Input Buffers

If set to 1 Enables Primary Reference Divide by 2

If set to 1 Enables Secondary Reference Divide by 2

EEPROM

FB Path Integer

Counter 32

When set to 0, FB divider is active

When set to 1, FB divider is disabled

6

7

2

3

FB_DIS

EEPROM

FB Path Integer

Counter 32

When set to 0, FB clock is CMOS type

When set to 1, FB clock is CML type and uses CML2CMOS converter in PLL

FB_CML_SEL

FB-Divider /

Deterministic

Blocks

When set to 0, Input clock for FB not inverted (normal mode, low speed)

When set to 1, Input clock for FB inverted (higher speed mode)

8

4

FB_INCLK_INV

EEPROM

9

5

FB_COUNT32_0

FB_COUNT32_1

FB_COUNT32_2

FB_COUNT32_3

FB_COUNT32_4

FB_COUNT32_5

FB_COUNT32_6

FB_PHASE0

Feedback Counter Bit0

10

11

12

13

14

15

16

17

18

19

20

21

22

6

Feedback Counter Bit1

7

Feedback Counter Bit2

FB Path Integer

Counter 32

(P divider)

8

Feedback Counter Bit3

EEPROM

9

Feedback Counter Bit4

10

11

12

13

14

15

16

17

18

Feedback Counter Bit5

Feedback Counter Bit6

Feedback Phase Adjust Bit0

Feedback Phase Adjust Bit1

Feedback Phase Adjust Bit2

Feedback Phase Adjust Bit3

Feedback Phase Adjust Bit4

Feedback Phase Adjust Bit5

Feedback Phase Adjust Bit6

FB_PHASE1

FB_PHASE2

FB Path Integer

Counter 32

(P Divider)

FB_PHASE3

EEPROM

FB_PHASE4

FB_PHASE5

FB_PHASE6

If set to 0, PLL is in normal mode

If set to 1, PLL is powered down

23

24

25

19

20

21

PD_PLL

PLL

EEPROM

Clock Tree and

Deterministic

Block

FB_MUX_SEL

Table 8

When set to 0, the VCXO Clock is selected for the Clock Tree and FB-Div/Det

When set to 1, the AUX Clock is selected for the Clock Tree and FB-Div/Det.

OUT_MUX_SEL

Table 8

If Set to 0 it selects the VCXO Clock and if Set to 1 it selects the AUX Clock

EEPROM

Feed Back Path Selects FB/VCXO-Path when set to 0 (TI Test-GTME)

The Secondary Reference clock input is selected when set to 1 (TI Test-GTME)

26

27

28

29

30

31

22

23

24

25

26

27

FB_SEL

Diagnostics

NRESHAPE1

SEL_DEL1

RESET_HOLD

EPLOCK

Reshapes the Reference Clock Signal 0, Disable Reshape 1

Reference

Selection Control

EEPROM

If set to 0 it enables short delay for fast operation

If Set to 1 Long Delay recommended for input references below 150Mhz.

Reset Circuitry

Status

If set to 1 the RESET or HOLD pin acts as HOLD, set to 0 it acts as RESET.

EEPROM

Read only. If EPLOCK reads a 0, the EEPROM is unlocked. If EPLOCK reads a

1, then the EEPROM is locked.

EPSTATUS

Status

EEPROM Status

Table 8. Output Buffers Source Feed, PLL Source Feed, and AUX IN/OUTPUT 9 Selection

FB_MUX_SEL

OUT_MUX_SEL

PLL FEED AND OUTPUT FEED

AUX INPUT OR OUTPUT 9

0

1

0

1

0

1

VCXO::PLL, VCXO::Y0…Y9 and Deterministic Block

AUXIN::PLL, VCXO::Y0…Y8 and Deterministic Block

VCXO::PLL, AUXIN::Y0…Y8 and Deterministic Block

AUXIN::PLL, AUXIN::Y0…Y8 and Deterministic Block

OUTPUT 9 is Enabled⁽¹⁾

AUX IN is Enabled

(1) Default

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INTERFACE, CONFIGURATION, AND CONTROL

The CDCE72010 is designed to support various applications with SPI bus interface and without. In the case

where systems lack the SPI bus or a Boot up configuration is required at start up before the management layer is

up the built in EEPROM is used to provide this function.

The Interface bus takes the serialized address and data and writes to the specified RAM bits. The content of the

RAM bits are connected to logical functions in the device. Changing the content of the RAM bits (high or low)

instantly changes the logical functions inside the device.

At power up or after power down is de-asserted the contents of the EEPROM bits are copied to their

corresponding RAM bits. After that the content of RAM can be changed via the SPI bus. When writing to

EEPROM commands are detected on the SPI bus the control logic begins writing the content of the RAM bits

into the corresponding EEPROM bits. This process takes about 50ms. During this time the power supply should

be above 3.2V.

The on-chip EEPROM can be operated in its unlocked or locked mode. An unlocked EEPROM indicates that the

stored bit values can be changed on another EEPROM write sequence (available for up to a 100 EEPROM write

sequences). A locked EEPROM indicates that the stored bit values cannot be changed on another EEPROM

write sequence.

Control Signals

RAM Registers

Interface & Control

SPI

EEPROM Cells

Figure 15. Interface Control

UNIVERSAL INPUT AND REFERENCE CLOCK BUFFERS

The CDCE72010 is designed to support what is referred to as a Universal Input Buffer structure. This type of

buffer is designed to accept Differential or single ended inputs and it is sensitive enough to act as a LVPECL or

LVDS in differential mode and LVCMOS in Single ended mode. With the proper external termination various

types of inputs signals can be supported. Those inputs will be discussed in a separate document (application

Notes).

The CDCE72010 has two internal voltage biasing circuitries. One to set the termination voltage for references

(PRI_REF and SEC_REF) and the second biasing circuitry is to set the termination voltage to the VCXO_IN and

AUX_IN. This means that we can only have one type of differential signal on PRI_REF and SEC_REF and only

one type of differential signal on VCXO_IN and AUX_IN.

PRI_REF Buffer Settings

PRI_REF & SEC_REF Input Buffer Settings

Register / Bits

PRI_REF

Input

Switch

N

Configuration

Settings

0.0 0.1 1.2 1.3

P

INV

0.0 0.1 1.0

1.2

Hyst

Mode

Coup Term

DC N/A

Vbb

1.1

1.3/4

0

X

0

X

O

X

1

0

50W 50W

X

1

X

0

1

O

C

O

C

O

C

0

1

0

X

0

X

0

X

0

ON

LVCMOS

LVPECL

--

1

VBB

P

N

AC Internal 1.9V

DC Internal 1.2V

INV

1

0

1

X

0

1

0

1

0

X

0

ON

LVPECL

LVDS

1

-- External

AC Internal 1.2V

DC Internal 1.2V

--

INV

SEC_REF Buffer Settings

Register / Bits

P

N

Switch

1

0

LVDS

0.0 0.1 1.2 1.4

P

N

INV

50W 50W

X

LVDS

-- External

--

0

X

0

X

O

X

1

0

X

OFF --

ON --

--

0

1

X

1

X

0

1

O

C

O

C

O

C

SEC_REF

Input

Figure 16. PRI_REF and SEC_REF Voltage Biasing Circuitry

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VCXO Input Buffer Settings

VCXO & AUX Input Buffer Settings

Register / Bits

Switch

N

Configuration

Settings

8.0 8.1 8.4 8.5

P

INV

VCXO

Input

8.0 8.1 8.2

8.4

Hyst

Mode

Coup Term

DC N/A

Vbb

8.3

8.5

0

X

0

X

O

X

1

0

X

1

X

0

1

O

C

O

C

O

C

0

1

0

X

0

X

0

X

0

ON

LVCMOS

LVPECL

--

1

50W 50W

AC Internal 1.9V

DC Internal 1.2V

VBB

P

N

1

0

1

X

0

1

0

1

0

X

0

ON

LVPECL

LVDS

1

-- External

AC Internal 1.2V

DC Internal 1.2V

--

INV

1

0

LVDS

X

LVDS

-- External

--

AUX

Input

X

OFF --

ON --

--

0

1

Figure 17. VCXO_IN and AUX_IN Voltage Biasing Circuitry

AUTOMATIC/MANUAL REFERENCE CLOCK SWITCHING (SMART MUX)

The CDCE72010 supports two reference clock inputs, the primary clock input, PRI_REF, and the secondary

clock input, SEC_REF. The clocks can be selected manually or automatically. The respective mode is selected

by the dedicated SPI register. In the manual mode the external REF_SEL signal selects one of the two input

clocks

In the automatic mode the primary clock is selected by default even if both clocks are available. In case the

primary clock is not available or fails, then the input switches to the secondary clock until the primary clock is

back. The figure below shows the automatic clock selection.

PRI_REF

SEC_REF

1

2

3

4

1

2

Internal

Reference Clock

Auto-Reference

secondary

primary

VCXO With

100Hz Loop

Figure 18. Automatic Clock Select Timing

In the automatic mode the frequencies of both clock signals has to be similar but may differ by up to 20%. There

is no limitation placed on the phase relationship between the two inputs.

The clock input circuitry is designed to suppress glitches during switching between the primary and secondary

clock in the manual and automatic mode. This insures that the clock outputs continue to clock reliably when a

transition from a clock input occurs.

The phase of the output clock will slowly follow the new input phase. The speed of this transition is determined

by the loop bandwidth. However, there is no phase build-out function supported (like in SONET/SDH

applications).

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PHASE FREQUENCY DETECTOR

The main function of the CDCE72010 device is to synchronize a Voltage Control Oscillator (VCO) or a Voltage

Control Crystal Oscillator (VCXO) output to a reference clock input. The phase detector compares 2 signals and

outputs the difference between them. It is symbolized by an XOR. The compared signals are derived from the

Reference clock and from the VCO/VCXO clocks. The Reference clock is divided by the “R” Divider (1 or 2) and

“M” divider (14 Bits) and presented to the PFD. The VCO/VCXO clock is divided by the Feedback Divider “P” (1

to 80) and the “N” Divider (14 Bits) and presented to the PFD.

Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (P*N)/(R*M)

The PFD is a classical style with UP and DOWN signals generating flip-flops and a common reset path. Some

special functions were implemented:

•

Bit CP_DIR (register 0 RAM bit<9> can swap internally the REF- and FB-CLK inputs to the PFD flip-flops.

The reset path can be typically delayed with the bits DELAY_PFD <1:0> (register 0 RAM bit<7:6>) from 1.5ns

to 6.0ns.

PFD Pulse Width Delay (Register 0 RAM Bits [7:6])

The “PFD pulse width delay” gets around the dead zone of the PFD transfer function and reduces phase noise

and reference spurs.

Table 9. PFD Pulse Width Delay

PFD1

PFD0

PFD PULSE WIDTH DELAY

0

1

0

1

0

1

1.5ns⁽¹⁾

3.0ns

4.5ns

6.0ns

(1) Default

The PFD receives two clocks of the similar frequencies and decides if one is lagging or leading. This

Lagging/Leading signals are feed to the Charge Pump. The Charge Pump in its turn takes the Lagging/Leading

signals and translate them into current pulses that are feed to the external filter. The Output of the external filter

is a DC level that controls the Voltage reference of the VCO/VCXO sitting outside and feeding the CDCE72010

at the VCXO Input. The VCO/VCXO drifts its outputs frequency with respect to the voltage applied to its Voltage

Control pin. This is how the loop is closed.

PRI_REF

Maximum Frequency = 250 MHz

Div 1,2

0

1

2

3

4

5

6

7

8

9

10 11 12 13

::Register 10

Register 2

Register 11::

0

1

SEC_REF

RAM Bit 5:0

Div 1,2

PFD Out to

Charge Pump

R’ Divider

M Delay

N Delay

Smart Mux

P Divider

VCXO_IN

Feedback Mux

AUX_IN

M Divider (14 Bits)

N Divider (14 Bits)

Feedback Divider

1,2,3,4,5,6,8,10,12…..80

5

6

7

8

9

10 11

Divide Function Register 11::

::Register 10

14 15 16 17 18 19 20 21 22 23 24 25 26 27

Phase Function Register 11::

12 13 14 15 16 17 18

Maximum Frequency = 250 MHz

Figure 19. Phase Frequency Detection

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Table 10. Feedback Divider Settings

FEEDBACK DIVIDER SETTINGS (REGISTER 11: BITS)

DIVIDER

SETTING

11

0

1

0

10

1

0

9

0

1

8

0

1

0

1

7

0

1

0

1

0

1

0

1

6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

5

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

4'

6

8

10

8'

12

16

20

12'

18

24

30

16'

24'

32

40

20'

30'

40'

50

24'

36

48

60

28

42

56

70

32'

48'

64

80

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PHASE DELAY FOR M AND N

Delay Block in M/N Path

Table 11. Reference Delay M (PRI_REF or SEC_REF) and Feedback Delay N (VCXO) Phase Adjustment

(1)

(Register 2 RAM Bits [5:0])

DLYM2/DLYN2

DLYM1/DLYN1

DLYM0/DLYN0

PHASE OFFSET

0ps⁽²⁾

0

1

0

1

0

1

0

1

0

1

0

1

0

1

±160ps

±320ps

±480ps

±830ps

±1130ps

±1450ps

±1750ps

(1) If Progr Delay M is set, all Yx outputs are lagging to the Reference Clock according to the value set. If Progr Delay N is set, all Yx

outputs are leading to the Reference Clock according to the value set. Above are typical values at V_CC= 3.3 V, T_A= 25°C, PECL-output

relate to Div4 mode.

(2) Default

Table 12. Reference Divider M/N 14-Bit (Register 10 RAM Bits [13:0] for M and RAM Bits [27:14] for N)

N13

0

N12

0

N11

0

N10

0

N9

0

N8

0

N7

N6

0

N5

0

N4

0

N3

0

N2

0

N1

0

N0

0

DIV BY⁽¹⁾

0

1

2

3

4

0

1

0

1

0

1

•

0

1

128⁽²⁾

•

1

0

1

0

1

16382

16383

16384

(1) If the divider value is Q, then the code will be the binary value of (Q - 1).

(2) Default

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CHARGE PUMP

The Charge Pump drives the loop filter that controls the external VCO/VCXO. The Charge pump frequency is

determined by the PFD frequency since the function of the charge pump is to translate the UP DOWN signals of

the PFD into current pulses that drives the external filter. The Charge pump current is set by the control vector

ICP [3:0]. The error amplifier operates from 0.7V to the V_DDsupply voltage. See the table below for ICP settings.

Table 13. CP, Charge Pump Current (Register 0 RAM Bits [17:14])

TYPICAL CHARGE PUMP

ICP3

ICP2

ICP1

ICP0

CURRENT

0 µA (3-State)

200 µA

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

400 µA

600 µA

800 µA

1.0 mA

1.2 mA

1.4 mA

1.6 mA

1.8 mA

2.0 mA

2.2 mA⁽¹⁾

2.4 mA

2.6 mA

2.8 mA

3.0 mA

(1) Default

The ‘Preset Charge-Pump to V_{CC_CP}/2 is a useful feature to quickly set the center frequency of the VC(X)O after

Power-up or Reset. The adequate control voltage for the VC(X)O will be provided to the Charge-Pump output by

an internal voltage divider of 1KΩ/1KΩ to V_{CC_CP}and GND (V_{CC_CP}/2).

This feature helps to get the initial frequency accuracy, i.e. required at CPRI (Common Public Radio Interface) or

OBSAI (Open Base Station Architecture Initiative).

The Preset Charge-Pump to V_{CC_CP}/2 can be set and reset by SPI register.

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Charge-Pump Current Direction

The direction of the charge-pump (CP) current pulse can be changed by the SPI register settings. It determines

in which direction CP current will regulate (Reference Clock leads to Feedback Clock). Most applications use the

positive CP output current (power-up condition) because of the use of a passive loop filter. The negative CP

current is useful when using an active loop filter concept with inverting operational amplifier. The Figure below

shows the internal PFD signal and the corresponding CP current.

Reference Clock After

the M Divider and Delay

Reference Clock After

the N Divider and Delay

V(PFD1) (Internal Signal)

V(PFD2) (Internal Signal)

Charge Pump Output

Current Icp

Charge Pump Output

Current Icp (Inverted)

p

.

PFD pulse width delay improves spurious suppression.

Figure 20. Charge Pump

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PLL LOCK FOR ANALOG AND DIGITAL DETECT

The CDCE72010 supports two PLL Lock indications: the digital lock signal or the analog lock signal. Both signals

indicate logic high-level at PLL_LOCK if the PLL locks according the selected lock condition.

The PLL is locked (set high), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) and

Feedback Clock (VCXO_IN clock) at the PFD (Phase Frequency Detect) are inside a predefined lock detect

window for a pre-defined number of successive clock cycles.

The PLL is out-of-lock (set low), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) and

Feedback Clock (VCXO_IN clock) at the PFD are outside the predefined lock detect window.

Both, the lock detect window and the number of successive clock cycles are user definable in the SPI register

settings.

Selected REF at PFD

(clock fed through M Divider

and M Delay

t

(lockdetect)

VCXO_IN at PFD

(clock fed through N Divider

and N Delay)

Figure 21. PLL Lock

The lock detect window describes the maximum allowed time difference for lock detect between the rising edge

of PRI_REF or SEC_REF and VCXO_IN. The time difference is detected at the phase frequency detector. The

rising edge of PRI_REF or SEC_REF is taken as reference. The rising edge of VCXO_IN is outside the lock

detect window, if there is a phase displacement of more than +0.5*t_(lockdetect)or -0.5*t_(lockdetect)

.

Table 14. Lock-Detect Window (Register 7 RAM Bits [1:0] and Register 9 RAM Bits [7:6])

LOCKW3

[7]

LOCKW2

[6]

LOCKW1

[1]

LOCKW0

[0]

PHASE-OFFSET AT PFD-INPUT⁽¹⁾

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.5 ns

5.8 ns⁽²⁾

15.1 ns

Reserved

3.4 ns

7.7 ns

17.0 ns

Reserved

5.4 ns

9.7 ns

19.0 ns

Reserved

15.0 ns

19.3 ns

28.6 ns

Reserved

(1) Typical values at V_CC= 3.3 V, T_A= 25°C

(2) Default

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Table 15. Number of Successive Lock Events Inside the Lock Detect Window

(Register 7 RAM Bits [4:3]) the PLL Lock Signal is Delayed for Number of

FB_CLK Events

NO. OF SUCCESSIVE LOCK

LOCKC1

LOCKC0

EVENTS

0

1

0

1

0

1

16

64⁽¹⁾

256

(1) Default

DIGITAL LOCK DETECT

When selecting the digital PLL lock option, PLL_LOCK will possibly jitter several times between lock and out of

lock until a stable lock is detected. A single “low-to-high” step can be reached with a wide lock detect window

and high number of successive clock cycles. PLL_LOCK will return to out of lock if just one cycle is outside the

lock detect window.

V_Out

Digital Lock Detection

Power_Down

PLL_LOCK

Lock

Output

Lock_Out

160 kW

5pF

Out-of-Lock

t

Lock_In

V_high= 0.6 V_CC

V_low= 0.4 V_CC

Figure 22. Digital Lock

56

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ANALOG LOCK DETECT

When selecting the analog PLL Lock option, the high-pulses load the external capacitor via the internal 110 µA

current source until logic high-level is reached. Therefore, more time is needed to detect logic high level, but

jittering of PLL_LOCK will be suppressed like possible in case of digital lock. The time PLL_LOCK needs to

return to out of lock depends on the level of V_OUT, when the current source starts to unload the external

capacitor.

V_CC

110 µA

(Lock)

V_Out

PLL_LOCK

(Output)

Power_Down

Lock_Out

5pF

V_Out= 1/C * I * t

C

110 µA

(Out-of-Lock)

t

160 kW

Example:

for I = 110 µA, C = 10 n, V_CC= 3.3 V and

V_high= V_Out= 0.55 * V_CC= 1.8 V

=> t = 164 µs

Lock_In

V_high= 0.55 V_CC

V_low= 0.35 V_CC

Figure 23. Analog Lock

FREQUENCY HOLD-OVER MODE

The HOLD-Function is a CDCE72010 feature that helps to improve system reliability. The HOLD-Function holds

the output frequency in case the input reference clock fails or is disrupted. During HOLD, the Charge-Pump is

switched off (3-State) freezing the last valid output frequency. The Hold-Function will be released after a valid

reference clock is reapplied to the clock input and detected by the CDCE72010. For proper HOLD function, the

Analog PLL-Lock-Detect mode has to be active. The following settings are involved with the HOLD Function:

•

Lock Detect Window: Defines the window in ns inwhich the Lock is valid. The size is 3.5ns, 8.5ns, 18.5ns.

Lock is set if Reference Clock and Feedback Clock are inside this predefined Lock-Detect Window for a

pre-selected number of successive cycles.

•

Out-of-Lock: Defines the out-of-lock condition: If the Reference Clock and the Feedback Clock at the PFD are

outside the predefined Lock Detect Window.

Number of Clock Cycles: Defines the number of successive PFD cycles which have to occur inside the lock

window to set Lock detect. This does not apply for Out-of-Lock condition.

•

Hold-Function: Selects HOLD-Function (see more details below).

Hold-Trigger: Defines whether the HOLD-Function is always activated or whether it is dependent on the state

of the analog PLL Lock detect output. In the latter case, HOLD is activated if Lock is set (high) and

de-activated if Lock is reset (low).

•

Analog PLL Lock Detect: Analog Lock output charges or discharges an external capacitor with every valid

Lock cycle. The time constant for Lock detect can be set by the value of the capacitor.

The CDCE72010 supports two types of HOLD functions, one external controllable HOLD mode and one internal

mode, HOLD.

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EXTERNAL/HOLD FUNCTION

The Charge Pump can directly be switched into 3-State. This function is also available via SPI register. If logic

low is applied to HOLD pin the Charge Pump will be switched to 3-State. After HOLD pin is released, the charge

pump is switched back in to normal operation, with the next valid reference clock cycle at PRI_REF or SEC_REF

and the next valid feedback clock cycle at the PFD. During HOLD, all divider and all outputs are at normal

operation.

INTERNAL/HOLD FUNCTION

In Internal HOLD Function or HOLD-Over-Function the PLL has to be in lock to start the HOLD function. It

switches the Charge Pump in to 3-State when an ‘out-of-lock’ event occurs. It leaves the ‘3-State Charge Pump’

state when the Reference Clock is back. Then it starts a locking sequence of 64 cycles before it goes back to the

beginning of the HOLD-Over loop.

PLL has to be in LOCK to start

HOLD-Function.

(The Analog Lock output is not reset by the first Out-of-

Lock event. It stays ‘High’ depending on the analog time

delay(output C-load). The time delay must be long enough

to guarantee proper HOLD function)

The Charge-Pump remains into 3-State

until the Reference Clock is back. The 1^st

valid Reference Clock at the PFD releases

Frequency Hold-Over Function works in

combination with the Analog Lock-Detect

no

the Charge-Pump.

Charge-Pump is switched into 3-State.

no

yes

PLL

Out-of-Lock

PLL-Lock

Output Set

3-State

Charge Pump

Ref. Clock

is Back

64 PFD

Lock Cycles

Start

PLL is out-of-lock if the phase

difference of Reference Clock and

Feedback Clock at PFD are outside the

predefined Lock

-Detect-Window or if a

Cycle-Slip occurs.

no

The PLL acquire 64 lock cycles to phase

align to the input clock.

Figure 24. Frequency Hold Over

58

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OUTPUT DIVIDERS AND PHASE ADJUST

The CDCE72010 is designed with individual Output Dividers for Outputs 1 to 8. Output Divider 1 drives Output 1

and Output 0 and Output Divider 8 drives Output 8 and Output 9. Each output divider has a bypass function or it

is referred to as divide by “one”. Since divide by one bypasses the divider block it can address higher operating

frequencies.

The output divider is designed to address divide by 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 18, 20, 24, 28, 30, 32, 36, 40,

42, 48, 50, 56, 60, 64, 70 and 80.The output divider includes a coarse phase adjust that shifts the divided clock

signal. The phase adjust resolution is a function of the divide function. The maximum number of phase steps

equals to the divider setting.

If the output is divide by 2, then two phase adjustment settings (0 and 180 degrees) are available. The resolution

of phase adjustment is related to the output divider setting by the following: Phase adjust resolution = (1/Output

Divider settings) X 360 Degrees.

Example: For a 491.52MHz VCXO where one of the outputs of the device is set to divide by 16 for a 30.72MHz

desired output, this will mean that the 30.72MHz clock will have (1/16) X 360 = 22.5 Degrees of phase

adjustment resolution.

Output Divide Select (OUT#DIVSEL#) and Coarse Phase Adjust Select (PH#ADJC#) registers are located in

Register 1 thought 8 for Output 1 thought 8 respectively.

The Phase difference between 2 divider settings on different output can be calculated using the following formula

and referring to the Phase Lag number in the Output Divider Table ( see Table 7).

Integer Remainder of [(Phase Lag X - Phase Lag Y)/ Divide X ] as an example if we need to calculate the phase

difference between divide by 4 and divide by 8 with respect to divide by 4 clock.

The Integer Remainder [(28.5 - 0.5)/4] = 0. This means there is 0 Cycle phase delay between Divide by 4 and

Divide by 8 with respect to Divide by 4 Clock.

If we need to do the same calculation with respect to Divide by 8 we will have Intger Remainder [(28.5 – 0.5)/8] =

0.5 that means that there is 0.5 Cycles between Divide by 4 and divide by 8 with respect to a divide by 8 clock.

(PH#ADJC#)

Phase Adjust Period

Coarse Phase Adjust Select

Start Divider

D

Output Divider

(OUT#DIVSEL#)

Figure 25. Maximum Output Frequency With Phase Alighment

For a complete listing of the coarse phase adjust settings, refer to the "CDCE72010 Coarse Phase Adjust"

document.

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DEVICE LAYOUT

The CDCE72010 is a high performance device packaged in a QFN-64. The die has all the ground pins bounded

to the thermal PAD on the bottom of the package. Therefore it is essential that the connection from the thermal

PAD to the ground layers should be low impedance. In addition, the thermal path in a QFN package is via the

thermal PAD on the bottom of the package. Therefore, the layout of the PAD is very important and it will affect

the thermal performance as well as the overall performance of the device. The illustration shown provides

optimal performance in terms of thermal issues, inductance and power supply bypassing. The 10 X 10 Filled VIA

pattern recommended allows for a low inductance connection between the thermal ground pad and the ground

plane of the board. This pattern forms a low thermal resistive path for the heat generated by the die to get

dissipated through the ground plane and to the exposed bottom side ground pad. It is recommended that solder

mask not be used on this bottom side pad to maximize its effectiveness as a thermal heat sink. The

recommended layout drives the thermal conductivity to 22.8 C/W in still air and 13.8 C/W in a 100LFM air flow if

implemented on a JEDEC compliant test thermal board.

Top Side Thermal PAD Layout

Only two capacitors are illustrated.

Only one side of the pin pads is shown.

Bottom Side Thermal PAD Layout

Only two capacitors are illustrated.

Figure 26. Device Layout

60

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DEVICE POWER

The CDCE72010 is designed as a high performance device, therefore careful attention must be paid to device

configuration with respect to power consumption. Total power consumption of the device can be estimated by

adding up the total power consumed by each block in the device.

The Table below describes the blocks used and power consumed per block. The total power of the device can

be calculated by multiplying the number of blocks used by the power consumption per block.

Table 16. Device Power

INTERNAL BLOCK POWER AT 3.3V (Typ)

PLL Core and Input and Feedback Circuitries

Output Dividers

Output Buffers ( LVPECL-HISWING)⁽¹⁾

Output Buffers (LVDS-HISWING)⁽¹⁾

Output Buffers (LVCMOS at 122 MHz)⁽¹⁾

POWER DISSIPATED / BLOCK

NUMBER OF BLOCKS / DEVICE

530mW

180mW

150mW

75mW

1

8

10

20

50mW

(1) Output buffers can be a total of 10 LVDS, 10 LVPECL, or 20 LVCMOS.

125

Max Die Temp

100

75

50

25

0

JEDEC 0 LFM 25 C

JEDEC 100 LFM 25 C

RL 0 LFM 25 C

RL 100 LFM 25 C

JEDEC 0 LFM 85 C

JEDEC 100 LFM 85 C

RL 0 LFM 85 C

RL 100 LFM 85 C

0

1

2

3

4

Power (W)

Figure 27. Die Temperature

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LOOP FILTER

The CDCE72010 is designed to control an external Voltage Controlled Oscillator (VCO) or a Voltage Controlled

Crystal Oscillator (VCXO) and to synchronize the controlled oscillators to the input reference. Controlling the

Oscillator happens via a DC voltage that is applied to the Voltage control pin. This DC voltage is generated by

the CDCE72010 in the form of AC pulses that get filtered by the external loop filter.

CDCE72010

VccCP

VCO/VCXO

R3

Charge

Pump

Clock Out

R2

C2

C1

C3

Figure 28. Loop Filter

62

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UNIVERSAL OUTPUT BUFFERS

The CDCE72010 is designed to drive three types of clock signaling, LVPECL, LVDS, and LVCMOS from each of

the ten outputs. This super buffer that contains all three drivers is refered to as the Universal Output Buffer. Only

one driver can be enabled at one time. Each universal output buffer is made from four independent buffers in

parallel. When LVPECL mode is selected, only the LVPECL Buffer is enabled and the rest of the buffers are

3-stated and in low power mode. When Selecting LVDS, only the LVDS Buffer is enabled and the rest of the

buffers are 3-stated and in low power mode. When LVCMOS mode is selected, both LVCMOS drivers are

enabled. One LVCMOS buffer drives the negative side and the other buffer drives the positive pin.

The LVCMOS drivers are driven from the same output divider but have separate control bits. In SPI Mode, bits

22, 23, 24, and 25 of Registers 0 to 9 are used to put the LVCMOS buffer in active, inverting, low, or 3-state. In

CD Mode, those bits are used for different functions and the LVCMOS buffer can be active when selected or

3-state when their not.

LVCMOS

LVPECL

Register (0 to 9)

RAM Bits::

21

22

23

24

25

26

27

LVDS

LVCMOS

Figure 29. Universal Output Buffer

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Output Dividers Synchronization

The CDCE72010 is a 10 output clock device with 8 output dividers and to insure that all the outputs are

synchronous a synchronization startup circuitry is used. The synchronization circuitry generates a pulse to reset

all the dividers in a way, that a predictable synchronous output is generated. The Synchronization signal can be

generated from different sources and can be synchronized to a specific clock. The Block diagram below

illustrates the signal path of the Output Divider Sync Signal. This function is assured up to 500 MHz.

NOTE:

The minimum frequency required for the output synchronization block to work properly

is 1 MHz.

Any of the Conditions will Produce a Conditional SYNC Start Signal:

1- REG9 <Bit11> INDET_BP is set to “0” & VCXO or AUX_CLK is available

2- REG9<Bit12> PLL_LOCK_BP is set to “0” & we have 1^stLock State

3- REG11<Bit19> PD_PLL is set to “0”& the PLL is ON

4- REG9<Bit13> LOW_FD_FB_EN is set to “1” N Divider Input Frequency above 600KHz

5- Write Activity to the Output Divider (s)

6- REG12<Bit8> Set to 1 ( /RESET Bit is Set to “1”)

7- REG12<Bit7> Set to 1 ( /Power Down Bit is Set to “1”)

If the value of the bits described as inverted the function associated with it will be ignored

with respect to the sync start signal generation.

/RESET Pin

Feedback Clock

“1”

“0” REG6<Bit5>

DET_START_BYPASS

REG6<Bit2> FB_DETERM_DIV_SEL

“0” Feedback Divider Clock

“1” Divide by 2 Feedback Clock

“0”

“1”

Reference Clock

REG0<Bit4> VCXOSEL

Synchronizing Output Divider SYNC Signal

“0”

1” REG9<Bit10>

STARTBYPASS

OUTPUT DIVIDERS SYNC SIGNAL

Figure 30. Output Divider Synchronization Block Diagram

64

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POWER UP RESET, POWER DOWN MODE AND RESET OR HOLD

The CDCE72010 is designed to address various clock synchronization applications. Some functions can be set

to be in automatic and manual mode or some functions can be controlled by software or by the internal circuitry.

Figure 31 below explains the various functionalities of power up reset internal circuitry functionality, power down

functionality and reset functionality. The hold function shares the same block with Reset and one bit in the

EEPROM will select either function.

V_CC

Reset SPI Interface and Register 12 to Default

POR

(Force Sleep/PD and /RESET or /HOLD)

11 12

REG12:

Power All Clocking Circuitry Down

- Shut Down All Analog Circuitry (/PD = 0 or Sleep = 0)

- Shut Down All Digital Circuitry (/PD = 0 or Sleep = 0)

- Disable All Output Buffers (/PD = 0 or Sleep = 0)

Sleep

/PD

PD or

Sleep

- Load EEPROM Into RAM When Released (at Rising Edge of /PD)

Reset Digital Circuitry

- Disable All Output Buffers (When /RESET = 0)

- Reset PLL (Load With RAM Content Values at Rising Edge)

- Reset Output Dividers and Phase Adjust Circuitry (at Rising Edge)

Reset

Hold

Reset

or

Hold

/Reset_Hold

When Hold Function Is Asserted

- Tri-state the Charge Pump Output When /HOLD = 0

Hold Function Is Deasserted When

- /HOLD = 1 and We Have Valid Reference Clock

REG11:

REG4:

29

04

Loss of Reference

Figure 31. Powerup, Reset, and Powerdown Block Diagram

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REVISION HISTORY

Changes from Original (June 2008) to Revision A ......................................................................................................... Page

•

Changed Frequency equation result from (R*M)/(P*N) to (P*N)/(R*M)................................................................................. 2

Added table note to Table 4................................................................................................................................................. 19

Added table note to Register 0: SPI Mode table description............................................................................................... 21

Changed Register 12: SPI Mode (RAM only Register) Note............................................................................................... 33

Added table note to Register 0:CD Mode table description................................................................................................. 36

Added additional information to INTERFACE, CONFIGURATION, AND CONTROL description....................................... 48

Changed Figure 16 ............................................................................................................................................................. 48

Changed Figure 17 ............................................................................................................................................................. 49

Added “P” to PHASE FREQUENCY DETECTOR feedback divider description ................................................................. 50

Changed Frequency equation from (R*M)/(P*N) to (P*N)/(R*M)......................................................................................... 50

Deleted P is the product of X Divider and FB Divider R and X Divider is set to be divide by 1 or 2................................... 50

Changed Figure 19 by adding maximum frequency = 250 MHz ......................................................................................... 50

Added note to Output Dividers Synchronization description ............................................................................................... 64

66

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PACKAGE OPTION ADDENDUM

www.ti.com

10-Jul-2009

PACKAGING INFORMATION

Orderable Device

CDCE72010RGCR

CDCE72010RGCRG4

CDCE72010RGCT

CDCE72010RGCTG4

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

VQFN

RGC

64

2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

VQFN

RGC

2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

25-Jul-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

CDCE72010RGCR

CDCE72010RGCT

VQFN

RGC

64

2000

250

330.0

16.4

9.3

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

25-Jul-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

CDCE72010RGCR

CDCE72010RGCT

VQFN

RGC

64

2000

250

333.2

345.9

28.6

Pack Materials-Page 2

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	CDCE72010RGCTG4
厂家：	TEXAS INSTRUMENTS
描述：	Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor 十大输出高性能时钟同步器，抖动消除器和时钟经销商时钟驱动器逻辑集成电路
文件：	总73页 (文件大小：1782K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CDCE72010RGCTG4 [TI]

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