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CDCI6214

ZHCSGV7E –JULY 2017–REVISED JANUARY 2020

CDCI6214 超低功耗时钟发生器（具有 PCIe 支持、四路可编程输出和

EEPROM）

1 特性

3 说明

1

•

具有 4 路可编程输出的一个可配置的高性能低功耗

PLL

CDCI6214 器件是一款超低功耗时钟发生器。此器件在

锁相环的两个独立基准输入之间进行选择，并在可配置

的差分输出通道上产生多达四个不同的频率，还在

LVCMOS 输出通道上生成参考时钟。

•

RMS 抖动性能

–

支持不带 SSC 的第 1/2/3/4 代 PCIe

•

典型功耗：1.8V 时为 150mW⁽²⁾

四个输出通道中的每个通道均有一个可配置的整数分频

器。通过与输出多路复用器结合，这样可产生五种不同

的频率。时钟分配分频器通过确定性方式进行复位，以

便实现干净的时钟门控以及无毛刺更新功能。可通过灵

活的断电选项优化器件以便在工作和待机模式中实现最

低功耗。通常，四路 156.25MHz LVDS 输出在 1.8V

下消耗 150mW。100MHz HCSL 输出的 386fs 典型

RMS 抖动增强了 PCIe 应用的系统裕度。

通用时钟输入

–

差分交流耦合输入或 LVCMOS 输入：1MHz 至

250MHz

–

晶振输入：8MHz 至 50MHz

•

灵活输出频率

–

44.1kHz 至 350MHz

无毛刺输出分频器切换

四路可独立配置的输出

CDCI6214 由内部寄存器进行配置，可通过与 I²C 兼容

的串行接口和内部 EEPROM 来访问内部寄存器。

–

LVCMOS、LVDS 或 HCSL 输出

具有可编程摆幅的差分交流耦合输出（与

LVDS、CML-、LVPECL 兼容）

CDCI6214 采用小外形封装并以超低功耗通过单个基准

实现高性能时钟树。工厂和用户可编程的 EEPROM 使

得 CDCI6214 适合作为低功耗、易于使用、瞬时启动

的时钟解决方案。

•

完全集成的 PLL、可配置的环路带宽：100kHz 至

3MHz

通过单电源或混合电源供电以进行电平转

换：1.8V、2.5V 和 3.3V

器件信息⁽¹⁾

可配置 GPIO

–

状态信号

器件型号

CDCI6214

封装

VQFN (24)

封装尺寸（标称值）

最多 4 个独立输出使能端子

输出分频器同步

4.00mm × 4.00mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

•

灵活的配置选项

(2) 四路 LVDS 输出，156.25MHz（含晶振参考）。

–

与 I²C 兼容的接口：最高 400kHz

具有两个页面和外部选择引脚的集成 EEPROM

应用示例 CDCI6214

•

仅支持 100Ω 系统

Voltage Domain

1.8V / 2.5V / 3.3V

工业温度范围：–40ºC 至 85ºC

小外形封装：24 引脚 VQFN (4mm × 4mm)

FPGA

DAC

Crystal

2 应用

Voltage Domain

1.8V / 2.5V / 3.3V

CDCI6214

•

PCIe 第 1/2/3/4 代时钟

MCU

1G/10G 以太网交换机、NIC、加速器

测试和测量、手持设备

多功能打印机

Ethernet

LVCMOS

Crystal Copy

PCIe

Voltage Domain

1.8V / 2.5V / 3.3V

广播基础设施

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNAS734

CDCI6214

ZHCSGV7E –JULY 2017–REVISED JANUARY 2020

www.ti.com.cn

6.22 Timing Requirements, I²C-Compatible Serial

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 EEPROM Characteristics.......................................... 6

Interface (SDA/GPIO2, SCL/GPIO3) ....................... 11

6.23 Power Supply Characteristics ............................... 11

6.24 Typical Characteristics.......................................... 12

Parameter Measurement Information ................ 13

7.1 Parameters.............................................................. 13

Detailed Description ............................................ 17

8.1 Overview ................................................................. 17

8.2 Functional Block Diagram ....................................... 17

8.3 Feature Description................................................. 18

8.4 Device Functional Modes........................................ 26

8.5 Programming .......................................................... 27

8.6 Register Maps ........................................................ 36

Application and Implementation ........................ 86

9.1 Application Information............................................ 86

9.2 Typical Applications ................................................ 86

9.3 Do's and Don'ts....................................................... 89

9.4 Initialization Setup .................................................. 89

7

8

6.6 Reference Input, Single-Ended and Differential Mode

Characteristics (REFP, REFN, FB_P, FB_N) ............ 6

9

6.7 Reference Input, Crystal Mode Characteristics (XIN,

XOUT)........................................................................ 6

6.8 General-Purpose Input and Output Characteristics

(GPIO[4:1], SYNC/RESETN) ..................................... 6

6.9 Triple Level Input Characteristics (EEPROMSEL,

REFSEL).................................................................... 7

10 Power Supply Recommendations ..................... 91

10.1 Power-Up Sequence............................................. 91

10.2 De-Coupling .......................................................... 91

11 Layout................................................................... 91

11.1 Layout Guidelines ................................................. 91

11.2 Layout Examples................................................... 92

12 器件和文档支持 ..................................................... 94

12.1 器件支持 ............................................................... 94

12.2 接收文档更新通知 ................................................. 94

12.3 社区资源................................................................ 94

12.4 商标....................................................................... 94

12.5 静电放电警告......................................................... 94

12.6 Glossary................................................................ 94

13 机械、封装和可订购信息....................................... 95

6.10 Reference Mux Characteristics .............................. 7

6.11 Phase-Locked Loop Characteristics ....................... 7

6.12 Closed-Loop Output Jitter Characteristics .............. 8

6.13 Output Mux Characteristics .................................... 8

6.14 LVCMOS Output Characteristics ............................ 8

6.15 HCSL Output Characteristics ................................. 9

6.16 LVDS DC-Coupled Output Characteristics ............. 9

6.17 Programmable Differential AC-Coupled Output

Characteristics ........................................................... 9

6.18 Output Skew and Delay Characteristics ............... 10

6.19 Output Synchronization Characteristics................ 10

6.20 Timing Characteristics........................................... 10

6.21 I²C-Compatible Serial Interface Characteristics

(SDA/GPIO2, SCL/GPIO3) ...................................... 11

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision D (June 2019) to Revision E

Page

•

删除了数据表中的分数输出分频器 (FOD) 和扩频时钟 (SSC) 信息......................................................................................... 1

Added footnote to Timing Characteristics table ................................................................................................................... 10

Removed FOD from Functional Block Diagram ................................................................................................................... 17

Changed REFSEL selection from L to H.............................................................................................................................. 19

Removed Output Channel Divider Types and Delay table .................................................................................................. 21

Removed the FOD control bits in the Power Management graphic..................................................................................... 26

Added Page-mode EEPROM read instructions.................................................................................................................... 29

Changed Pre-Configured EEPROM Page 0 graphic............................................................................................................ 34

Changed Pre-Configured EEPROM Page 1 graphic............................................................................................................ 35

Removed fractional output divider information from the registers ....................................................................................... 36

Removed FOD information from the CDCI6214 Registers table.......................................................................................... 36

Added additional details on pullup resistor and load capacitor added to power-up sequence ............................................ 91

2

CDCI6214

www.ti.com.cn

ZHCSGV7E –JULY 2017–REVISED JANUARY 2020

Changes from Revision C (November 2018) to Revision D

Page

•

Added VDDREF and tablenote to the output supply voltage parameter in the Recommended Operating Conditions ......... 5

Added statement on chX_1p8vdet setting ........................................................................................................................... 20

Changed CDCI6214 - Pre-Configured EEPROM Page 0 graphic........................................................................................ 34

Changes from Revision B (April 2018) to Revision C

Page

•

Changed pin names for pins 1 and 2 from: XIN and XOUT to: XOUT/FB_P and XIN/FB_N. ............................................... 4

Changed descriptions for pins 1 and 2................................................................................................................................... 4

Changed pin names for pins 1 and 2 in Absolute Maximum Ratings .................................................................................... 5

Changed pin names for pins 1 and 2 in Reference Input, Single-Ended and Differential Mode Characteristics

(REFP, REFN, FB_P, FB_N).................................................................................................................................................. 6

•

Changed Input capacitance specification symbols in Reference Input, Single-Ended and Differential Mode

Characteristics (REFP, REFN, FB_P, FB_N) from: C_{IN_XOUT}and C_{IN_XIN}to: C_{IN_XOUT/FB_P}and C_{IN_XIN/FB_P}........................... 6

•

Changed pins 1 and 2 from: XIN and XOUT to: XOUT/FB_P and XIN/FB_N in the Functional Block Diagram ................. 17

Changed pins 1 and 2 from: XIN and XOUT to: XOUT/FB_P and XIN/FB_N in the Reference Block graphic................... 18

Changed External (XIN) pin to: FB_P/N in the Phase-Locked Loop Circuit graphic............................................................ 20

Changed pins 1 and 2 from: XIN and XOUT to: XOUT/FB_P and XIN/FB_N in the CDCI6214 - Pre-Configured

EEPROM Page 0 and CDCI6214 - Pre-Configured EEPROM Page 1 graphics ................................................................. 34

•

Changed pins XIN and XOUT to: XOUT/FB_P and XIN/FB_N in the Typical Applications schematics.............................. 86

Changed design parameter superscript to a subscript ........................................................................................................ 87

Changes from Revision A (October 2017) to Revision B

Page

•

Changed pinout pins 5 and 6 from NC to REFP, REFN inputs.............................................................................................. 4

Changed supply voltage maximum from: 3.6 V to: 3.65 V..................................................................................................... 5

Removed Skew between HCSL maximum from the Output Skew and Delay Characteristics table ................................... 10

Changes from Original (July 2017) to Revision A

Page

•

将器件状态从“预告信息”更改为“生产数据”.............................................................................................................................. 1

Changed REFSEL pin description to reflext REFMUX control. ........................................................................................... 22

3

CDCI6214

ZHCSGV7E –JULY 2017–REVISED JANUARY 2020

www.ti.com.cn

5 Pin Configuration and Functions

RGE Package

24-Pin VQFN

Top View

XOUT / FB_P

XIN / FB_N

VDDREF

REFSEL

REFP

1

2

3

4

5

6

18

17

16

15

14

13

Y2P

Y2N

VDDO12

VDDO34

Y3P

25 (GND)

REFN

Y3N

Not to scale

Pin Functions

TYPE

DESCRIPTION

NAME

NO.

1

XOUT/FB_P

XIN/FB_N

VDDREF

REFSEL

REFP

IO

I

Crystal Driver Output / LVCMOS Input / Differential Positive Reference

Crystal Input / Differential Negative Reference

Power Supply Pin for Input Path, Digital and EEPROM

Manual Reference Selection MUX for PLL, R_PU= 50 kΩ, R_PD= 50 kΩ

Differential Positive Reference

2

3

P

I

4

5

I

REFN

6

I

Differential Negative Reference

Y0

7

O

I

Output 0 Pin

RESETN/SYNC

Y4N

8

Chip Reset. Alternatively, Output Divider Sync, R_PU= 50 kΩ⁽¹⁾

9

O

IO

O

P

O

IO

O

I

Output 4 Negative Pin

Y4P

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

Output 4 Positive Pin

OE/GPIO4

SCL/GPIO3

Y3N

Global output enable (default) or programmable GPIO, R_PU= 50 kΩ⁽¹⁾

Serial interface clock (default) or programmable GPIO

Output 3 Negative Pin

Y3P

Output 3 Positive Pin

VDDO34

VDDO12

Y2N

Power Supply for Outputs 3 and 4

Power Supply for Outputs 1 and 2

Output 2 Negative Pin

Y2P

Output 2 Positive Pin

SDA/GPIO2

STATUS/GPIO1

Y1N

Serial interface data (default) or programmable GPIO

Status (default) or programmable GPIO, R_PU= 50 kΩ⁽¹⁾

Output 1 Negative Pin

Y1P

Output 1 Positive Pin

EEPROM Page Mode Select, R_PU= 50 kΩ, R_PD= 50 kΩ⁽¹⁾

EEPROMSEL

VDDVCO

GND

P

G

Power Supply Pin for VCO / PLL

Ground, Thermal Pad

(1) R_PUis an internal pullup resistor. R_PDis an internal pulldown resistor.

4

CDCI6214

www.ti.com.cn

ZHCSGV7E –JULY 2017–REVISED JANUARY 2020

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

VDDREF, VDDVCO, VDDO12, VDDO34

XIN/FB_P, XOUT/FB_N, REFP, REFN

Supply voltage

Input voltage

–0.3

3.65

V

VDDREF +

0.3

–0.3

V

STATUS/GPIO1, SDA/GPIO2, SCL/GPIO3, OE/GPIO4,

REFSEL, EEPROMSEL, RESETN/SYNC

VDDREF +

0.3

Input voltage

Output voltage

VDDO_x +

0.3

Y0, Y1P, Y1N, Y2P, Y2N, Y3P, Y3N, Y4P, Y4N

VDDREF +

0.3

STATUS/GPIO1, SDA/GPIO2, SCL/GPIO3, OE/GPIO4

T_J

Junction temperature

Storage temperature

125

150

ºC

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

VDDREF,

VDDVCO

Core supply voltage⁽¹⁾

1.71

3.465

V

VDDO1

VDDO2

VDDO3

VDDO4

T_A

Output supply voltage

Ambient temperature

1.71

3.465

85

V

1.71

V

1.71

V

–40ºC

ºC

(1) VDDREF and VDDVCO must be powered from the same supply voltage.

6.4 Thermal Information

CDCI6214

THERMAL METRIC⁽¹⁾

RGE (VQFN)

24 PINS

39.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

R_θJC(bot)

ψ_JT

29.5

16.9

Junction-to-case (bottom) thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

2.6

0.4

ψ_JB

16.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

5

CDCI6214

ZHCSGV7E –JULY 2017–REVISED JANUARY 2020

www.ti.com.cn

6.5 EEPROM Characteristics

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

each word

MIN

10

TYP

MAX

10,000

UNIT

cycles

years

n_EEcyc

t_EEret

EEPROM programming cycles

EEPROM data retention

10

6.6 Reference Input, Single-Ended and Differential Mode Characteristics (REFP, REFN, FB_P,

FB_N)

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_{IN_Ref}

V_IH

Reference frequency

1

250

MHz

0.8 ×

VDDREF

Input high voltage

Input low voltage

LVCMOS input buffer

V

0.2 ×

VDDREF

V_IL

LVCMOS input buffer

Differential input voltage swing,

peak-to-peak

VDDREF = 2.5 V or 3.3 V, AC-

coupled differential input buffer

V_{IN_DIFF}

0.5

1.6

1.0

Differential input voltage swing,

peak-to-peak

VDDREF = 1.8 V, AC-coupled

differential input buffer

V

dV_IN/dT

IDC

Input slew rate

Input duty cycle

20% – 80%

3

V/ns

40%

60%

No xtal active, on-chip load

disabled, at 25°C

C_{IN_XOUT/FB_P}Input capacitance

7

pF

No xtal active, on-chip load

disabled, at 25°C

C_{IN_XIN/FB_P}

C_{IN_REF}

Input capacitance

5

pF

at 25°C

6.7 Reference Input, Crystal Mode Characteristics (XIN, XOUT)

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

Fundamental mode

MIN

8

TYP

MAX

50

UNIT

MHz

Ω

f_{IN_Xtal}

Z_ESR

Crystal frequency

Crystal equivalent series resistance A supported crystal is within

30

100

Using on-chip load capacitance. A

Crystal load capacitance

C_L

5

100

3

8

pF

uW

pF

fF

supported crystal is within.

P_XTAL

C_{XIN_LOAD}

Crystal tolerated drive power

On-Chip load capacitance

A supported crystal tolerates up to

Programmable in typical 200-

fF steps at room temp

9.1

DNL_{XIN_LOAD}Differential non-linearity

at room temp

200

6.8 General-Purpose Input and Output Characteristics (GPIO[4:1], SYNC/RESETN)

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0.8 ×

VDDREF

V_IH

V_IL

Input high voltage

V

0.2 ×

VDDREF

Input low voltage

V

I_IH

Input high level current

Input low level current

Input slew rate

VIH = VDDREF

–0.02

0.004

–50

μA

I_IH

VIH = VDDREF, Pin 12, 19

VIL = GND

I_IL

μA

I_IL

VIL = GND, Pin 12, 19

20% – 80%

–0.004

μA

dV_IN/dT

C_{IN_GPIO}

0.5

V/ns

pF

Input Capacitance

10

6

CDCI6214

www.ti.com.cn

ZHCSGV7E –JULY 2017–REVISED JANUARY 2020

General-Purpose Input and Output Characteristics (GPIO[4:1], SYNC/RESETN) (continued)

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0.8 ×

VDDREF

V_OH

V_OL

Output high voltage

only capacitive load

V

0.2 ×

VDDREF

Output low voltage

only capacitive load

V

dV_OUT/dT Output slew rate

R_PUPullup resistance

20% - 80%, at 10pF

Pin 11, 20

0.3

77

V/ns

kΩ

6.9 Triple Level Input Characteristics (EEPROMSEL, REFSEL)

VDDVCO,VDDO12, VDDO34, VDDREF = 1.8V ±5%, 2.5V ±5%, 3.3V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0.8 ×

VDDREF

V_IH

V_IM

V_IL

Input high voltage

V

0.41 ×

VDDREF

0.5 ×

VDDREF

0.58 ×

VDDREF

Input mid voltage

Input low voltage

V

0.2 ×

VDDREF

I_IH

Input high level current

Input mid level current

Input low level current

input slew rate

VIH = VDDREF

40

–1

μA

ns

I_IM

VIH = VDDREF/2

VIL = GND

I_IL

–40

t_RIN

10% - 90%

50

C_{IN_TRI}

R_PDPU

10

pF

kΩ

64

6.10 Reference Mux Characteristics⁽¹⁾

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

XIN = Crystal 25 MHz, REF = 27

MHz

L_{REF_MUX}

Reference mux isolation

89

dBc

XIN = Crystal 25 MHz, REF =

24.576 MHz

Reference mux isolation

78

dBc

(1) Mux isolation is defined as the attenuation relative to the carrier base harmonic as a positive dBc number.

6.11 Phase-Locked Loop Characteristics

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_PFD

f_VCO

Phase detector frequency

1

100

MHz

Voltage-controlled oscillator

frequency

2400

2800

MHz

kHz

Configurable closed-loop PLL

bandwidth

f_BW

REF = 25 MHz

100

400

3000

700

f_CLKDIST

K_VCO

Clock distribution frequency

MHz

Voltage-controlled oscillator gain

f_VCO= 2.4 GHz

f_VCO= 2.5 GHz

f_VCO= 2.8 GHz

62

92

MHz/V

K_VCO

Allowable temperature drift for

continuous lock

|ΔT_CL

|

dT/dt ≤ 20 K / min

125

ºC

7

CDCI6214

ZHCSGV7E –JULY 2017–REVISED JANUARY 2020

www.ti.com.cn

6.12 Closed-Loop Output Jitter Characteristics

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

int. Range from 10 kHz to 20 MHz ,

XIN = Crystal 25 MHz, Integer

Output Divider, Yx = 156.25 MHz

LVDS

500

750

800

500

fs

int. Range from 10 kHz to 20 MHz ,

XIN = Crystal 25 MHz, Integer

Output Divider, Yx = 100 MHz HCSL

t_{RJ_CL}

RMS phase jitter

386

fs

PCIe Gen 3/4 Common Clock

transfer functions applied, XIN =

Crystal 25 MHz, Integer Output

Divider, Yx = 100 MHz HCSL

6.13 Output Mux Characteristics⁽¹⁾

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

REF = 27 MHz, XIN = 25 MHz, VCO

= 2500 MHz, PSFB = 4, Y_ODD =

312.5 MHz, Y_EVEN = 208.3 MHz,

LVPECL

L_{OUT_MUX}

Output mux isolation

65

dBc

REF = 27 MHz, XIN = 25 MHz, VCO

= 2500 MHz, PSFB = 4, Y_ODD =

312.5 MHz, Y_EVEN = 250 MHz,

LVPECL

Output mux isolation

63

72

64

57

dBc

REF = 27 MHz, XIN = 25 MHz, VCO

= 2500 MHz, PSFB = 4, Y_ODD =

312.5 MHz, Y_EVEN = 89.3 MHz,

LVPECL

REF = 27 MHz, XIN = 25 MHz, VCO

= 2500 MHz, PSFB = 4, IODs =

312.5 MHz, Yx=BYPASS (XIN),

LVPECL

REF = 27 MHz, XIN = 25 MHz, VCO

= 2500 MHz, PSFB = 4, Y_ODD =

100 MHz, Y_EVEN = 266.6 MHz,

LVPECL

(1) Mux isolation is defined as the attenuation relative to the carrier base harmonic as a positive dBc number.

6.14 LVCMOS Output Characteristics

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

f_{O_LVCMOS}Output frequency

TEST CONDITIONS

MIN

TYP

MAX

350

UNIT

MHz

V

VDDO_x = 2.5 V or 3.3 V, normal

drive

0.1

VDDO_x = 1.8 V, normal drive

0.1

250

V_{OH_LVCMO}

0.8 ×

VDDREF

Output high voltage

Normal mode, only capacitive load

S

V_{OL_LVCMO}

S

0.2 ×

VDDREF

Output low voltage

Normal mode, only capacitive load

Slow mode, only capacitive load

Normal mode

V

Ω

V_{OH_LVCMO}

S

0.7 ×

VDDREF

Output high voltage

V_{OL_LVCMO}

S

0.3 ×

VDDREF

Output low voltage

R_{ON_LVCMO}

S

Output impedance

28

80

R_{ON_LVCMO}

S

Output impedance

Weak mode

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LVCMOS Output Characteristics (continued)

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

L_{LVCMOS_10}

0M

f_CARRIER= 100 MHz, f_OFFSET= 10

MHz

Phase noise floor, single side band

–148

dBc/Hz

6.15 HCSL Output Characteristics

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

MIN

0.1

0.2

0.4

TYP

MAX

350

0.55

1.0

UNIT

MHz

V

f_{O_HCSL}

Output frequency

V_{CM_HCSL}Output common mode

0.34

V_OD

Differential output voltage

f_{O_HCSL}= 100 MHz

V

Differential output voltage, peak to

peak

V_SS

f_{O_HCSL}= 100 MHz

0.8

2.0

Vpp

mV

R_p= 49.9 Ω ±5%, f_{O_HCSL}= 100

MHz

V_CROSS

ΔV_CROSS

dV/dt

Absolute crossing point

250

550

w.r.t to average crossing

point, f_{O_HCSL}= 100 MHz

Relative crossing point variation

Slew rate for rising and falling edge

Slew rate matching

100

mV

Differential, at V_CROSS±150 mV,

f_{O_HCSL}= 100 MHz

1

4

V/ns

(1)

Single-ended, at V_CR₍₁_O₎_SS±75 mV,

f_{O_HCSL}= 100 MHz

ΔdV/dt

20%

ODC

R_P

Output duty cycle

Not in PLL bypass mode

45%

45

55%

55

Parallel termination

R_p= 49.9 Ω ±5% required

Ω

f_CARRIER= 100 MHz, f_OFFSET= 10

MHz

L_{HCSL_100M}Phase noise floor, single side band

(1) PCIe test load slew rate

-152

dBc/Hz

6.16 LVDS DC-Coupled Output Characteristics

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_{O_PRG_AC}Output frequency

0.1

350

MHz

VDDO_X = 2.5 V, 3.3 V,

chx_lvds_cmtrim_inc = 2

V_CM

Output common mode

1.125

1.2

0.9

1.375

V

VDDO_X = 1.8 V,

chx_lvds_cmtrim_inc = 2

0.8

1

V_OD

t_RF

Differential output voltage

Output rise/fall times

Output duty cycle

LVDS

0.25

0.3

0.45

V

LVDS (20% to 80%)

Not in PLL bypass mode

675

ps

ODC

45%

55%

L_{LVDS_DC_1}

00M

f_CARRIER= 100MHz, f_OFFSET

10MHz

=

Phase noise floor, single side band

–152

dBc/Hz

6.17 Programmable Differential AC-Coupled Output Characteristics

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C and AC-coupled

outputs

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MHz

V

f_{O_PRG_AC}Output frequency

0.1

350

V_OD

t_RF

Differential output voltage

LVDS-like

0.45

0.8

Differential output voltage

Output rise/fall times

CML-like

V

LVPECL-like

0.9

V

LVDS-like (20% to 80%)

675

ps

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Programmable Differential AC-Coupled Output Characteristics (continued)

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C and AC-coupled

outputs

PARAMETER

Output rise/fall times

Output duty cycle

TEST CONDITIONS

CML-like (20% to 80%)

MIN

TYP

520

500

MAX

UNIT

ps

t_RF

LVPECL-like (20% to 80%)

Not in PLL bypass mode

ps

ODC

45%

55%

L_{DIFF_AC_10}

0M

f_CARRIER= 100 MHz, f_OFFSET= 10

MHz

Phase noise floor, single side band

–152

dBc/Hz

6.18 Output Skew and Delay Characteristics

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_{SK_HCSL}

Skew between HCSL

Y[4:1] = HCSL, f_OY[4:1]= 100 MHz

140

ps

Y[4:1] = programmable output

swing, f_OY[4:1]= 100 MHz

t_{SK_DIFFAC}Skew between progr. differential AC

t_{SK_LVCMOS}Skew between LVCMOS

150

100

3

ps

ns

Y[4:1] = LVCMOS, f_OY[4:1]= 100

MHz

t_{SK_LVCMOS}

Y[4:0] = LVCMOS, f_OY[4:0]= 100

MHz

Skew between LVCMOS to Bypass

_BYP

REF = 67 MHz, VCO = 2680 MHz,

PSFB = 4, PSA_{Y_ODD}= 4,

t_{PD_ZDM}

Propagation delay

PSB_{Y_EVEN}= 4, IOD_{Y_ODD}= 10,

IOD_{Y_EVEN}= 10, Y_{P_ODD}= Y_{N_ ODD}

= IOD, in ext. ZDM, LVCMOS

–600

600

ps

6.19 Output Synchronization Characteristics

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

With respect to PLL reference rising

edge at 100 MHz with R = 1

t_{SU_SYNC}

t_{H_SYNC}

Setup time SYNC pulse

3

ns

With respect to PLL reference rising

edge at 100 MHz with R = 1

Hold time SYNC pulse

3

ns

With R = 1, at least 2 PFD periods

+ 24 feedback pre-scaler periods

t_{PWH_SYNC}High pulse width for SYNC

t_{PWL_SYNC}Low pulse width for SYNC

60

6

ns

With R = 1, at least 1 PFD period

Tri-state to first rising edge, f_Y[4:1]

200 MHz

<

t_EN

Individual output enable time⁽¹⁾

Individual output disable time⁽¹⁾

4

nCK

Last falling edge to tri-state, f_Y[4:1]

200 MHz

<

t_DIS

nCK

(1) Output clock cycles of respective output channel. Global output enable handled by digital logic, additional propagation will be added.

6.20 Timing Characteristics

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Initialization time from POR to

device releasing PLL outputs.

t_INIT

t_VDD

Initialization time⁽¹⁾

5

ms

Timing requirement for any VDD pin

while RESETN = LOW

Power supply ramp⁽²⁾⁽³⁾

50

2000

µs

(1) t_INIT= t_EELOAD+ t_STAB

(2) RESETN pin should be LOW until VDD reaches 95% of final value. TI recommends adding a pullup resistor of 4.7 kΩ and a capacitance

of 0.47 µF to Ground on RESETN pin to meet the POR timing requirement.

(3) After supply is settled within ±5% of target value, initial rising edge on RESETN will start internal logic. When POR voltage is exceeded

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6.21 I²C-Compatible Serial Interface Characteristics (SDA/GPIO2, SCL/GPIO3)

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0.7 ×

VDDREF

V_IH

V_IL

Input voltage, logic high

V

0.3 ×

VDDREF

Input voltage, logic low

V

V_HYS

I_IH

Input Schmitt trigger hysteresis

Input leakage current

VDDREF = 3.3 V, f_SCL= 400 kHz

VDDREF = 2.5 V, f_SCL= 400 kHz

VDDREF = 1.8 V, f_SCL= 400 kHz

VDDREF = 0.17 V..3.12 V

156

118

85

mV

μA

–10

10

At 3-mA sink current, VDDREF = 3.3

V – 5%

V_OL

Low-level output voltage

0.4

V

At 3-mA sink current, VDDREF = 2.5

V – 5%

0.4

At 2-mA sink current, VDDREF = 1.8

V – 5%

0.342

I_OL

Low-level output current

Input capacitance

V_OL= 0.4 V

3

mA

pF

C_IN

10

6.22 Timing Requirements, I²C-Compatible Serial Interface (SDA/GPIO2, SCL/GPIO3)

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ns

t_{PW_G}

f_SCL

Pulse width of suppressed glitches

SCL clock frequency

50

Standard

100

400

0.6

kHz

μs

f_SCL

SCL clock frequency

Fast-mode

t_{SU_STA}

Setup time start condition

SCL = V_IHbefore SDA = V_IL

SCL = V_ILafter SCL = V_IL. After this

time, the first clock edge is

generated.

t_{H_STA}

Hold time start condition

0.6

μs

SDA valid after SCL = V_IL, f_SCL

100 kHz

=

t_{SU_SDA}

Setup time data

250

100

ns

SDA valid after SCL = V_IL, f_SCL

400 kHz

=

t_{H_SDA}

Hold time data

SDA valid before SCL = V_IH

f_SCL= 100 kHz

0

4

μs

ns

t_{PWH_SCL}

t_{PWL_SCL}

t_OF

Pulse width high, SCL

Pulse width low, SCL

Output fall time

f_SCL= 400 kHz

0.6

4.7

1.3

f_SCL= 100 kHz

f_SCL= 400 kHz

C_OUT= 10..400 pF

250

6.23 Power Supply Characteristics

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

Reference input current

Crystal input current

TEST CONDITIONS

DBL = on

MIN

TYP

4

MAX

UNIT

mA

I_{DD_REF}

I_{DD_XIN}

Crystal with P_max= 200 μW

2

mA

f_VCO= 2500 MHz, PSFB = PSA = 4

and PSB = off

I_{DD_VCO}

I_{DD_OUT}

VCO and PLL current

Output channel current

13

10

mA

Activated output channel, 1x LVDS

156.25 MHz

I_{DD_IOD}

I_{DD_PDN}

Output integer divider current

Power-down current

2

3

mA

Using reset pin / bits

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Power Supply Characteristics (continued)

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= –40ºC to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

4x 156.25-MHz LVDS case using

crystal input and doubler

I_{DD_TYP}

Typical current

83

mA

Yx = 100 MHz LVDS, on one of

VDDx injected sine wave 50 mV at

f_INJ= 10 kHz,

L_PSNR

Power supply noise rejection⁽¹⁾

–56

–46

–49

–69

–74

–73

dBc

Yx = 100MHz LVDS, on one of

VDDx injected sine wave 50 mV at

f_INJ= 100 kHz

L_PSNR

Yx = 100MHz LVDS, on one of

VDDx injected sine wave 50 mV at

f_INJ= 1 MHz

Yx = 100MHz LVDS, on one of

VDDx injected sine wave 50 mV at

f_INJ= 10 MHz

Yx = 100MHz LVDS, on one of

VDDx injected sine wave 50 mV at

f_INJ= 20 MHz

Yx = 100MHz LVDS, on one of

VDDx injected sine wave 50 mV at

f_INJ= 40 MHz

(1) dBc with respect to output carrier frequency.

6.24 Typical Characteristics

VDDx = 1.8 V at room temperature

-20

-30

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-100

-110

-120

-130

-140

-150

-160

-170

-180

10²

10³

10⁴

10⁵

10⁶

10⁷

4x10⁷

10²

10³

10⁴

10⁵

10⁶

10⁷

4x10⁷

Frequency in Hz

Reference: Crystal

25 MHz

Closed-Loop Phase Noise 100-MHz HCSL

from 2.4-GHz VCO

Reference: Crystal

25 MHz

Closed-Loop Phase Noise 156.25-MHz

LVDS from 2.5-GHz VCO

Figure 1. 100-MHz Carrier

Figure 2. 156.25-MHz Carrier

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7 Parameter Measurement Information

7.1 Parameters

7.1.1 Reference Inputs

V

DD

R₁= 100 W

R

S

Z

O

= 50 W

XOUT/FB_P

XIN/FB_N

R

INT

mF

C = 0.1

R₂= 100 W

Clock Generator:

+ R = 50 W

R

INT

S

Figure 3. Single-Ended LVCMOS Crystal Input

Signal

Generator

100 ꢀ

< 2 V_PP

DUT

(1) Applied signal has to stay within V_{IN_DIFF}limits.

Figure 4. Differential AC-Coupled Input

7.1.2 Outputs

Scope

LVCMOS

50 ꢀ

DUT

GND

Figure 5. LVCMOS Output

<2 pF

GND

DUT

100 ꢀ

>100 kꢀ

LVDS

High

Impedance

Probe

<2 pF

GND

Figure 6. LVDS Output, DC-Coupled

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Parameters (continued)

Scope

50ꢀ

DUT

LVDS

GND

Figure 7. LVDS Output AC-Coupled

Scope

50ꢀ

CML,

LVPECL

DUT

GND

Figure 8. Differential AC-Coupled (CML, LVPECL)

QAx, QBx

V_OD

nQAx, nQBx

80%

0 V

20%

V_{OUT,DIFF,PP = 2xVOD}

t_f

Figure 9. Differential Output Voltage and Rise/Fall Time

Differential Waveform HCSL

+ / - 150 mV

(1) Differential waveform created using math function in scope subtracting positive from negative output pin waveform:

YxP - YxN.

(2) Slew rate measured using absolute ± 150 mV on the differential waveform. This correlates to the cross-point of the

single ended positive and negative waveform.

Figure 10. HCSL, Differential Rise and Fall Time

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Parameters (continued)

YxN

V_CROSSMEDIAN

YxP

V_CROSSMEDIAN+ 75 mV

V_CROSSMEDIAN- 75 mV

Figure 11. HCSL, Slew Rate Variation

YxN

û V_CROSS

YxP

(1) Measurement conducted using the single ended waveforms. Total variation of the crossing point of rising YxP and

falling YxN edges.

Figure 12. HCSL, Delta Crossing Voltage

R_Sꢀ

Balun

DUT

HCSL

R_Sꢀ

50 ꢀ

Figure 13. HCSL, Phase Noise Measurement

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Parameters (continued)

TI: 3.5 in

33 ꢀ

1 pF

< 1 pF

GND

>100 kꢀ

DUT

HCSL

Differential impedance 100 ꢀ

High

Impedance

Probe

1 pF

< 1 pF

GND

33 ꢀ

50 ꢀ

(1) Measured using Tektronix DPO75902SX oscilloscope. Recommended to use an oscilloscope bandwidth setting of 4/8

GHz and vertical setting of 50mV/division. Data processed using Clock Jitter Tool: Ver:1.6.7.2.

Figure 14. HCSL PCIe Test Load Setup

7.1.3 Serial Interface

ACK

STOP

START

t_IR

t_IF

t_{PWL_SCL}t_{PWH_SCL}

V_IH

V_IL

SCL

t_{H_STA}

t_{SU_STA}

t_BUS

t_{SU_SDA}

t_IR

t_{H_SDA}

t_{SU_STOP}

t_IF

V_IH

V_IL

SDA

Figure 15. I²C Timing

7.1.4 Power Supply

Sine

Wave

Modulator

Power Supply

Phase Noise/

Spectrum

Analyzer

Signal

Generator

DUT

Device Output

Balun

Reference

Input

Figure 16. PSNR Setup

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8 Detailed Description

8.1 Overview

The CDCI6214 clock generator is a phase-locked loop with integrated loop filter and selectable input reference.

The output of the integrated voltage-controlled oscillator (VCO) is connected to a clock distribution network,

which includes multiple frequency dividers and feeds four output channels with configurable differential and

single-ended output buffers.

8.2 Functional Block Diagram

VDDVCO

24

CDCI6214

7

Y0

LVCMOS

4

Differential

REFP

REFN

5

6

PSA

PSB

BYP

DS

IOD1

14 Bit

22

21

Y1P

Y1N

Phase Locked Loop

1 MHz

to 250 MHz

ch2

DS

100 kHz

to 3000 kHz

@25 MHz

ch1_mux

PSA

1 MHz

to 50 MHz

1 MHz

to 100 MHz

2400 MHz

to 2800 MHz

ch1_iod_mux

REFSEL

4

/4, /5, /6

x2

16 VDDO12

CP

LF

8 MHz

to 50 MHz

R

PFD

VCO

DS

8 Bits

PSB

/4, /5, /6

OSC

PSA

PSB

BYP

DS

XOUT/FB_P

XIN/FB_N

18

ch1

ch3

Y2P

Y2N

17

IOD2

14 Bit

N

PSFB

1

2

14 Bits

/4, /5, /6

ZDM

C_L

ch2_mux

ch2_iod_mux

3 pF

to 9 pF

LDOs for Analog

LDO for Digital

PSA

PSB

BYP

DS

IOD3

14 Bit

14

ch2

VDDREF

3

Y3P

Y3N

13

ch4

ch3_mux

ch3_iod_mux

M

Default

H

L

Osc.

Registers

15 VDDO34

12

19

SCL

SDA

I2C

Digital

Page 1

Page 0

PSA

PSB

BYP

DS

10

ch3

Y4P

Y4N

9

IOD4

14 Bit

GPIOGPIO GPO Reset Sync

DS

ch4_mux

ch4_iod_mux

EEPROM

11

20

8

23

EEPROMSEL

blockdiag_detailed_pg1p0_v7

GPIO4

GPIO1

RESETN / SYNC

Figure 17. CDCI6214 Clock Generator With Four Outputs

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8.3 Feature Description

The following sections describe the individual blocks of the CDCI6214 ultra-low power clock generator.

8.3.1 Reference Block

A reference clock to the PLL is fed to pins 1 (XOUT/FB_P) and 2 (XIN/FB_N) or to pins 5 (REFP) and 6 (REFN).

There are multiple input stages available to adapt to many clock references. The bit-fields that control the

reference input type selection are xin_inbuf_ctrl and ref_inbuf_ctrl.

The reference mux selects the reference for the PLL and the PLL-bypass path. For debug purposes ip_byp_mux

allows to connect the reference divider or doubler output to the clock distribution.

The buffers for the PLL-bypass path can be individually enabled and disabled using ip_byp_en_ch[4:1] and

ip_byp_en_y0.

ref_inbuf_ctrl

ch0_lvcmos_drv

REFP

REFN

5

6

ip_byp_en_y0

7

Y0

ip_byp_mux

4

REFSEL

4

ip_rdiv = 0

ref_mux

x2

ref_mux_src

PLL

chX

chX_iod_mux

ip_byp_en_chX

ip_xo_gm

R

ip_xo_gm_fine

ip_rdiv

ip_rdiv í 1

OSC

ip_xo_cload

1

2

XOUT/FB_P

XIN/FB_N

C_L

PLL

xin_inbuf_ctrl

Internal

Zero Delay

Feedback

Figure 18. Reference Block

8.3.1.1 Input Stages

8.3.1.1.1 Crystal Oscillator

The XIN and XOUT pins provide a crystal oscillator stage to drive a fundamental mode crystal in the range of 8

MHz to 50 MHz. The crystal input stage integrates a tunable load capacitor array up to 9 pF using ip_xo_cload.

The drive capability of the oscillator is adjusted using ip_xo_gm.

8.3.1.1.2 LVCMOS

The LVCMOS input buffer threshold voltage follows VDDREF. This helps to use the device as a level shifter as

the outputs have separate supplies.

8.3.1.1.3 Differential AC-Coupled

The differential input stage has an internal bias generator and should only be used with AC-coupled reference

inputs.

8.3.1.2 Reference Mux

Either XIN or REF can be selected as reference to the PLL and clock distribution path. The reference mux is

controlled using the REFSEL pin with ref_mux_src = 0 or the ref_mux bit-field with ref_mux_src = 1.

8.3.1.3 Reference Divider

A reference divider can be used to divide higher input frequencies to the permitted PFD range. It supports

division values of 1 to 255 using ip_rdiv.

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Feature Description (continued)

8.3.1.3.1 Doubler

The reference path contains a doubler circuit. It is used to double the input frequency and can be used to

achieve the highest PFD update frequency of 100 MHz using a 50-MHz crystal. The doubler activates using

ip_rdiv = 0.

8.3.1.4 Bypass-Mux

The input reference or the input to the PFD can be routed to the bypass path using ip_byp_mux.

8.3.1.5 Zero Delay, Internal and External Path

In zero delay mode the REF input clock is used as reference clock at the PFD. The FB_P clock (LVCMOS) or

FB_P/N clock (differential) can be used to feed an external source as feedback clock to the PFD. The external

feedback path is recommended for zero delay operation. Moreover there is an additional internal feedback path

which is sourced by output channel 2.

Table 1. Zero Delay Operation⁽¹⁾

Operation

Reference

Feedback

ref_mux_

src

ref_inbuf xin_inbuf zdm_mo zdm_cloc zdm_aut

ch2_iod_

div⁽²⁾

REFSEL

ref_mux

ip_rdiv

pll_psfb

pll_psa

pll_ndiv

_ctrl

de

ksel

o

Normal PLL, XIN

Reference

L

H

x

1

0

1

x

0

x

Normal PLL, REF

Reference

x

0

1

x

0

1

x

1

Normal PLL, REF

Reference

x

Zero Delay, Internal

Feedback

x

A

B

C

Zero Delay, External

Feedback

x

(1) 'x' allows any possible bit-field value. An entry of 'A', 'B' or 'C' indicates the same bit-field value.

(2) For internal feedback channel 2 is required. For external feedback the output clock connected to FB_P/N is recommended to have same

settings as default PLL feedback path.

8.3.2 Phase-Locked Loop

The CDCI6214 contains a fully integrated phase-locked loop circuit. The error between a reference phase and an

internal feedback phase is compared at the phase-frequency-detector. The comparison result is fed to a charge

pump that is connected to an integrated loop filter. The control voltage resulting from the loop filter tunes an

internal voltage-controlled oscillator (VCO). The frequency of the VCO is fed through a pre-scaler feedback

divider (PSFB) and another feedback divider back to the PFD.

The PLL closed-loop bandwidth is configurable using registers PLL0, PLL1, and PLL2.

•

Integer PLL

PFD operates 1 MHz to 100 MHz

Live Lock-Detector provides PLL lock status on status pin and bit lock_det (there is an additional sticky bit

unlock_s)

•

Integrated selectable loop filter components

For 25-MHz PFD bandwidths between 100 kHz and 3000 kHz can be achieved to optimize PLL to input

reference

•

Voltage-Controlled Oscillator (VCO) tuning range of 2400 to 2800 MHz

VCO is compatible to 0.5% spread spectrum (SSC) references at 100 MHz.

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Clock Distribution

/4, /5 /6

4

DS

Clock Distribution

Pre-Scaler A

Voltage Controlled

Oscillator

pll_cp_up

pll_cp_dn

pll_lf_res

R_Res

pll_psa

Charge

Pump

Reference Clock

Phase

Frequency

C_Pcap

C_Zcap

pll_lf_zcap

DS

Detector

Feedback Clock

/4, /5 /6

Clock Distribution

Pre-Scaler B

pll_lf_pcap

GND

pll_psb

Divider

Synchronization

14 Bit

Feedback Divider

/4, /5 /6

Feedback Pre-Scaler

DS

pll_ndiv

pll_psfb

zdm_mode

zdm_clocksel

FB_P/N

Internal (CH2)

Figure 19. Phase-Locked Loop Circuit

Table 2. Common Clock Generator Loop Filter Settings⁽¹⁾

I_CPin mA

pll_cp_up⁽²⁾

C_PcapIN pF

pll_lf_pcap

17.5

R_ResIN kΩ

C_ZcapIN pF

pll_lf_zcap

450

Phase

Margin in °

Damping

Factor

f_VCOin MHz

f_PFDin MHz

BW in MHz

pll_lf_res

2400

2457.6

2500

2680

2688

2800

25

50

0.51

67

0.9

2.0

2.5

0.97

1.41

1.04

0.49

0.93

0.38

0.93

0.36

1.00

67

68

67

68

67

68

67

68

1.3

1.2

1.4

0.9

1.3

1.0

2.0

2.4

1.8

2.0

0.2

1.5

0.2

2.6

1.3

17.5

2.5

1.5

2.5

5.5

2.5

3.5

1.5

450

100

61.44

25

17.5

450

17.5

450

17.5

450

50

17.5

450

67

19.5

480

48

17.5

480

96

19.5

480

50

17.5

450

100

17.5

450

(1) All values typical design targets.

(2) Program same value to pll_cp_dn.

8.3.3 Clock Distribution

The VCO connects to two individually configurable pre-scaler dividers sourcing the on-chip clock distribution.

The clock distribution consists of four output channels. Each output channel contains a divider with integer

division and synchronization capabilities.

A mux after each divider allows to feed the generated frequency to the adjacent output buffers. Thus for single

frequency clock generation only a single output divider needs to be active.

The output buffers are compatible to various signaling standards: LVDS, CML-like, LVPECL-like, LVCMOS and

HCSL using ch1_outbuf_ctrl.

•

HCSL must be directly connected to a load termination to ground. A series resistance can be used to adapt to

the trace impedance.

•

LVDS requires a differential termination connected between the positive and negative output buffer pins. The

termination can be connected directly or using AC-coupling. When using the LVDS output type, set

ch1_1p8vdet, ch2_1p8vdet, ch3_1p8vdet, andch4_1p8vdet to match the VDDO12 and VDDO34.

•

CML and LVPECL are only supported in an AC-coupled configuration. The receiver and the termination may

only be connected through AC-coupling capacitors to the device pins.

•

LVCMOS outputs are designed for capacitive loads only. A series resistance should be used to adapt the

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driver impedance to the trace impedance. For a typical 50-Ω trace, a resistor between 22 Ω to 33 Ω should be

used. The polarity of the positive and negative pins can be adjusted separately.

The output buffers support a wide frequency range of up to 350 MHz. Higher output frequencies up to 700 MHz

are functional, but are not covered by electrical specifications.

8.3.3.1 Output Channel

Figure 20. Clock Distribution Pre-Scaler Dividers⁽¹⁾

chX_sync_en

chX_iod_div

PSA

DS

chX-1

5 Bit

Digital Delay

YXP

YXN

14 Bit

Integer Divider

PSB

BYP

chX+1

chX_sync_delay

chX_mux

chX_iod_mux

chX_outbuf_ctrl

chX_mute_sel

chX_cmos_pol

chX_1p8vdet

Clock Distribution

chx_lvcmos_drv

Figure 21. Clock Distribution, Output Channel

INSTANCES

PSA

DIVISION VALUES

4, 5, 6

PSB

4, 5, 6

(1) A known phase relationship for divider synchronization with mixed division values is ensured by architecture.

Table 3. Output Buffer Signal Standards

OUTPUT

Y0

LVCMOS

HCSL⁽¹⁾

LVDS

AC-CML⁽²⁾

AC-LVPECL⁽²⁾

X

Y1

X

x

X

x

X

Y2

X

Y3

Y4

(1) For highest performance it is recommended to use HCSL on output Y1 or Y4.

(2) The common mode shall be provided externally through an external bias source, like a voltage divider or pullup resistor. The output

buffer will provide sufficient swing.

Table 4. Output Channel Signal Selection

NO.

0

INPUT SOURCE

Channel N-1

IOD N

Y1 (N=1)

Y2 (N=2)

Y3 (N=3)

Y4 (N=4)

x

1

x

2

Channel N+1

Table 5. Integer Divider Input Selection

NO.

0

SOURCE

Pre-scaler A

Pre-scaler B

Bypass

1

3

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8.3.3.2 Divider Glitch-Less Update

The bit fields ch1_glitchless_en can be used to enable glitch-less output divider update. This feature ensures that

the high pulse of a clock period is not cut off by the output divider update process. It ensures that setup and hold

time of a receiver is not violated. The low pulse in the transition from earlier period to the new period is extended

accordingly.

Glitch-Less Divider Disabled:

Glitch-Less Divider Enabled:

t_per1> t_per2

t_per1< t_per2

Figure 22. Glitch-Less Divider Update

8.3.4 Control Pins

The ultra-low power clock generator is controlled by multiple LVCMOS input pins.

EEPROMSEL acts as EEPROM page select. The CDCI6214 clock generator contains two pages of configuration

settings. The level of this pin is sampled after device power-up. A low level selects page zero. A high level

selects page one. The EEPROMSEL pin is a tri-level input pin. This third voltage level is automatically applied by

an internal voltage divider. The mid-level is used to select an internal default where the serial interface is

enabled.

RESETN/SYNC (pin 8) , SCL (pin 12), and SDA (pin 19) have a secondary functionality and can act as general-

purpose inputs and outputs (GPIO). This means that either the serial interface or the GPIO functionality can be

active.

RESETN/SYNC resets the internal circuitry and is used in the initial power-up sequence. The pin can be

reconfigured to act as synchronization input. The differential outputs are kept in mute while SYNC is low. When

SYNC is high, outputs are active. Moreover status signals can be driven by this pin.

SCL can act as general-purpose input.

SDA can act as general-purpose input and output.

REFSEL is used to select between the input references to the PLL. A low level selects the crystal reference on

XIN. A high level selects the differential input reference on REFP, REFN.

Table 6. Control and GPIO List

INPUT

OUTPUT

2-LEVEL

TERMINATION

RECONFIGU

RABLE?

2-LOGIC-

3-LOGIC-

LEVELS

NO.

NAME

GPIO

PULLDOWN

PULLUP

LEVELS

–

23

20

19

12

11

8

EEPROMSEL

STATUS

SDA

-

–

yes

–

50 kΩ

–

GPIO1

GPIO2

GPIO3

GPIO4

GPIO0

-

yes

–

yes

–

yes

–

SCL

–

OE

–

yes

–

50 kΩ

RESETN

REFSEL

–

4

yes

50 kΩ

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Table 7. GPIO - Input Signal List⁽¹⁾

SIGNAL NO.

ABBREVIATION

FREQ_INC

FREQ_DEC

OE (global)

OE_Y1

DESCRIPTION

0

1

2

4

5

6

7

Frequency increment; increments the IOD⁽²⁾

Frequency decrement; decrements the IOD.⁽²⁾

Enables or disables all differential outputs Y[4:1] (bypass not affected).⁽³⁾

(3)

Enables or disables Y1.

(3)

OE_Y2

Enables or disables Y2.

(3)

OE_Y3

Enables or disables Y3.

(3)

OE_Y4

Enables or disables Y4.

(1) Signals from this list are available on pin 11 (OE / GPIO4) and pin 20 (STATUS / GPIO1), see GENERIC1.

(2) Selected using bit mask in GENERIC3.

(3) Disable / Mute behaviour configured individually using ch_mute_sel bit in GENERIC0 table.

Table 8. GPIO - Output Signal List⁽¹⁾

SIGNAL NO.

ABBREVIATION

PLL_LOCK

DESCRIPTION

0 = PLL out of lock; 1 = indicates PLL in lock

0

1

XTAL_OSC

0 = crystal failure; 1 = crystal oscillates

0 = PLL (VCO) calibration ongoing; 1 = calibration done

0 = device logic busy; 1 = device operational

0 = output sync ongoing, muted; 1 = outputs released operational

0 = EEPROM idle; 1 = EEPROM access ongoing

0 = EEPROM pin sees low level; 1 = EEPROM pin sees high level

0 = EEPROM pin sees low or high level; 1 = EEPROM pin sees mid level

Indicates I²C slave address LSB config from loaded EEPROM

Clock, State machine

2

CAL_DONE

CONF_DONE

SYNC_DONE

EEPROM_BUSY

EEPROM_Y12

EEPROM_M12

I2C_LSB

3

4

5

6

7

8

9

CLK_FSM

10

11

12

13

14

CLK_PFD_REF

CLK_PFD_FB

BUF_SYNC

BUF_SCL

Clock, PFD, reference

Clock, PFD, feedback

buffered SYNC pin

buffered SCL pin

BUF_SDA

buffered received SDA pin

(1) Signals from this list are available on pin 8 (RESETN/SYNC or GPIO0), pin 11 (OE / GPIO4) and pin 20 (STATUS / GPIO1).

8.3.4.1 Global and Individual Output Enable: OE and OE_Y[4:1]

The output enable functionality allows to enable or disable all or a specific output buffer. The bypass copy on Y0

is excluded from the global output enable signal. When an output is disabled, it drives a configurable mute-state,

ch[4:1]_mute_sel. When the serial interface is deactivated one can use all individual output enable signals at the

same time, see mode. The individual output enable signal controls the respective output channel integer divider

to gate the clock. Therefore each integer divider needs to be active. When multiple outputs are sourced from the

(1)

same integer divider, the respective OE signal will enable/disable the output(s).

NOTE

When multiple output enable signals are configured on multiple-GPIO pins, then the global

output enable OE has higher priority than the individual output enable OE[4:1]. An

individual output enable OE[4:1] may only be configured on a single pin.

The individual output enable signal enables and disables the respective output in a deterministic way. Therefore

the high and low level of the signal is qualified by counting four cycles of the respective output clock. The

following steps can be seen in Figure 23:

1. The OE falling edge which disables the outputs.

2. Transition from logic high to logic low / logic low to logic high for Y2 after four rising edges.

(1) The GPIO direction of pins 12 and 19 is automatically set through the mode bit. Pin 11 and 20 must be set as inputs using gpio1_dir_sel

and gpio4_dir_sel bit in the GENERIC0 table.

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3. Transition from logic high to logic low / logic low to logic high for Y1 after four rising edges.

4. The OE rising edge which enables the outputs.

5. Output Y2 starts toggling after four rising edges.

6. Output Y1 starts toggling after four rising edges.

MUTE_SEL= Logic Low

OE

Y1P

1

2

3

4

1

2

3

4

Y1N

Y2P

Y2N

1

2

3

4

1

2

3

4

1

2

3

4

5

6

MUTE_SEL= Logic High

OE

Y1P

1

2

3

4

1

2

3

4

Y1N

Y2P

Y2N

1

2

3

4

1

2

3

4

1

2

3

4

5

6

Figure 23. Individual Output Enable and Disable

NOTE

The deterministic behaviour of the individual output enable is designed for an output

frequency up to 200 MHz.

8.3.5 Operation Modes

The device can operate in different modes.

Following operating modes can be set and the GPIOs configured. An operating mode change only becomes

effective when it is loaded from the EEPROM after a power cycle.

Table 9. Modes of Operation

DESCRIPTION

I²C + GPIOs

OEs

MODE

REFSEL

EEPROMSEL

GPIO4

I/O

GPIO3

SCL

GPIO2

SDA

GPIO1

I/O

Fallback

M

0

1

LH

I/O

SCL

SDA

I/O

OE4

OE3

OE2

OE1

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8.3.6 Divider Synchronization - SYNC

The output dividers can be reset in a deterministic way. This can be achieved using the sync bit or the pin 8

configured for SYNC function using gpio0_input_sel and gpio0_dir_sel. The level of the pin is qualified internally

using the reference frequency at the PFD. A low level will mute the outputs. A high level will synchronously

release all output dividers to operation, so that all outputs share a common rising edge, see Figure 24. The first

rising edge can be individually delayed in steps of the respective pre-scaler period, up to 32 cycles using

ch1_sync_delay. This allows to compensate external delays like routing mismatch, cables or inherent delays

introduced by logic gates in an FPGA design. Each channel can be included or excluded from the SYNC process

(1) (2)

using ch1_sync_en.

For a deterministic behaviour over power-cycles seen from input to output the reference divider must be set to 1.

It should not divide the reference clock nor should the reference doubler be used.

VCO

Clock Distribution Pre-Scaler Dividers

PS[BA]=4

PS[BA]=5

PS[BA]=6

Output Channel Dividers

All clocks muted.

PS[BA]=4

IOD=4

PS[BA]=5

IOD=4

PS[BA]=6

IOD=4

Internal SYNC

(ä PFD qualified)

1

2

3

Internal synchronization start

All signals muted

Synchronized dividers released

Figure 24. Divider Synchronization

(1) ch[4:1]_sync_en may only be activated with an active clock source selected in ch1_iod_mux bit in the CH1_CTRL2 table.

(2) The LVCMOS bypass output Y0 is not part of the SYNC process, neither are the dividers of the PLL.

Table 10. Digital Delay Step Size

PRE-SCALER STEP IN ns

VCO FREQUENCY IN MHz

/4

/5

/6

2400

2457.6

2500

1.67

1.63

1.60

1.43

2.08

2.03

2.00

1.79

2.50

2.44

2.40

2.14

2800

8.3.7 EEPROM - Cyclic Redundancy Check

The device contains a cyclic redundancy check (CRC) function for reads from the EEPROM to the device

registers. At start-up the EEPROM will be read internally and a CRC value calculated. One of the EEPROM

words contains an earlier stored CRC value. The stored and the actual CRC value are compared and the result

transferred to STATUS1 register. The CRC calculation can be triggered again by writing a '1' to the update_crc

bit. A mismatch between stored and calculated CRC value is informational only and non-blocking to the device

operation. Just reading back the CRC status bit and the live CRC value can speed up in-system EEPROM

programming and avoid reading back each word of the EEPROM for known configurations.

The polynomial used is CCITT-CRC16: x¹⁶+ x¹²+ x⁵+ 1.

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...

GENERIC0 ... GENERIC3 ...

CHX_CTRL4

Registers

STATUS1

nvmcrcerr

update_crc

CRC

(CCITT-CRC16)

Transfer Logic

EEPROM

Figure 25. EEPROM CRC

8.3.8 Power Supplies

The CDCI6214 provides multiple power supply pins. Each of the power supplies supports 1.8 V, 2.5 V, or 3.3 V.

Internal low-dropout regulators (LDO) source the internal blocks and allow each pin to be supplied with its

individual supply voltage. The VDDREF pin supplies the control pins and the serial interface. Therefore, any

pullup resistors shall be connected to the same domain as VDDREF. By default the LDOs are configured for

1.8-V ±5% operation.

8.3.8.1 Power Management

The device is very flexible with respect to internal power management. Each block offers a power-down bit and

can be disabled to save power when the block is not required. The available bits are illustrated in Figure 26. The

bypass output Y0 is connected to the pdn_ch4 bit. Each output channel has a bit which should be adapted to the

applied supply voltage, ch[4:1]_1p8vdet.

VDDREF

VDDVCO

VDDO12

VDDO34

3

24

16

15

pdn_ref

pdn_pll

pdn_ch1

pdn_ch3

pdn_pll_vco

ch1_1p8vdet

pdn_ch2

ch3_1p8vdet

pdn_ch4

pdn_pll_vcobuf

pdn_pll_vcobuf2

pdn_pll_cp

ch2_1p8vdet

ch4_1p8vdet

pdn_pll_pfd

pdn_pll_lockdet

pdn_pll_psfb

pdn_pll_psa

pdn_pll_psb

Figure 26. Power Management

8.4 Device Functional Modes

8.4.1 Pin Mode

In pin mode, pins 12 and 19 are input pins that act as individual output enable pins. Together with pins 11 and

20, this mode allows for one output enable pin per output channel.

8.4.2 Serial Interface Mode

In serial interface mode, pins 12 and 19 are configured as an I²C interface.

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Device Functional Modes (continued)

8.4.2.1 Fall-Back Mode

As the programming interface can be intentionally deactivated using the EEPROM, an accidental disabling of the

I²C blocks further access to the device. The serial interface can be forced using the fall-back mode. To enter this

mode, the user leaves pin 4 and pin 23 floating while the supply voltage is applied to VDDREF. In this mode, pin

11 is preconfigured as an input and pin 20 is configured as an output.

8.5 Programming

The CDCI6214 ultra-low power clock generator provides an I²C-compatible serial interface for register and

EEPROM access. The device is compatible to standard-mode I²C at 100 kHz and the fast-mode I²C at 400-kHz

clock frequency.

Table 11. I²C-Compatible Serial Interface, Slave Address Byte

7

6

5

4

3

2

1

0

Slave Address A[6:0]⁽¹⁾

R/W# Bit⁽²⁾

(1) The slave address consists of two sections. The hardwired MSBs A[6:2] and the software-selectable LSBs A[1:0].

(2) The R/W# bit indicates a read (1) or a write (0) transfer.

Table 12 shows the slave address decoding with respect to EEPROMSEL pin. This enables the user to avoid in-

system conflicts with different configurations, as the selected EEPROM page can be reflected in the slave

address least significant bit A0. Moreover a device being powered up in the silicon default, can always be

expected under the default address of 0xE9 for reads (or 0xE8 for writes).

Table 12. I²C-Compatible Serial Interface, Programmable Slave Address

A6

A5

A4

A3

A2

A1

0

A0

EEPROMSEL

MID

DESCRIPTION

Device Default

0

1

0

1

I2C_A0⁽¹⁾

I2C_A0⁽²⁾

LOW

EEPROM, Page 0

EEPROM, Page 1

1

HIGH

(1) Configuration Bit in EEPROM Page 0, default value of 0.

(2) Configuration Bit in EEPROM Page 1, default value of 1.

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The serial interface uses the following protocol as shown in Figure 27. The slave address is followed by a word-

wide register offset and a word-wide register value.

Write Transfer

7

1

S

Slave Address

Wr

A

8

1

Register Address High

A

Register Address Low

A

8

1

Date Byte High

A

Date Byte Low

A

P

Read Transfer

7

1

S

Slave Address

Wr

A

8

1

Register Address High

A

Register Address Low

A

7

1

Sr

Slave Address

Rd

A

8

1

Date Byte High

A

Date Byte Low

N

P

Legend

S

Sr

Start condition sent by master device

Write bit = 0 sent by master device

Acknowledge sent by master device

Stop condition sent by master device

Not-acknowledge sent by master device

|

Repeated start condition sent by master device

Read bit = 1 sent by master device

Wr Rd

A

P

N

A

Acknowledge sent by slave device

N

|

Not-acknowledge sent by slave device

Data sent by slave

Data

Data sent by master

Figure 27. I²C-Compatible Serial Interface, Supported Protocol

8.5.1 Recommended Programming Procedure

TI recommends programming the registers of the device in the following way:

1. Ensure that ee_lock is set when overwriting the EEPROM.

2. Configure the voltage domain bits appropriately ch[4:1]_1p8vdet.

3. Program register addresses in descending order from 0x44 to 0x00 including all register addresses with

reserved values.

8.5.2 EEPROM Access

NOTE

The EEPROM word write access time is typically 8 ms. The EEPROM_BUSY signal

indicates when the EEPROM is busy and can be observed as a status signal on a GPIO

pin to optimally time the writes (for example, in gpio4_output_sel).

There are two methods to write into the internal EEPROM:

1. Register Commit

2. EEPROM Direct Access

Use the following steps to bring the device into a known state and be able to conduct the programming:

1. Power down all device supplies

2. Apply RESETN=LOW.

3. Apply REFSEL=MID (leave tri-stated).

4. Apply EEPROMSEL=MID (leave tri-stated).

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5. Apply 1.8 V/2.5 V/3.3 V to all device supplies. When device operation is not required, only apply 1.8

V/2.5V/3.3 V to VDDREF.

6. Apply RESETN=HIGH.

7. Use the I²C interface to configure the device using slave address 0x74. See Table 12 for more details.

In the Register Commit flow all bits from the device registers are copied into the EEPROM. The

recommended flow is:

1. Pre-configure the device as desired, except the serial interface using mode.

2. Write 1 to recal to calibrate the VCO in this operation mode.

3. Select the EEPROM page, to copy the register settings into, using regcommit_page.

4. Unlock the EEPROM for write access with ee_lock = 0x5

5. Start the commit operation by writing a 1 to regcommit

6. Force a CRC update by writing a 1 to update_crc.

7. Read back the calculated CRC in nvmlcrc.

8. Store the read CRC value in the EEPROM by writing 0x3F to nvm_wr_addr and then the CRC value to

nvm_wr_data.

In the EEPROM Direct Access flow the EEPROM words are directly accessed using the address and the

data bit-fields. The recommended flow is:

1. Prepare an EEPROM image consisting of 64 words.

2. Unlock the EEPROM for write access with ee_lock = 0x5

3. Write the initial address offset to the address bit-field. Write a 0x00 to nvm_wr_addr.

4. Loop through the EEPROM image from address 0 to 63 by writing each word from the image to

nvm_wr_data. The EEPROM word address is automatically incremented by every write access to

nvm_wr_data.

5. The EEPROM read is similar to EEPROM write. First write 0x00 to nvm_rd_addr, then loop through all

bytes by reading from nvm_rd_data. The EEPROM word address is automatically incremented by every

write access to nvm_rd_data.

Write Transfer

I²C register

offset

15

6

5

0

Reserved

NVM_WR_ADDR

0x0E

NVM_WR_DATA

0x0D

Read Transfer

I²C register

offset

15

6

5

0

Reserved

NVM_RD_ADDR

0x0B

0x0C

NVM_RD_DATA

Copyright

Figure 28. EEPROM Direct Access Using I²C

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8.5.3 Device Defaults

The CDCI6214 contains the following defaults:

Table 13. CDCI6214 Register Defaults

ADDRESS

0x46

0x45

0x44

0x43

0x42

0x41

0x40

0x3F

0x3E

0x3D

0x3C

0x3B

0x3A

0x39

0x38

0x37

0x36

0x35

0x34

0x33

0x32

0x31

0x30

0x2F

0x2E

0x2D

0x2C

0x2B

0x2A

0x29

0x28

0x27

0x26

0x25

0x24

0x23

0x22

0x21

0x20

0x1F

0x1E

0x1D

0x1C

0x1B

0x1A

0x19

0x18

0x17

DEFAULT

EEPROM PAGE 0

EEPROM PAGE 1

0x00460000

0x00450000

0x00440000

0x00430020

0x00420000

0x00410F34

0x0040000D

0x003F0210

0x003E4210

0x003D1000

0x003C0010

0x003B0009

0x003A0008

0x00390A65

0x00380405

0x00370004

0x00360000

0x00358000

0x00340008

0x00330A65

0x00320405

0x00310004

0x00300000

0x002F8000

0x002E0008

0x002D0A65

0x002C0405

0x002B0004

0x002A0000

0x00298000

0x00280008

0x00270A65

0x00260405

0x00250004

0x00240000

0x00238000

0x00220050

0x00210007

0x00200000

0x001F1E72

0x001E5140

0x001D400A

0x001C0000

0x001B0000

0x001A0718

0x00190000

0x00180601

0x00170000

0x00460000

0x00450000

0x00440000

0x00430020

0x00420200

0x00410F34

0x0040000D

0x003F4210

0x003E4218

0x003D1500

0x003C0018

0x003B0061

0x003A0008

0x00398851

0x00380409

0x00370006

0x00360000

0x00358000

0x00340008

0x00338861

0x00320429

0x00310006

0x00300000

0x002F8000

0x002E0008

0x002D0851

0x002C0409

0x002B0006

0x002A0000

0x00298000

0x00280008

0x00270851

0x00260409

0x00250006

0x00240000

0x00238000

0x00220050

0x00210007

0x00200000

0x001F1E72

0x001E5140

0x001D000C

0x001C0000

0x001B0000

0x001A0A1C

0x00190406

0x00180601

0x00170595

0x00460000

0x00450000

0x00440000

0x00430020

0x00420200

0x00410F34

0x0040000D

0x003F4210

0x003E4218

0x003D1500

0x003C0018

0x003B0061

0x003A0008

0x00398851

0x00380008

0x00370000

0x00360000

0x00358000

0x00340008

0x00338861

0x00320431

0x00310006

0x00300000

0x002F8000

0x002E0008

0x002D0851

0x002C0010

0x002B0000

0x002A0000

0x00298000

0x00280008

0x00270851

0x00260409

0x00250006

0x00240000

0x00238000

0x00220050

0x00210007

0x00200000

0x001F1E72

0x001E5140

0x001D000C

0x001C0000

0x001B0000

0x001A0A1C

0x00192406

0x00180601

0x00170595

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Table 13. CDCI6214 Register Defaults (continued)

ADDRESS

0x16

0x15

0x14

0x13

0x12

0x11

0x10

0xF

DEFAULT

EEPROM PAGE 0

EEPROM PAGE 1

0x00160000

0x00150000

0x00140000

0x00130000

0x00120000

0x001126C4

0x0010921F

0x000FA037

0x000E0000

0x000D0000

0x000C0000

0x000B0000

0x000A0000

0x00090000

0x00080000

0x00070000

0x00060000

0x00050028

0x00040055

0x00030000

0x00020053

0x00016882

0x00000000

0x00160000

0x00150000

0x00140001

0x00130000

0x0012FFFF

0x001126C4

0x0010921F

0x000FA037

0x000E0000

0x000D0000

0x000C0000

0x000B0000

0x000AC964

0x0009C964

0x00080001

0x00070C0D

0x0006159F

0x00050028

0x00040055

0x00030000

0x00020053

0x00016865

0x00000001

0x00160000

0x00150000

0x00140001

0x00130000

0x0012FFFF

0x001126C4

0x0010921F

0x000FA037

0x000E0000

0x000D0000

0x000C0000

0x000B0000

0x000AC964

0x0009C964

0x00080001

0x00070C0D

0x000619CA

0x00050028

0x000400DD

0x00030800

0x00020053

0x00016864

0x00000000

0xE

0xD

0xC

0xB

0xA

0x9

0x8

0x7

0x6

0x5

0x4

0x3

0x2

0x1

0x0

Table 14. Default EEPROM Image

ADDRESS

Section

Word Value

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xEE00

0x490F

0x0362

0x0E00

0x1400

0xC104

0x0C00

0x5000

0x0861

0x8421

0x0006

0x0000

Base

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Table 14. Default EEPROM Image (continued)

ADDRESS

0xC

Section

Word Value

0x6501

0x5368

0xAA80

0x4382

0x0001

0x0030

0x4500

0x79C9

0x8000

0x0C00

0x1200

0x2904

0x0002

0x3002

0x4800

0xA410

0x0008

0xC008

0x2000

0x1045

0x0033

0x0020

0x8003

0x4104

0x39CA

0x0000

0xD

0xE

0xF

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

Page 0

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Table 14. Default EEPROM Image (continued)

ADDRESS

Section

Word Value

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x6400

0x5368

0xEE80

0x4382

0x0001

0x0030

0x4500

0x79C9

0x8000

0x0C00

0x1200

0x2904

0x0002

0x8000

0xA400

0x0008

0xC008

0x2000

0x1046

0x0033

0x0020

0x0000

0x4004

0x39CA

0xC964

Page 1

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VDDVCO

24

CDCI6214

7

Y0

Disabled

LVCMOS

4

Differential

REFP

5

6

REFN

DS

22

21

PSA

PSB

BYP

Y1P

Y1N

100 MHz

HCSL

Phase Locked Loop

6

25 MHz

ch2

DS

ch1_mux

970 kHz

4

1 MHz

ch1_iod_mux

50 MHz

2400 MHz

67 °

REFSEL

4

to 50 MHz

/4, /5, /6

x2

16 VDDO12 1.8 V

CP

LF

R

PFD

VCO

25 MHz

DS

8 Bits

PSB

/4, /5, /6

OSC

DS

6

XOUT

18

ch1

ch3

PSA

PSB

BYP

Y2P

Y2N

100 MHz

HCSL

12

4

1

2

17

ZDM

14 Bits

/4, /5, /6

C_L

ch2_mux

ch2_iod_mux

5 pF

XIN

LDOs for Analog

LDO for Digital

DS

14

13

ch2

PSA

PSB

BYP

VDDREF

3

Y3P

Y3N

100 MHz

HCSL

6

ch4

ch3_mux

ch3_iod_mux

M

H

L

Default

Osc.

Registers

15 VDDO34 1.8 V

12

19

OE3

OE2

I2C

Digital

Page 1

Page 0

DS

6

10

ch3

PSA

PSB

BYP

Y4P

Y4N

100 MHz

HCSL

9

GPIOGPIO GPO Reset Sync

DS

ch4_mux

ch4_iod_mux

EEPROM

11

OE4

20

8

23

blockdiag_detailed_pg1p0_v7

OE1

RESETN

EEPROMSEL

LOW

Figure 29. CDCI6214 - Pre-Configured EEPROM Page 0

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VDDVCO

24

CDCI6214

7

Y0

Disabled

LVCMOS

4

Differential

REFP

REFN

5

6

DS

22

21

PSA

PSB

BYP

Y1P

Y1N

100 MHz

HCSL

Phase Locked Loop

6

25 MHz

ch2

DS

ch1_mux

970 kHz

4

1 MHz

ch1_iod_mux

50 MHz

2400 MHz

67 °

REFSEL

4

to 50 MHz

/4, /5, /6

x2

16 VDDO12 1.8 V

CP

LF

R

PFD

VCO

25 MHz

DS

8 Bits

PSB

/4, /5, /6

OSC

DS

PD

XOUT/FB_P

18

ch1

ch3

PSA

PSB

BYP

Y2P

Powered Down

12

4

1

2

Y2N

17

ZDM

14 Bits

/4, /5, /6

C_L

ch2_mux

ch2_iod_mux

5 pF

XOUT/FB_N

VDDREF

LDOs for Analog

LDO for Digital

DS

14

13

ch2

PSA

PSB

BYP

3

Y3P

Y3N

100 MHz

LVPECL

6

ch4

ch3_mux

ch3_iod_mux

M

H

L

Default

Osc.

Registers

15 VDDO34 1.8 V

12

19

SCL

SDA

I2C

Digital

Page 1

Page 0

DS

PD

10

ch3

PSA

PSB

BYP

Y4P

Powered Down

Y4N

9

GPIOGPIO GPO Reset Sync

DS

ch4_mux

ch4_iod_mux

EEPROM

11

OE3

20

8

23

blockdiag_detailed_pg1p0_v7

OE1

RESETN

EEPROMSEL

HIGH

Figure 30. CDCI6214 - Pre-Configured EEPROM Page 1

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8.6 Register Maps

8.6.1 CDCI6214 Registers

Table 15 lists the memory-mapped registers for the CDCI6214.

NOTE

All register offset addresses not listed in Table 15 should be considered as reserved

locations and the register contents should not be modified.

NOTE

All bit-field combinations not listed in the description column should be considered as

reserved combinations and should only be programmed using the given values.

Table 15. CDCI6214 Registers

ADDRESS

ACRONYM

REGISTER NAME

SECTION

Generic setting, device operation mode, synchronization, control pins, reset, and

power down.

0h

GENERIC0

Go

1h

2h

GENERIC1

GENERIC2

GENERIC3

POWER0

POWER1

STATUS0

STATUS1

STATUS2

STATUS3

EEPROM0

EEPROM1

EEPROM2

EEPROM3

EEPROM4

STARTUP0

STARTUP1

STARTUP2

REV0

Generic settings, GPIO input signal selection.

Generic settings, GPIO output signal selection.

Generic settings, EEPROM and frequency increment / decrement.

Power-down bits, output channels.

Go

3h

4h

5h

Power-down bits, phase-locked-loop.

6h

Status information, calibration bus.

7h

Status information, PLL lock and EEPROM.

Status information, miscellaneous

8h

9h

Status information, live CRC of EEPROM

EEPROM, stored CRC of EEPROM

Ah

Bh

EEPROM, direct access read address

Ch

EEPROM, direct access read data

Dh

EEPROM, direct access write address

Eh

EEPROM, direct access write data

Fh

Start-up configuration, EEPROM lock, auto-calibration, and I2C glitch filter

Start-up configuration, digital state machine counters

Revision ID

10h

11h

18h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

21h

23h

24h

25h

INPUT0

Input reference, buffer configuration, and crystal oscillator controls.

Input reference, reference divider, and bypass buffers.

Input reference debug, status pin buffers.

PLL, feedback dividers.

INPUT1

INPUT_DBG0

PLL0

PLL1

PLL, charge pump current and clock distribution pre-scaler dividers.

PLL, loop filter configuration

PLL2

PLL4

PLL, lock detector and PFD delay

CH1_CTRL0

CH1_CTRL1

CH1_CTRL2

Output channel 1, RESERVED

Output channel 1, integer divider and mux control.

Output channel 1, synchronization, digital delay, output buffer, mux and mute

controls.

26h

CH1_CTRL3

Go

27h

28h

CH1_CTRL4

CH1_CTRL5

Output channel 1, divider glitchless enable and spread spectrum controls.

Output channel 1, RESERVED

Go

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Table 15. CDCI6214 Registers (continued)

ADDRESS

29h

ACRONYM

CH2_CTRL0

CH2_CTRL1

CH2_CTRL2

REGISTER NAME

SECTION

Go

Output channel 2, RESERVED

Output channel 2, integer divider and mux control.

2Ah

Go

2Bh

Go

Output channel 2, synchronization, digital delay, output buffer, mux and mute

controls.

2Ch

CH2_CTRL3

Go

2Dh

2Eh

2Fh

30h

31h

CH2_CTRL4

CH2_CTRL5

CH3_CTRL0

CH3_CTRL1

CH3_CTRL2

Output channel 2, divider glitchless enable and spread spectrum controls.

Output channel 2 , RESERVED

Go

Output channel 3, RESERVED

Output channel 3, integer divider and mux control.

Output channel 3, synchronization, digital delay, output buffer, mux and mute

controls.

32h

CH3_CTRL3

Go

33h

34h

35h

36h

37h

CH3_CTRL4

CH3_CTRL5

CH4_CTRL0

CH4_CTRL1

CH4_CTRL2

Output channel 3, divider glitchless enable and spread spectrum controls.

Output channel 3, RESERVED

Go

Output channel 4, RESERVED

Output channel 4, integer divider and mux control.

Output channel 4, synchronization, digital delay, output buffer, mux and mute

controls.

38h

CH4_CTRL3

Go

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

CH4_CTRL4

CH4_CTRL5

CHX_CTRL0

CHX_CTRL1

CHX_CTRL2

CHX_CTRL3

CHX_CTRL4

Output channel 4, divider glitchless enable and spread spectrum controls.

Output channel 4, RESERVED

Go

Output channels, generic clock distribution and bypass output controls.

Output channels, RESERVED

Complex bit access types are encoded to fit into small table cells. Table 16 shows the codes that are used for

access types in this section.

Table 16. CDCI6214 Access Type Codes

ACCESS TYPE CODE

READ TYPE

DESCRIPTION

R

Read

RC

C

R

to Clear

Read

WRITE TYPE

W

Write

WEX

WMC

WPD

WSC

WST

RESET OR DEFAULT VALUE

Value after reset or the default

value

-n

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8.6.1.1 GENERIC0 Register (Address = 0h) [reset = 0h]

GENERIC0 is shown in Figure 31 and described in Table 17.

Return to Summary Table.

Figure 31. GENERIC0 Register

15

14

13

12

11

10

9

8

i2c_a0

R/W-0h

gpio0_input_sel gpio4_dir_sel

gpio1_dir_sel

R/W-0h

gpio0_dir_sel

R/W-0h

zdm_clocksel

R/W-0h

RESERVED

R/W-0h

zdm_mode

R/W-0h

7

6

5

4

3

2

1

0

RESERVED

R/W-0h

pll_rst_lockdet

R/W-0h

sync

recal

resetn_soft

R/W-0h

swrst

powerdown

R/WPD-0h

mode

R/W-0h

R/WSC-0h

Table 17. GENERIC0 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15

i2c_a0

R/W

0h

When regcommit is used to program an EEPROM page, using

regcommit_page, this defines the LSB of the I²C slave address.

When a configuration is loaded into the registers from an EEPROM

page, this represents the saved LSB bit.

14

13

12

11

10

gpio0_input_sel

gpio4_dir_sel

gpio1_dir_sel

gpio0_dir_sel

zdm_clocksel

R/W

0h

Input signal select for GPIO0, Pin 8.

0h = RESETN

1h = SYNC

GPIO4 direction select.

0h = Input

1h = Output

GPIO1 direction select.

0h = Input

1h = Output

Direction select for Pin 8.

0h = Input

1h = Output

Selects the internal or external clock for calibration, in the ZDM

mode. In non-ZDM mode, always internal clock will be selected and

this register doesn't have any meaning.

0h = Internal Feedback

1h = External Feedback

9

8

RESERVED

zdm_mode

R/W

0h

RESERVED

Zero Delay Mode

0h = ZDM Off

1h = ZDM On

7

6

5

RESERVED

pll_rst_lockdet

sync

R/W

0h

RESERVED.

R/W

Reset (active high) to PLL lock detect circuit.

R/WSC

Generates sync pulse (for output decoder). This is a self clearing

register bit and writing '1' will create the SYNC pulse.

4

recal

R/WSC

0h

Self clearing bit. Writing '1' will do the re-calibration. For example -

after the configuration followed by calibration if '1' is written to this

register the calibration engine will start with the current capcode and

cross code.

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Table 17. GENERIC0 Register Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

3

resetn_soft

R/W

0h

Configure the pin RESETN/SYNC as a soft reset.

0h = Hard Reset (reset state machines and registers)

1h = Soft Reset (state machines only, register content stays as is)

2

swrst

R/WSC

0h

Soft reset bit. This is a self clearing bit. Writing a '0' has no effect

and writing a '1' creates a reset pulse which resets the digital logic

except the programmable registers. Also, this soft reset has similar

effect on digital logic as hard reset (RESENTN/SYNC). Soft reset will

restart the configuration and calibration.

1

0

powerdown

mode

R/WPD

R/W

0h

Analog Power Down.

0h = Active

1h = Power down

Mode of Operation.

0h = Serial Interface, I2C

1h = Pin Mode, Output Enable

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8.6.1.2 GENERIC1 Register (Address = 1h) [reset = 6A32h]

GENERIC1 is shown in Figure 32 and described in Table 18.

Return to Summary Table.

Figure 32. GENERIC1 Register

15

7

14

13

12

4

11

3

10

2

9

8

RESERVED

R/W-1Ah

ref_mux_src

R/W-0h

ref_mux

R/W-0h

6

5

1

0

gpio4_input_sel

R/W-3h

gpio1_input_sel

R/W-2h

Table 18. GENERIC1 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-10

9

RESERVED

R/W

1Ah

RESERVED

ref_mux_src

R/W

0h

3h

Reference mux control signal source.

0h = Pin

1h = ref_mux bit-field

8

ref_mux

Reference mux bit override.

0h = XIN

1h = REF

7-4

gpio4_input_sel

GPIO4 input signal select. Do not choose the same signal on

gpio1_input_sel.

2h = OE

4h = OE1

5h = OE2

6h = OE3

7h = OE4

3-0

gpio1_input_sel

R/W

2h

GPIO1 input signal select.Do not choose the same signal on

gpio4_input_sel.

2h = OE

4h = OE1

5h = OE2

6h = OE3

7h = OE4

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8.6.1.3 GENERIC2 Register (Address = 2h) [reset = 53h]

GENERIC2 is shown in Figure 33 and described in Table 19.

Return to Summary Table.

Figure 33. GENERIC2 Register

15

14

13

12

4

11

10

gpio0_output_sel

R/W-0h

9

8

0

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

7

6

5

3

2

1

gpio4_output_sel

R/W-5h

gpio1_output_sel

R/W-3h

Table 19. GENERIC2 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-12

RESERVED

R/W

0h

Reserved.

11-8

gpio0_output_sel

R/W

0h

GPIO0, Pin 8, output select ,

0h = PLL_LOCK

1h = XTAL_OSC

2h = CAL_DONE

3h = CONF_DONE

4h = SYNC_DONE

5h = EEPROM_BUSY

6h = EEPROM_Y12

7h = EEPROM_M12

8h = I2C_LSB

9h = CLK_FSM

Ah = CLK_PFD_REF

Bh = CLK_PFD_FB

Ch = BUF_SYNC

Dh = BUF_SCL

Eh = BUF_SDA

7-4

gpio4_output_sel

R/W

5h

GPIO4 , output select ,

0h = PLL_LOCK

1h = XTAL_OSC

2h = CAL_DONE

3h = CONF_DONE

4h = SYNC_DONE

5h = EEPROM_BUSY

6h = EEPROM_Y12

7h = EEPROM_M12

8h = I2C_LSB

9h = CLK_FSM

Ah = CLK_PFD_REF

Bh = CLK_PFD_FB

Ch = BUF_SYNC

Dh = BUF_SCL

Eh = BUF_SDA

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Table 19. GENERIC2 Register Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

3-0

gpio1_output_sel

R/W

3h

GPIO1 , output select ,

0h = PLL_LOCK

1h = XTAL_OSC

2h = CAL_DONE

3h = CONF_DONE

4h = SYNC_DONE

5h = EEPROM_BUSY

6h = EEPROM_Y12

7h = EEPROM_M12

8h = I2C_LSB

9h = CLK_FSM

Ah = CLK_PFD_REF

Bh = CLK_PFD_FB

Ch = BUF_SYNC

Dh = BUF_SCL

Eh = BUF_SDA

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8.6.1.4 GENERIC3 Register (Address = 3h) [reset = 0h]

GENERIC3 is shown in Figure 34 and described in Table 20.

Return to Summary Table.

Figure 34. GENERIC3 Register

15

14

13

12

11

10

9

8

disable_crc

update_crc

nvmcommit

regcommit

regcommit_pag

e

RESERVED

R/W-0h

R/WMC-0h

R/WSC-0h

R/W-0h

7

6

5

4

3

2

1

0

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/WSC-0h

RESERVED

R/WSC-0h

RESERVED

R/W-0h

Table 20. GENERIC3 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15

disable_crc

R/W

0h

Disable the CRC computation. However if Page is selected CRC will

happen after PoR (power on reset from analog). For example- after

the calibration if this bit is set to '1' and apply a soft reset (or reset

through pin) the configuration will bypass the CRC computation.

14

update_crc

R/WMC

0h

This is a self clearing register bit. Writing a '1' will cause the re-

computation of CRC. The computed CRC can be read from the live

CRC (nvmlcrc) register after the status bit nvmbusyh = 0.

13

12

11

nvmcommit

R/WSC

R/W

0h

Commits contents of the EEPROM page selected by

REGCOMMIT_PAGE to internal register. This register will self-clear

regcommit

Commits contents of the registers to EEPROM selected by

REGCOMMIT_PAGE register. This register will self-clear.

regcommit_page

Decide which page of EEPROM to use for the Register/NVM commit

operations. Note= this register is used only after the initial power-up

configuration from EEPROM if any. Once power-up configuration is

done with the page chosen by EEPROMSEL the value of this

register will be used for subsequent configurations using

Register/NVM commit operations.

0h = Page 0

1h = Page 1

10-3

2-1

0

RESERVED

R/W

0h

Reserved

R/WSC

R/W

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8.6.1.5 POWER0 Register (Address = 4h) [reset = 54h]

POWER0 is shown in Figure 35 and described in Table 21.

Return to Summary Table.

Figure 35. POWER0 Register

15

14

13

12

11

10

9

8

RESERVED

R/W-0h

7

6

5

4

3

2

1

0

pdn_ch4

R/W-0h

RESERVED

R/W-1h

pdn_ch3

R/W-0h

RESERVED

R/W-1h

pdn_ch2

R/W-0h

RESERVED

R/W-1h

pdn_ch1

R/W-0h

RESERVED

R/W-0h

Table 21. POWER0 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-8

RESERVED

pdn_ch4

R/W

0h

Reserved.

7

R/W

0h

Powers Down CH4 LDO.

0h = Active

1h = Power down

6

5

RESERVED

pdn_ch3

R/W

1h

0h

Reserved.

Powers Down CH3 LDO.

0h = Active

1h = Power down

4

3

RESERVED

pdn_ch2

R/W

1h

0h

Reserved.

Powers Down CH2 LDO.

0h = Active

1h = Power down

2

1

RESERVED

pdn_ch1

R/W

1h

0h

Reserved.

Powers Down CH1 LDO.

0h = Active

1h = Power down

0

RESERVED

R/W

0h

Reserved.

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8.6.1.6 POWER1 Register (Address = 5h) [reset = 30h]

POWER1 is shown in Figure 36 and described in Table 22.

Return to Summary Table.

Figure 36. POWER1 Register

15

14

13

12

11

10

9

8

RESERVED

pdn_pll_vcobuf

2

pdn_pll_vco

pdn_pll_vcobuf

R/W-0h

5

R/W-0h

7

6

4

3

2

1

0

pdn_pll_cp

R/W-0h

pdn_pll_lockdet pdn_pll_psfbb

R/W-0h R/W-1h

pdn_pll_psfba

R/W-1h

RESERVED

R/W-0h

pdn_pll_pfd

R/W-0h

pdn_pll_psfb

R/W-0h

pdn_ref

R/W-0h

Table 22. POWER1 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-11

RESERVED

R/W

0h

Reserved.

10

pdn_pll_vcobuf2

R/W

0h

1h

Power down of VCO buffer LDO.

0h = Active

1h = Power down

9

pdn_pll_vco

Power down of VCO LDO.

0h = Active

1h = Power down

8

pdn_pll_vcobuf

pdn_pll_cp

Power down of VCO buffer.

0h = Active

1h = Power down

7

Power down of charge pump LDO.

0h = Active

1h = Power down

6

pdn_pll_lockdet

pdn_pll_psfbb

pdn_pll_psfba

Power down of PLL lock detector.

0h = Active

1h = Power down

5

Power down of PLL feedback pre-scaler.

0h = Active

1h = Power down

4

Active low enable of prescaler-a. Active (low) during PoR and '1'

later. 1h = Power Down PFD. 0h = Otherwise.

3

2

RESERVED

pdn_pll_pfd

R/W

0h

Reserved.

Active low enable of PFD. Inactive (high) till calibration and '0'

afterwards. 1h = Power Down PFD. 0h = Otherwise.

1

0

pdn_pll_psfb

pdn_ref

R/W

0h

Active low enable of prescaler. Active (low) during PoR and '1' later.

1h = Powers Down PS, 0h = Otherwise.

Powers Down Input Path LDO. Kill Switch. Do not use. 1h = PD, 0h

= Otherwise.

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8.6.1.7 STATUS0 Register (Address = 6h) [reset = 0h]

STATUS0 is shown in Figure 37 and described in Table 23.

Return to Summary Table.

Figure 37. STATUS0 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

cal_status

R-0h

Table 23. STATUS0 Register Field Descriptions

BIT

15-0

FIELD

cal_status

TYPE

RESET

DESCRIPTION

R

0h

Calibration word.

8.6.1.8 STATUS1 Register (Address = 7h) [reset = 0h]

STATUS1 is shown in Figure 38 and described in Table 24.

Return to Summary Table.

Figure 38. STATUS1 Register

15

14

13

12

11

10

9

8

RESERVED

R-0h

lock_det_a

pll_vco_cal_rea nvm_rd_error

dy

nvm_wr_error

R-0h

RC-0h

7

6

5

4

3

2

1

0

rd_error

R-0h

wr_error

R-0h

nvmcrcerr

R-0h

nvmbusy

R-0h

cal_done

R-0h

config_done

R-0h

unlock_s

R/WEX-0h

lock_det

R-0h

Table 24. STATUS1 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-12

RESERVED

R

0h

Reserved.

11

10

lock_det_a

R

0h

Reads the PLL Lock status. 0h: PLL is Unlocked. 1h: PLL is locked.

VCO Buffer LDO POR can be read through this register.

pll_vco_cal_ready

9

nvm_rd_error

RC

0h

Occurs when any NVM operation is issued during Read Phase of the

NVM. The Read Phase of the NVM includes CRC calculation or a

simple read through RD NVM Addr/Data registers from any NVM

location or a NVM commit operation.

8

nvm_wr_error

RC

0h

Occurs when any NVM operation is issued during Write Phase of the

NVM. Write Phase of the NVM includes a simple write into any NVM

location through WR NVM Addr/Data registers or a Register Commit

operation.

7

6

5

rd_error

wr_error

nvmcrcerr

R

0h

Reading using the I2C interface with an address above the address

of the last register gives this error.

Writing using the I2C interface with an address above the address of

the last register gives this error.

NVM CRC Error Indication. The NVMCRCERR bit is set to 1 if a

CRC Error has been detected when reading back from on-chip

EEPROM during device configuration. This bit will be cleared when

NVMCOMMIT is submitted or Update CRC is issued.

4

nvmbusy

R

0h

NVM Program Busy Indication. The NVMBUSY bit is 1 during an on-

chip EEPROM Erase/Program cycle. While NVMBUSY is 1 the on-

chip EEPROM cannot be accessed. When the NVM operation is

completed this bit will be cleared. NVM related operations are

REGcommit NVMcommit CRC calculation or simple Read/Write

through RD/WR NVM.

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Table 24. STATUS1 Register Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

3

cal_done

R

0h

1h = Calibration (Two rounds of Amplitude followed by calibration) is

done.

2

1

config_done

unlock_s

R

0h

1 h = Configuration (CRC Check followed by transfer of EEPROM to

registers) is done.

R/WEX

Lock Detect Sticky Bit. This indicates the loss of lock of the PLL and

this is cleared only by recalibration or

RESETN/SYNC pin

a hard reset through

0h = locked

1h = unlocked

0

lock_det

R

0h

When the calibration is done frequency may or may not be locked.

1h = Frequency is locked. 0h = Otherwise

0h = unlocked

1h = locked

8.6.1.9 STATUS2 Register (Address = 8h) [reset = 0h]

STATUS2 is shown in Figure 39 and described in Table 25.

Return to Summary Table.

Figure 39. STATUS2 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

misc_status

R-0h

Table 25. STATUS2 Register Field Descriptions

BIT

15-0

FIELD

misc_status

TYPE

RESET

DESCRIPTION

R

0h

Miscellaneous status word.

8.6.1.10 STATUS3 Register (Address = 9h) [reset = 0h]

STATUS3 is shown in Figure 40 and described in Table 26.

Return to Summary Table.

Figure 40. STATUS3 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

nvmlcrc

R-0h

Table 26. STATUS3 Register Field Descriptions

BIT

15-0

FIELD

nvmlcrc

TYPE

RESET

DESCRIPTION

R

0h

The NVMLCRC register holds the Live CRC byte that has been

calculated while reading on-chip EEPROM.

8.6.1.11 EEPROM0 Register (Address = Ah) [reset = 0h]

EEPROM0 is shown in Figure 41 and described in Table 27.

Return to Summary Table.

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Figure 41. EEPROM0 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

nvmscrc

R-0h

Table 27. EEPROM0 Register Field Descriptions

BIT

15-0

FIELD

nvmscrc

TYPE

RESET

DESCRIPTION

R

0h

Stored CRC value. This value is used to compare with the computed

CRC and to update the CRC Status bit

8.6.1.12 EEPROM1 Register (Address = Bh) [reset = 0h]

EEPROM1 is shown in Figure 42 and described in Table 28.

Return to Summary Table.

Figure 42. EEPROM1 Register

15

7

14

6

13

5

12

4

11

10

2

9

1

8

0

RESERVED

R/W-0h

3

RESERVED

R/W-0h

nvm_rd_addr

R/W-0h

Table 28. EEPROM1 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-6

5-0

RESERVED

nvm_rd_addr

R/W

0h

Reserved.

R/W

0h

Writing an address into the NVM WR Address starts the read loop.

This register will contain the data read from the EEPROM at the

address provided by the NVM WR Address. The address is auto-

incremented and subsequent read from the NVM RD Data register

will give the data from the next EEPROM location.

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8.6.1.13 EEPROM2 Register (Address = Ch) [reset = 0h]

EEPROM2 is shown in Figure 43 and described in Table 29.

Return to Summary Table.

Figure 43. EEPROM2 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

nvm_rd_data

R-0h

Table 29. EEPROM2 Register Field Descriptions

BIT

15-0

FIELD

nvm_rd_data

TYPE

RESET

DESCRIPTION

R

0h

Reading from this register will return the data present at the

EEPROM from the immediate next address location than what was

programmed in the NVM RD Address register since writing into NVM

RD Address register already returned the data from EEPROM from

the written address. Subsequent read from this register will cause

the address to be auto-incremented and cause a read from the next

EEPROM location.

8.6.1.14 EEPROM3 Register (Address = Dh) [reset = 0h]

EEPROM3 is shown in Figure 44 and described in Table 30.

Return to Summary Table.

Figure 44. EEPROM3 Register

15

7

14

6

13

5

12

4

11

10

2

9

1

8

0

RESERVED

R/W-0h

3

RESERVED

R/W-0h

nvm_wr_addr

R/W-0h

Table 30. EEPROM3 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-6

5-0

RESERVED

R/W

0h

Reserved.

nvm_wr_addr

R/W

0h

Writing an address into the NVM WR Address starts the write loop.

But Writing a data into the NVM WR Data register will program the

EEPROM with that data at the address provided by writing into NVM

WR Address initially.

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8.6.1.15 EEPROM4 Register (Address = Eh) [reset = 0h]

EEPROM4 is shown in Figure 45 and described in Table 31.

Return to Summary Table.

Figure 45. EEPROM4 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

nvm_wr_data

R/W-0h

Table 31. EEPROM4 Register Field Descriptions

BIT

15-0

FIELD

nvm_wr_data

TYPE

RESET

DESCRIPTION

R/W

0h

Writing a data into this register will program the EEPROM with the

written data at the address given by NVM WR Address. Subsequent

write into this register will cause the address to be auto-incremented

and cause a program at the next EEPROM location.

8.6.1.16 STARTUP0 Register (Address = Fh) [reset = 37h]

STARTUP0 is shown in Figure 46 and described in Table 32.

Return to Summary Table.

Figure 46. STARTUP0 Register

15

14

13

12

4

11

10

9

8

ee_lock

R/W-0h

RESERVED

R/W-0h

zdm_auto

R/W-0h

7

6

5

3

2

1

0

bypass_cal

R/W-0h

bypass_config

R/W-0h

cal_mute

R/W-1h

shift_left

R/W-2h

gpio3_gf_en

R/W-1h

gpio2_gf_en

R/W-1h

acal_en

R/W-1h

Table 32. STARTUP0 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-12

ee_lock

R/W

0h

Locks EEPROM for regcommit and EEPROM write operations. To

unlock, write 5h, any other value to lock.

11-9

8

RESERVED

zdm_auto

R/W

0h

Reserved.

Setting this bit 1 will allow state machine to control the value of

pll_ndiv and pll_psfb internally in Normal/ZDM mode of calibration. If

set 0 the user has to manually program the pll_ndiv and pll_psfb

7

6

bypass_cal

R/W

0h

Bypass the calibration. By default two rounds of calibrations (AC

followed by FC) will be done. Setting this bit to 1 will bypass the

calibration.

bypass_config

Bypass the configuration. Note that on PoR this bit is zero and

hence configuration will happen. However after the first configuration

this bit can be set and apply the soft/pin reset so that configuration

will be bypassed.

5

cal_mute

R/W

1h

Mute the output during the calibration.

0h = Outputs stay active

1h = Outputs muted

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Table 32. STARTUP0 Register Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

4-3

shift_left

R/W

2h

Divide the ref clock (PFD clock) during calibration by 2 to the power

of value

0h = 1

1h = 2

2h = 4

3h = 8

2

1

0

gpio3_gf_en

gpio2_gf_en

acal_en

R/W

1h

Enable the glitch filter for SCL, GPIO3.

0h = Disabled

1h = Enabled

Enable the glitch filter for SDA, GPIO2.

0h = Disabled

1h = Enabled

Enable automatic frequency calibration at power-up or EEPROM re-

load.

0h = Disabled

1h = Enabled

8.6.1.17 STARTUP1 Register (Address = 10h) [reset = 921Fh]

STARTUP1 is shown in Figure 47 and described in Table 33.

Return to Summary Table.

Figure 47. STARTUP1 Register

15

7

14

13

12

4

11

3

10

9

8

0

pll_lock_dly

R/W-12h

ac_init_dly

R/W-10h

6

5

2

1

ac_init_dly

R/W-10h

cp_dly

R/W-1Fh

Table 33. STARTUP1 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-11

10-5

4-0

pll_lock_dly

ac_init_dly

cp_dly

R/W

12h

Wait time before lock detect goes high after the calibration. Expected

value is approximately 1 ms. The actual delay will be 4 × T ×

{programmed value} where T = 200ns typically.

R/W

10h

1Fh

Peak detector settlig time, that is, pll_en_peakdet_vco going high to

first cross code change. Expected value is 1.6 µs. The actual delay

will be 4 × T × {programmed value} where T = 200ns typically.

Delay from vtune driver enable (pll_en_vtune_drv) going high to

peak detector enable (pll_en_peakdet_vco) going high. Expected

delay is 200 µs. The actual delay will be 64 × T × {programmed

value} where T = 200ns typically.

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8.6.1.18 STARTUP2 Register (Address = 11h) [reset = 6C4h]

STARTUP2 is shown in Figure 48 and described in Table 34.

Return to Summary Table.

Figure 48. STARTUP2 Register

15

14

6

13

5

12

4

11

3

10

2

9

8

0

RESERVED

R/W-0h

switch_dly

R/W-0h

err_cnt

R/W-6h

7

1

fc_setl_dly

ac_cmp_dly

R/W-4h

R/W-3h

Table 34. STARTUP2 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15

RESERVED

switch_dly

R/W

0h

Reserved.

14-11

10-8

R/W

0h

6h

Indicates number of digital clocks to wait before SSM clock is turned

off after all the active signals are low. Internally scaled up by 2⁶.

Digital clock period is 200ns typically.

err_cnt

Indicates how long to wait for before declaring lock detect. In PFD

clocks period.

0h = 32

1h = 64

2h = 128

3h = 256

7-6

5-0

fc_setl_dly

R/W

3h

4h

Delay between two cap codes in terms of REFCLK period. Expected

value is 1 µs. The actual delay will be 32 × T × {programmed value}

where T is the refclk period.

ac_cmp_dly

Delay between successive cross code change. Expected value is 1

µs. The actual delay will be 4 × T × {programmed value} where T =

200ns typically.

8.6.1.19 REV0 Register (Address = 18h) [reset = 601h]

REV0 is shown in Figure 49 and described in Table 35.

Return to Summary Table.

Figure 49. REV0 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-6h

4

3

rev_reg

R-1h

Table 35. REV0 Register Field Descriptions

BIT

FIELD

TYPE

RESET

06h

DESCRIPTION

15-8

7-0

Reserved

rev_reg

R

Reserved

1h

Revision ID register.

1h = CDCI6214

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8.6.1.20 INPUT0 Register (Address = 1Ah) [reset = B14h]

INPUT0 is shown in Figure 50 and described in Table 36.

Return to Summary Table.

Figure 50. INPUT0 Register

15

14

13

12

4

11

10

9

1

8

0

ref_inbuf_ctrl

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

ip_xo_cload

R/W-Bh

7

6

5

3

2

RESERVED

ip_xo_gm

R/W-5h

xin_inbuf_ctrl

R/W-0h

Table 36. INPUT0 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15

ref_inbuf_ctrl

R/W

0h

Reference input buffer select.

0h = LVCMOS

1h = AC-Differential

RESERVED

14

13

RESERVED

R/W

0h

RESERVED

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Table 36. INPUT0 Register Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

12-8

ip_xo_cload

R/W

Bh

Selects load cap for XO (up to 9 pF) in 5 bit binary selection). Step

size is about 200 fF.

0h = 3.0 pF

1h = 3.2 pF

2h = 3.4 pF

3h = 3.6 pF

4h = 3.8 pF

5h = 4.0 pF

6h = 4.2 pF

7h = 4.4 pF

8h = 4.6 pF

9h = 4.8 pF

Ah = 5.0 pF

Bh = 5.2 pF

Ch = 5.4 pF

Dh = 5.6 pF

Eh = 5.8 pF

Fh = 6.0 pF

10h = 6.2 pF

11h = 6.4 pF

12h = 6.5 pF

13h = 6.7 pF

14h = 6.9 pF

15h = 7.1 pF

16h = 7.3 pF

17h = 7.5 pF

18h = 7.7 pF

19h = 7.9 pF

1Ah = 8.1 pF

1Bh = 8.3 pF

1Ch = 8.5 pF

1Dh = 8.7 pF

1Eh = 8.9 pF

1Fh = 9.0 pF

RESERVED

7-6

RESERVED

R/W

0h

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Table 36. INPUT0 Register Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

5-2

ip_xo_gm

R/W

5h

Tune bias current for XO. Gm programmability. Typical values:

0h = Disabled

1h = 14 µA

2h = 29 µA

3h = 44 µA

4h = 59 µA

5h = 148 µA

6h = 295 µA

7h = 443 µA

8h = 591 µA

9h = 884 µA

Ah = 1177 µA

Bh = 1468 µA

Ch = 1758 µA

1-0

xin_inbuf_ctrl

R/W

0h

Input buffer select.

0h = XO

1h = CMOS

2h = DIFF

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8.6.1.21 INPUT1 Register (Address = 1Bh) [reset = 0h]

INPUT1 is shown in Figure 51 and described in Table 37.

Return to Summary Table.

Figure 51. INPUT1 Register

15

14

13

12

11

10

9

8

RESERVED

R/W-0h

ip_byp_en_ch4 ip_byp_en_ch3 ip_byp_en_ch2 ip_byp_en_ch1 ip_byp_en_y0

ip_byp_mux

R/W-0h

ip_rst_rdiv

R/W-0h

6

R/W-0h

5

R/W-0h

4

R/W-0h

3

R/W-0h

2

7

1

0

ip_rdiv

R/W-0h

Table 37. INPUT1 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15

RESERVED

R/W

0h

RESERVED

14

13

12

11

ip_byp_en_ch4

R/W

0h

Bypass path buffer enable for CH4. This is required to drive a

bypass signal using ch4_iod_mux.

0h = disabled

1h = enabled

ip_byp_en_ch3

ip_byp_en_ch2

ip_byp_en_ch1

Bypass path buffer enable for CH3. This is required to drive a

bypass signal using ch3_iod_mux.

0h = disabled

1h = enabled

Bypass path buffer enable for CH2. This is required to drive a

bypass signal using ch2_iod_mux.

0h = disabled

1h = enabled

Bypass path buffer enable for CH1. This is required to drive a

bypass signal using ch1_iod_mux.

0h = disabled

1h = enabled

10

9

ip_byp_en_y0

ip_byp_mux

R/W

0h

Enable input clock to come out on Y0 buffer.

Selects Y0 clock between "REF_CLK" and "PFD_CLK".

0h = REF

1h = PFD

8

ip_rst_rdiv

ip_rdiv

R/W

0h

Resets flops in ref divider. Active (high) during power on reset or

SWRST or pin reset and inactive afterwards.

7-0

Reference clock divider. 0 = Doubler ON, 1 = /1, 2 = /2. and so forth.

0h = x2

1h = /1

2h = /2

3h = /3

4h = /4

5h = /5

...

FFh = /255

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8.6.1.22 INPUT_DBG0 Register (Address = 1Ch) [reset = 0h]

INPUT_DBG0 is shown in and described in Table 38.

Return to Summary Table.

Figure 52. INPUT_DBG0 Register

15

7

14

6

13

12

11

10

9

8

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

5

4

3

2

1

0

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

Table 38. INPUT_DBG0 Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED.

RESERVED

15-6

RESERVED

R/W

0h

5

4

3

2

1

0

R/W

0h

8.6.1.23 PLL0 Register (Address = 1Dh) [reset = Ch]

PLL0 is shown in Figure 53 and described in Table 39.

Return to Summary Table.

Figure 53. PLL0 Register

15

7

14

6

13

5

12

4

11

10

2

9

1

8

0

pll_psfb

R/W-0h

pll_ndiv

R/W-Ch

3

pll_ndiv

R/W-Ch

Table 39. PLL0 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-14

pll_psfb

R/W

0h

Programming bits for PLL feedback pre-scaler.

0h = /4

1h = /5

2h = /6

13-0

pll_ndiv

R/W

Ch

Feedback divider, must be at least 6h.

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8.6.1.24 PLL1 Register (Address = 1Eh) [reset = 5140h]

PLL1 is shown in Figure 54 and described in Table 40.

Return to Summary Table.

Figure 54. PLL1 Register

15

7

14

6

13

5

12

4

11

10

2

9

1

8

pll_cp_up

R/W-14h

pll_cp_dn

R/W-14h

3

0

pll_cp_dn

R/W-14h

pll_psb

R/W-0h

pll_psa

R/W-0h

Table 40. PLL1 Register Field Descriptions

BIT

15-10

FIELD

TYPE

RESET

DESCRIPTION

pll_cp_up

R/W

14h

Programming bits for up current of CP.

0h = 0.0 mA

1h = 0.1 mA

2h = 0.2 mA

3h = 0.3 mA

[...]

1Fh = 3.1 mA

37h = 3.2 mA

38h = 3.3 mA

[...]

3Dh = 3.8 mA

3Eh = 3.9 mA

3Fh = 4.0 mA

9-4

pll_cp_dn

R/W

14h

Programming bits for down current of CP.

0h = 0.0 mA

1h = 0.1 mA

2h = 0.2 mA

3h = 0.3 mA

[...]

1Fh = 3.1 mA

37h = 3.2 mA

38h = 3.3 mA

[...]

3Dh = 3.8 mA

3Eh = 3.9 mA

3Fh = 4.0 mA

3-2

1-0

pll_psb

pll_psa

R/W

0h

Programming bits for pre-scaler B.

0h = /4

1h = /5

2h = /6

Programming bits for pre-scaler A.

0h = /4

1h = /5

2h = /6

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8.6.1.25 PLL2 Register (Address = 1Fh) [reset = 1E72h]

PLL2 is shown in Figure 55 and described in Table 41.

Return to Summary Table.

Figure 55. PLL2 Register

15

7

14

13

5

12

4

11

10

9

1

8

RESERVED

R/W-0h

pll_lf_zcap

R/W-Fh

pll_lf_res

R/W-3h

6

3

2

0

pll_lf_res

R/W-3h

pll_lf_pcap

R/W-12h

Table 41. PLL2 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-14

13-9

RESERVED

pll_lf_zcap

R/W

0h

RESERVED.

R/W

Fh

Programming bits of cap value of zero of loop-filter.

0h = 000 pF

1h = 030 pF

2h = 060 pF

3h = 090 pF

4h = 120 pF

5h = 150 pF

6h = 180 pF

7h = 210 pF

8h = 240 pF

9h = 270 pF

Ah = 300 pF

Bh = 330 pF

Ch = 360 pF

Dh = 390 pF

Eh = 420 pF

Fh = 450 pF

10h = 480 pF

11h = 510 pF

12h = 540 pF

13h = 570 pF

14h = 600 pF

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Table 41. PLL2 Register Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

8-5

pll_lf_res

R/W

3h

Programming bits of res value of zero of loop-filter.

0h = open kΩ

1h = 00.5 kΩ

2h = 01.5 kΩ

3h = 02.5 kΩ

4h = 03.5 kΩ

5h = 04.5 kΩ

6h = 05.5 kΩ

7h = 06.5 kΩ

8h = 07.5 kΩ

9h = 08.5 kΩ

Ah = 09.5 kΩ

Bh = 10.5 kΩ

Ch = 11.5 kΩ

4-0

pll_lf_pcap

R/W

12h

Programming bits of cap value of pole of loop-filter.

0h = 00.0 pF

1h = 00.5 pF

2h = 01.5 pF

3h = 02.5 pF

4h = 03.5 pF

5h = 04.5 pF

6h = 05.5 pF

7h = 06.5 pF

8h = 07.5 pF

9h = 08.5 pF

Ah = 09.5 pF

Bh = 10.5 pF

Ch = 11.5 pF

Dh = 12.5 pF

Eh = 13.5 pF

Fh = 14.5 pF

10h = 15.5 pF

11h = 16.5 pF

12h = 17.5 pF

13h = 18.5 pF

14h = 19.5 pF

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8.6.1.26 PLL4 Register (Address = 21h) [reset = 7h]

PLL4 is shown in Figure 56 and described in Table 42.

Return to Summary Table.

Figure 56. PLL4 Register

15

14

6

13

12

4

11

10

9

1

8

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

7

5

3

2

0

RESERVED

R/W-0h

pll_pfd_dly_ctrl

R/W-0h

pll_lockdet_window

R/W-1h

pll_lockdet_wait

R/W-3h

Table 42. PLL4 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-7

RESERVED

R/W

0h

Reserved.

6-5

pll_pfd_dly_ctrl

R/W

0h

Programming of PFD reset delay. In PFD period.

0h = 2

1h = 6

2h = 10

3h = 14

4-2

pll_lockdet_window

R/W

1h

Programmability of PFD input and output time window for lock

detect.

0h = disabled

1h = typical 1.4 ns

2h = typical 2.6 ns

3h = typical 3.9 ns

4h = typical 5.2 ns

5h = typical 6.4 ns

6h = typical 7.6 ns

7h = typical 8.9 ns

1-0

pll_lockdet_wait

R/W

3h

Programmability of analog lock detect timer. In PFD cycles

0h = 1

1h = 16

2h = 64

3h = 128

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8.6.1.27 CH1_CTRL0 Register (Address = 23h) [reset = 8000h]

CH1_CTRL0 is shown in Figure 57 and described in Table 43.

Return to Summary Table.

Figure 57. CH1_CTRL0 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R/WEX-8000h

Table 43. CH1_CTRL0 Register Field Descriptions

BIT

15-0

FIELD

RESERVED

TYPE

RESET

DESCRIPTION

R/WEX

8000h

RESERVED

8.6.1.28 CH1_CTRL1 Register (Address = 24h) [reset = 0h]

CH1_CTRL1 is shown in Figure 58 and described in Table 44.

Return to Summary Table.

Figure 58. CH1_CTRL1 Register

15

7

14

6

13

5

12

11

3

10

2

9

1

8

RESERVED

R/W-0h

RESERVED

R/WEX-0h

4

0

RESERVED

R/WEX-0h

Table 44. CH1_CTRL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED.

15-9

8-0

RESERVED

R/W

0h

R/WEX

0h

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8.6.1.29 CH1_CTRL2 Register (Address = 25h) [reset = 8003h]

CH1_CTRL2 is shown in Figure 59 and described in Table 45.

Return to Summary Table.

Figure 59. CH1_CTRL2 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

ch1_iod_mux

R/W-2h

ch1_iod_div

R/WEX-3h

ch1_iod_div

R/WEX-3h

Table 45. CH1_CTRL2 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-14

ch1_iod_mux

R/W

2h

Input Clock selection for IOD.

0h = PSA

1h = PSB

3h = REF

13-0

ch1_iod_div

R/WEX

3h

IOD Division Value. 0h = Powers Down, Output=Input/IOD_DIV

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8.6.1.30 CH1_CTRL3 Register (Address = 26h) [reset = 9h]

CH1_CTRL3 is shown in Figure 60 and described in Table 46.

Return to Summary Table.

Figure 60. CH1_CTRL3 Register

15

14

6

13

12

4

11

10

9

8

ch1_sync_delay

R/W-0h

ch1_sync_en

R/W-0h

RESERVED

R/W-0h

ch1_mute_sel

R/W-0h

7

5

3

2

1

0

ch1_mute

R/W-0h

ch1_cmos_pol

R/W-0h

ch1_outbuf_ctrl

R/W-2h

ch1_mux

R/W-1h

Table 46. CH1_CTRL3 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-11

ch1_sync_delay

R/W

0h

Sync Delay cycles of IOD Input Clock. One cycle is a period of the

selected pre-scaler clock.

10

ch1_sync_en

R/W

0h

Enables SYNC for the channel.

0h = Disabled

1h = Enabled

9

8

RESERVED

R/W

0h

Reserved.

ch1_mute_sel

Mute selection for Output Channel.

0h = P=L N=H

1h = P=H N=L

7

ch1_mute

R/W

0h

2h

To mute the output on this channel.

0h = Un-mutes the output. 1h = mutes the output.

4-2

ch1_outbuf_ctrl

Select the output buffer format.

0h = disabled

(1)

1h = LVDS

2h = HCSL

3h = CML

4h = LVPECL

1-0

ch1_mux

R/W

1h

Output Clock Selection.

1h = CH1

2h = CH2

(1) For DC-connection program chx_lvds_cmtrim_inc = 2 and ch[4:1]_1p8vdet in Table 67 and Table 66 accordingly.

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8.6.1.31 CH1_CTRL4 Register (Address = 27h) [reset = 679h]

CH1_CTRL4 is shown in Figure 61 and described in Table 47.

Return to Summary Table.

Figure 61. CH1_CTRL4 Register

15

14

13

12

11

10

9

8

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-3h

RESERVED

R/W-0h

7

6

5

4

3

2

1

0

RESERVED

R/W-3h

RESERVED

ch1_glitchless_

en

R/W-1h

R/W-0h

R/W-1h

Table 47. CH1_CTRL4 Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED

15-12

RESERVED

R/W

0h

11-9

8

RESERVED

ch1_glitchless_en

R/W

3h

0h

1h

3h

1h

0h

1h

7-6

5-4

3

2

1

0

Enables Glitchless switching for Output Channel.

0h = Immediate

1h = Glitchless

8.6.1.32 CH1_CTRL5 Register (Address = 28h) [reset = 8h]

CH1_CTRL5 is shown in Figure 62 and described in Table 48.

Return to Summary Table.

Figure 62. CH1_CTRL5 Register

15

7

14

6

13

5

12

4

11

10

9

8

RESERVED

R/W-0h

3

2

1

0

RESERVED

R/W-0h

ch1_1p8vdet

R/W-1h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

Table 48. CH1_CTRL5 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-4

3

RESERVED

ch1_1p8vdet

R/W

0h

RESERVED.

R/W

1h

0h

Specify supply on the channel.

0h = 2.5 V or 3.3 V

1h = 1.8 V

2-0

RESERVED

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8.6.1.33 CH2_CTRL0 Register (Address = 29h) [reset = 8000h]

CH2_CTRL0 is shown in Figure 63 and described in Table 49.

Return to Summary Table.

Figure 63. CH2_CTRL0 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R/WEX-8000h

Table 49. CH2_CTRL0 Register Field Descriptions

Bit

15-0

Field

RESERVED

Type

Reset

Description

R/WEX

8000h

RESERVED

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8.6.1.34 CH2_CTRL1 Register (Address = 2Ah) [reset = 0h]

CH2_CTRL1 is shown in Figure 64 and described in Table 50.

Return to Summary Table.

Figure 64. CH2_CTRL1 Register

15

7

14

6

13

5

12

11

3

10

2

9

1

8

RESERVED

R/W-0h

RESERVED

R/WEX-0h

4

0

RESERVED

R/WEX-0h

Table 50. CH2_CTRL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED.

15-9

8-0

RESERVED

R/W

0h

R/WEX

0h

8.6.1.35 CH2_CTRL2 Register (Address = 2Bh) [reset = 0h]

CH2_CTRL2 is shown in Figure 65 and described in Table 51.

Return to Summary Table.

Figure 65. CH2_CTRL2 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

ch2_iod_mux

R/W-0h

ch2_iod_div

R/WEX-0h

ch2_iod_div

R/WEX-0h

Table 51. CH2_CTRL2 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-14

ch2_iod_mux

R/W

0h

Input Clock selection for IOD.

0h = PSA

1h = PSB

3h = REF

13-0

ch2_iod_div

R/WEX

0h

IOD Division Value. 0h = Powers Down, Output = Input/IOD_DIV

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8.6.1.36 CH2_CTRL3 Register (Address = 2Ch) [reset = 8h]

CH2_CTRL3 is shown in Figure 66 and described in Table 52.

Return to Summary Table.

Figure 66. CH2_CTRL3 Register

15

14

6

13

12

4

11

10

9

8

ch2_sync_delay

R/W-0h

ch2_sync_en

R/W-0h

RESERVED

R/W-0h

ch2_mute_sel

R/W-0h

7

5

3

2

1

0

ch2_mute

R/W-0h

ch2_cmos_pol

R/W-0h

ch2_outbuf_ctrl

R/W-2h

ch2_mux

R/W-0h

Table 52. CH2_CTRL3 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-11

ch2_sync_delay

R/W

0h

Sync Delay cycles of IOD Input Clock. One cycle is a period of the

selected pre-scaler clock.

10

ch2_sync_en

R/W

0h

Enables SYNC for the channel.

0h = Disabled

1h = Enabled

9

8

RESERVED

R/W

0h

RESERVED.

ch2_mute_sel

Mute selection for Output Channel.

0h = P=L N=H

1h = P=H N=L

7

ch2_mute

R/W

0h

To mute the output on this channel.

0h = Un-mutes the output. 1h = mutes the output.

6-5

ch2_cmos_pol

programmability of output CMOS buffer polarity.

0h = P+ N+

1h = P+ N–

2h = P– N+

3h = P– N–

4-2

ch2_outbuf_ctrl

R/W

2h

Select the output buffer format.

0h = disabled

1h = LVDS⁽¹⁾

2h = HCSL

3h = CML

4h = LVPECL

5h = CMOSPN

6h = CMOSP

7h = CMOSN

1-0

ch2_mux

R/W

0h

Output Clock Selection.

0h = CH1

1h = CH2

2h = CH3

(1) For DC-connection program chx_lvds_cmtrim_inc = 2 and ch[4:1]_1p8vdet in Table 67 and Table 66 accordingly.

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8.6.1.37 CH2_CTRL4 Register (Address = 2Dh) [reset = 71h]

CH2_CTRL4 is shown in Figure 67 and described in Table 53.

Return to Summary Table.

Figure 67. CH2_CTRL4 Register

15

14

13

12

11

10

9

8

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

7

6

5

4

3

2

1

0

RESERVED

R/W-3h

RESERVED

ch2_glitchless_

en

R/W-1h

R/W-0h

R/W-1h

Table 53. CH2_CTRL4 Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED

15-12

RESERVED

R/W

0h

11-8

7-6

5-4

3-1

0

RESERVED

ch2_glitchless_en

R/W

0h

1h

3h

0h

1h

Enables Glitchless switching for Output Channel.

0h = Immediate

1h = Glitchless

8.6.1.38 CH2_CTRL5 Register (Address = 2Eh) [reset = 8h]

CH2_CTRL5 is shown in Figure 68 and described in Table 54.

Return to Summary Table.

Figure 68. CH2_CTRL5 Register

15

7

14

6

13

5

12

4

11

10

9

8

RESERVED

R/W-0h

3

2

1

0

RESERVED

R/W-0h

ch2_1p8vdet

R/W-1h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

Table 54. CH2_CTRL5 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-4

3

RESERVED

ch2_1p8vdet

R/W

0h

RESERVED.

R/W

1h

0h

Specify supply on the channel.

0h = 2.5 V or 3.3 V

1h = 1.8 V

2-0

RESERVED

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8.6.1.39 CH3_CTRL0 Register (Address = 2Fh) [reset = 8000h]

CH3_CTRL0 is shown in Figure 69 and described in Table 55.

Return to Summary Table.

Figure 69. CH3_CTRL0 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R/WEX-8000h

Table 55. CH3_CTRL0 Register Field Descriptions

BIT

15-0

FIELD

RESERVED

TYPE

RESET

DESCRIPTION

R/WEX

8000h

RESERVED

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8.6.1.40 CH3_CTRL1 Register (Address = 30h) [reset = 0h]

CH3_CTRL1 is shown in Figure 70 and described in Table 56.

Return to Summary Table.

Figure 70. CH3_CTRL1 Register

15

7

14

6

13

5

12

11

3

10

2

9

1

8

RESERVED

R/W-0h

RESERVED

R/WEX-0h

4

0

RESERVED

R/WEX-0h

Table 56. CH3_CTRL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED.

RESERVED

15-9

8-0

RESERVED

R/W

0h

R/WEX

0h

8.6.1.41 CH3_CTRL2 Register (Address = 31h) [reset = 0h]

CH3_CTRL2 is shown in Figure 71 and described in Table 57.

Return to Summary Table.

Figure 71. CH3_CTRL2 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

ch3_iod_mux

R/W-0h

ch3_iod_div

R/WEX-0h

ch3_iod_div

R/WEX-0h

Table 57. CH3_CTRL2 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-14

ch3_iod_mux

R/W

0h

Input Clock selection for IOD.

0h = PSA

1h = PSB

3h = REF

13-0

ch3_iod_div

R/WEX

0h

IOD Division Value. 0h = Powers Down, Output=Input/IOD_DIV

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8.6.1.42 CH3_CTRL3 Register (Address = 32h) [reset = 4h]

CH3_CTRL3 is shown in Figure 72 and described in Table 58.

Return to Summary Table.

Figure 72. CH3_CTRL3 Register

15

14

6

13

12

4

11

10

9

8

ch3_sync_delay

R/W-0h

ch3_sync_en

R/W-0h

RESERVED

R/W-0h

ch3_mute_sel

R/W-0h

7

5

3

2

1

0

ch3_mute

R/W-0h

ch3_cmos_pol

R/W-0h

ch3_outbuf_ctrl

R/W-1h

ch3_mux

R/W-0h

Table 58. CH3_CTRL3 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-11

ch3_sync_delay

R/W

0h

Sync Delay cycles of IOD Input Clock. One cycle is a period of the

selected pre-scaler clock.

10

ch3_sync_en

R/W

0h

Enables SYNC for the channel.

0h = Disabled

1h = Enabled

9

8

RESERVED

R/W

0h

RESERVED.

ch3_mute_sel

Mute selection for Output Channel.

0h = P=L N=H

1h = P=H N=L

7

ch3_mute

R/W

0h

To mute the output on this channel.

0h = Un-mutes the output. 1h = mutes the output.

6-5

ch3_cmos_pol

programmability of output CMOS buffer polarity.

0h = P+ N+

1h = P+ N–

2h = P– N+

3h = P– N–

4-2

ch3_outbuf_ctrl

R/W

1h

Select the output buffer format.

0h = disabled

1h = LVDS⁽¹⁾

2h = HCSL

3h = CML

4h = LVPECL

5h = CMOSPN

6h = CMOSP

7h = CMOSN

1-0

ch3_mux

R/W

0h

Output Clock Selection.

0h = CH2

1h = CH3

2h = CH4

(1) For DC-connection program chx_lvds_cmtrim_inc = 2 and ch[4:1]_1p8vdet in Table 67 and Table 66 accordingly.

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8.6.1.43 CH3_CTRL4 Register (Address = 33h) [reset = 671h]

CH3_CTRL4 is shown in Figure 73 and described in Table 59.

Return to Summary Table.

Figure 73. CH3_CTRL4 Register

15

14

13

12

11

10

9

8

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-3h

RESERVED

R/W-0h

7

6

5

4

3

2

1

0

RESERVED

R/W-3h

RESERVED

ch3_glitchless_

en

R/W-1h

R/W-0h

R/W-1h

Table 59. CH3_CTRL4 Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED

15-12

RESERVED

R/W

0h

11-9

8

RESERVED

ch3_glitchless_en

R/W

3h

0h

1h

3h

0h

1h

7-6

5-4

3-1

0

Enables Glitchless switching for Output Channel.

0h = Immediate

1h = Glitchless

8.6.1.44 CH3_CTRL5 Register (Address = 34h) [reset = 8h]

CH3_CTRL5 is shown in Figure 74 and described in Table 60.

Return to Summary Table.

Figure 74. CH3_CTRL5 Register

15

7

14

6

13

5

12

4

11

10

9

8

RESERVED

R/W-0h

3

2

1

0

RESERVED

R/W-0h

ch3_1p8vdet

R/W-1h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

Table 60. CH3_CTRL5 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-4

3

RESERVED

ch3_1p8vdet

R/W

0h

RESERVED.

R/W

1h

0h

Specify supply on the channel.

0h = 2.5 V or 3.3 V

1h = 1.8 V

2-0

RESERVED

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8.6.1.45 CH4_CTRL0 Register (Address = 35h) [reset = 8000h]

CH4_CTRL0 is shown in Figure 75 and described in Table 61.

Return to Summary Table.

Figure 75. CH4_CTRL0 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R/WEX-8000h

Table 61. CH4_CTRL0 Register Field Descriptions

Bit

15-0

Field

RESERVED

Type

Reset

Description

R/WEX

8000h

RESERVED

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8.6.1.46 CH4_CTRL1 Register (Address = 36h) [reset = 0h]

CH4_CTRL1 is shown in and described in .

Return to Summary Table.

Figure 76. CH4_CTRL1 Register

15

7

14

6

13

5

12

11

3

10

2

9

1

8

RESERVED

R/W-0h

RESERVED

R/WEX-0h

4

0

RESERVED

R/WEX-0h

Table 62. CH4_CTRL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED.

RESERVED

15-9

8-0

RESERVED

R/W

0h

R/WEX

0h

8.6.1.47 CH4_CTRL2 Register (Address = 37h) [reset = 0h]

CH4_CTRL2 is shown in Figure 77 and described in Table 63.

Return to Summary Table.

Figure 77. CH4_CTRL2 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

ch4_iod_mux

R/W-0h

ch4_iod_div

R/WEX-0h

ch4_iod_div

R/WEX-0h

Table 63. CH4_CTRL2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-14

ch4_iod_mux

R/W

0h

Input Clock selection for IOD.

0h = PSA

1h = PSB

3h = REF

13-0

ch4_iod_div

R/WEX

0h

IOD Division Value. 0h = Powers Down, Output=Input/IOD_DIV.

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8.6.1.48 CH4_CTRL3 Register (Address = 38h) [reset = 4h]

CH4_CTRL3 is shown in Figure 78 and described in Table 64.

Return to Summary Table.

Figure 78. CH4_CTRL3 Register

15

14

6

13

12

4

11

10

9

8

ch4_sync_delay

R/W-0h

ch4_sync_en

R/W-0h

RESERVED

R/W-0h

ch4_mute_sel

R/W-0h

7

5

3

2

1

0

ch4_mute

R/W-0h

ch4_cmos_pol

R/W-0h

ch4_outbuf_ctrl

R/W-1h

ch4_mux

R/W-0h

Table 64. CH4_CTRL3 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-11

ch4_sync_delay

R/W

0h

Sync Delay cycles of IOD Input Clock. One cycle is a period of the

selected pre-scaler clock.

10

ch4_sync_en

R/W

0h

Enables SYNC for the channel.

0h = Disabled

1h = Enabled

9

8

RESERVED

R/W

0h

RESERVED.

ch4_mute_sel

Mute selection for Output Channel.

0h = P=L N=H

1h = P=H N=L

7

ch4_mute

R/W

0h

1h

To mute the output on this channel.

0h = Un-mutes the output. 1h = mutes the output.

4-2

ch4_outbuf_ctrl

Select the output buffer format.

0h = disabled

1h = LVDS⁽¹⁾

2h = HCSL

3h = CML

4h = LVPECL

1-0

ch4_mux

R/W

0h

Output Clock Selection. 0h = Previous Channel, 1h = Current

Channel, 2h = Next Channel, 3h = AGND

0h = CH3

1h = CH4

(1) For DC-connection program chx_lvds_cmtrim_inc = 2 and ch[4:1]_1p8vdet in Table 67 and Table 66 accordingly.

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8.6.1.49 CH4_CTRL4 Register (Address = 39h) [reset = 71h]

CH4_CTRL4 is shown in Figure 79 and described in Table 65.

Return to Summary Table.

Figure 79. CH4_CTRL4 Register

15

14

13

12

11

10

9

8

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

7

6

5

4

3

2

1

0

RESERVED

R/W-3h

RESERVED

ch4_glitchless_

en

R/W-1h

R/W-0h

R/W-1h

Table 65. CH4_CTRL4 Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED

15-12

RESERVED

R/W

0h

11-8

7-6

5-4

3-1

0

RESERVED

ch4_glitchless_en

R/W

0h

1h

3h

0h

1h

Enables Glitchless switching for Output Channel.

0h = Immediate

1h = Glitchless

8.6.1.50 CH4_CTRL5 Register (Address = 3Ah) [reset = 8h]

CH4_CTRL5 is shown in Figure 80 and described in Table 66.

Return to Summary Table.

Figure 80. CH4_CTRL5 Register

15

7

14

6

13

5

12

4

11

10

9

8

RESERVED

R/W-0h

3

2

1

0

RESERVED

R/W-0h

ch4_1p8vdet

R/W-1h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

Table 66. CH4_CTRL5 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-4

3

RESERVED

ch4_1p8vdet

R/W

0h

RESERVED.

R/W

1h

0h

Specify supply on the channel.

0h = 2.5 V or 3.3 V

1h = 1.8 V

2-0

RESERVED

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8.6.1.51 CHX_CTRL0 Register (Address = 3Bh) [reset = 61h]

CHX_CTRL0 is shown in Figure 81 and described in Table 67.

Return to Summary Table.

Figure 81. CHX_CTRL0 Register

15

14

13

12

11

10

9

8

RESERVED

chx_rst

chx_lvds_cmtrim_inc

chx_lvds_cmtrim_dec

chx_diffbuf_ibia

s_trim

R/W-0h

7

R/W-0h

5

R/W-0h

R/W-3h

6

4

3

2

1

0

chx_diffbuf_ibias_trim

chx_lvcmos_dr

v

RESERVED

ch0_lvcmos_drv

R/W-0h

RESERVED

R/W-3h

R/W-1h

R/W-0h

R/W-1h

Table 67. CHX_CTRL0 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-14

RESERVED

R/W

0h

RESERVED

13

chx_rst

R/W

0h

All Channel RST during power up and later. 1h = RST, 0h = Normal.

12-11

chx_lvds_cmtrim_inc

Increments differential output buffer output common-mode

programmability.

Use

either

CHX_LVDS_CMTRIM_INC

or

CHX_LVDS_CMTRIM_DEC.

10-9

8-5

chx_lvds_cmtrim_dec

chx_diffbuf_ibias_trim

R/W

0h

3h

Decrements differential output buffer output common-mode

programmability. Increment

Use

either

CHX_LVDS_CMTRIM_INC

or

CHX_LVDS_CMTRIM_DEC.

Differential output buffer tail current programmability.

Ch = 350 µA

8h = 400 µA

4h = 450 µA

0h = 500 µA

1h = 550 µA

2h = 600 µA

3h = 650 µA

4

chx_lvcmos_drv

R/W

1h

Adjust CH1 to CH4 LVCMOS driver strength.

0h = Normal

1h = Fast

3

RESERVED

R/W

1h

0h

RESERVED

2-1

ch0_lvcmos_drv

Enable Y0 channel and adjust LVCMOS driver strength.

0h = Off

1h = Normal

3h = Fast

0

RESERVED

R/W

1h

RESERVED

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8.6.1.52 CHX_CTRL1 Register (Address = 3Ch) [reset = 18h]

CHX_CTRL1 is shown in Figure 82 and described in Table 68.

Return to Summary Table.

Figure 82. CHX_CTRL1 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R/W-18h

Table 68. CHX_CTRL1 Register Field Descriptions

BIT

15-0

FIELD

RESERVED

TYPE

RESET

DESCRIPTION

R/W

18h

RESERVED

8.6.1.53 CHX_CTRL2 Register (Address = 3Dh) [reset = 1500h]

CHX_CTRL2 is shown in Figure 83 and described in Table 69.

Return to Summary Table.

Figure 83. CHX_CTRL2 Register

15

14

13

12

11

3

10

9

1

8

0

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-15h

7

6

5

4

2

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

Table 69. CHX_CTRL2 Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED

15-13

RESERVED

R/W

0h

12-8

7-0

R/W

15h

0h

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8.6.1.54 CHX_CTRL3 Register (Address = 3Eh) [reset = 4210h]

CHX_CTRL3 is shown in and described in Table 70.

Return to Summary Table.

Figure 84. CHX_CTRL3 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R/W-4210h

Table 70. CHX_CTRL3 Register Field Descriptions

BIT

15-0

FIELD

RESERVED

TYPE

RESET

DESCRIPTION

R/W

4210h

RESERVED

8.6.1.55 CHX_CTRL4 Register (Address = 3Fh) [reset = 210h]

CHX_CTRL4 is shown in Figure 85 and described in Table 71.

Return to Summary Table.

Figure 85. CHX_CTRL4 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R/W-210h

Table 71. CHX_CTRL4 Register Field Descriptions

BIT

15-0

FIELD

RESERVED

TYPE

RESET

DESCRIPTION

R/W

210h

RESERVED

8.6.1.56 DBG0 Register (Address = 42h) [reset = 200h]

DBG0 is shown in and described in Table 72.

Return to Summary Table.

Figure 86. DBG0 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R/W-200h

Table 72. DBG0 Register Field Descriptions

BIT

15-0

FIELD

RESERVED

TYPE

RESET

DESCRIPTION

R/W

200h

RESERVED

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

An ultra-low power clock generator is ideal to drive clocks in industrial, portable and data center applications. The

device is flexible in its configuration and be pre-preprogramed with two separate configuration. For example a

production test and an application configuration, or two different configurations for two flavors of a product. The

internal EEPROM is protected by a CRC hash which is available as a status bit. The two EEPROM pages are

selected using a control pin. As each major block of the device is powered by its own supply pin, the device can

easily be used for signal translation and to accommodate various supply voltages which may be available in a

system. Up to five different frequencies can be generated from a single device and feed different parts of an

application. Each of the four differential outputs supports various signal standards. On one hand the general

purpose pin functionality allows to provide status information to other parts of the system, on the other hand it

adds modularity and flexibility to an application. Clock outputs can be muted individually or globally, the division

ratio updated, the output dividers synchronized and a spread spectrum function enabled or disabled. The clock

generator PLL can also be used in a zero delay mode which will compensate most of the seen phase delay

between an external reference clock and the output clocks. Together with an external feedback option this allows

to compensate traces on top of the digital delay steps provided inside the device. All these features make the

ultra-low power clock generator for design library integration and re-use in modular projects.

9.2 Typical Applications

1.8V

/ 2.5V

/ 3.3V

1.8V

/ 2.5V

/ 3.3V

1.8V

/ 2.5V

/ 3.3V

1.8V

/ 2.5V

/ 3.3V

VDDREF VDDVCO

XOUT/FB_P

VDDO12 VDDO34

Y0

Y1P

Y1N

Y2P

Y2N

Y3P

Y3N

Y4P

Y4N

100 nF

25 MHz

XIN/FB_N

100 nF

MCU_CLK_SYNC

RESETN/SYNC

U1

CDCI6214

100 nF

REFSEL

EEPROMSEL

100 nF

VDD_REF

PAD

100 nF

GND

OE/GPIO4

SCL/GPIO3

SDA/GPIO2 STATUS/GPIO1

MCU_CLK_OE

MCU_SCL

MCU_SDA

MCU_CLK_STATUS

Figure 87. Typical Serial Interface Application Schematic

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Typical Applications (continued)

VDD_CLK_3V3

GND

VDDREF

VDDVCO

VDDO12

VDDO34

XOUT/FB_P

Y0

Y1P

Y1N

Y2P

Y2N

Y3P

Y3N

Y4P

Y4N

25 MHz

U1

XIN/FB_N

REFP

FPGA_PCIe_HCSL_AP

FPGA_PCIe_HCSL_AN

OPT_MODULE_LVDS_AP

CDCI6214

REFP

REFN

100 nF

100 Ω

REFN

VDDREF

OPT_MODULE_LVDS_AN

OPT_MODULE_LVDS_BP

OPT_MODULE_LVDS_BN

FPGA_PCIe_HCSL_BP

FPGA_PCIe_HCSL_BN

50 kΩ

CLKGen_RSTN

RESETN

VDDREF

GND

4.7 kꢀ

50 kΩ

REFSEL

VDDREF

GND

4.7 kꢀ

50 kΩ

EEPROMSEL

VDD_CLK_3V3

VDDREF

50 kΩ

PAD

OE4

OE3

OE2

OE1

GND

CLKGen_PCIe_A

CLKGen_OPTMOD_A

CLKGen_OPTMOD_B

CLKGen_PCIe_B

Figure 88. Typical Individual Output Enable Application Schematic

9.2.1 Design Requirements

For this example, the design parameters are listed in Table 76

Table 76. Design Parameters

PARAMETER

t_VDD

EXAMPLE VALUE

Larger than 50 µs and smaller than 3 ms

t_{PWL_SYNC}

f_XIN

Larger than (1 / f_XIN

)

Crystal 8 MHz to 50 MHz

Input slew rate for external clock reference better

than 3 V / ns

dV_IN/dT

9.2.2 Detailed Design Procedure

For this application, TI recommends the following steps:

1. Decide how the device shall receive the register settings to plan for in-system programming of the EEPROM.

2. Choose which operation mode to use on the device (I²C or GPIOs) and which pins are inputs and which are

outputs (see registers GENERIC0, GENERIC1, and GENERIC2).

3. Consider that the serial interface and the GPIOs are supplied by VDDREF as well as the input pins (for

example, a 3.3-V crystal oscillator (XO) driving XIN forces uses 3.3-V I²C).

4. Keep track of which voltage levels the output supplies will have. There are configuration bits in the output

channels (see CH1_CTRL5, CH2_CTRL5, CH3_CTRL5, and CH4_CTRL5).

5. Consider which output frequency has the most stringent phase noise specifications. Select this frequency to

decide on the reference and VCO frequency.

6. Cross-check if your specific bandwidth requirement for an external reference can be achieved using the

internal loop filter components (see registers PLL1 and PLL2).

7. Optimize the clock distribution using output muxes to run the least amount of blocks to conserve power,

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8. For HCSL output buffer format, optimize the signal integrity and slew rate at the receiver input using a series

resistor between device pin and the 50 Ω termination to GND.Y1,Y4 provide higher slew rates compared to

Y2,Y3.

Use Equation 1 through Equation 4 to calculate the a basic frequency plan or use the provided software TICS

Pro to generate settings.

NOTE

The user has to ensure PLL stability is given by applying the adequate loop filter and

charge pump settings. A phase margin of ≥ 68º is recommended. The target bandwidth is

recommended between 600 kHz .. 1100 kHz.

f_Y0= f_XIN= f_REF

(1)

(2)

(3)

f_PFD= f_REF/ ip_ref_div

where

•

ip_ref_div ≥ 1

1 MHz <= f_PFD<= 100 MHz

f_VCO= f_PFD· pll_nc · (pll_ps + 4)

with

•

2400 <= f_VCO<= 2800

0 <= pll_ps <= 2

f_Y[4:1]= f_VCO/ ((pll_ps[ab] + 4) · ch[4:1]_iod_div)

with

•

0 <= pll_ps[ab] <= 2

1 <= ch[4:1]_iod_div <= 16383

44.1 kHz <= f_Y[4:1]<= 350 MHz

(4)

9.2.3 Application Curves

Reference 25 MHz

crystal with

HCSL output with

Integrated RMS

Jitter from 10 kHz

to 40 MHz 370 fs

at 3.3 V, room

PSA=4,

PSB=6

C1 = PSA/4, C2 =

PSA/4 and 30 PSA

cycles delayed

C3 = PSB/4, C4 =

PSB/4 and 30 PSA

cycles delayed

50 Ω onboard

termination to

balun into 5052A

Signal Source

Analyzer

Doubler to VCO

2.4 GHz

temperature

Figure 90. Divider Sync and Digital Delay

Figure 89. Typical Phase Noise Y1, HCSL, 3.3 V

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9.3 Do's and Don'ts

The maximum swing and level must match to the applied VDDREF (for example, for a 3.3-V XO as reference,

VDDREF must be 3.3 V).

VDDREF and VDDVCO must be powered from the same supply voltage.

9.4 Initialization Setup

The device digital logic starts after the internal power-on-release circuit triggered (POR). The digital core is

connected to the VDDREF domain. The EEPROM settings are loaded into the device registers and the new

settings applied to the device. The EEPROM page is selected according to the EEPROMSEL pin logic level. A

low level loads page 0, and a logic high level loads page 1. By default, the differential outputs are muted for the

initial VCO calibration and PLL lock process. After the PLL circuit achieved a phase lock to the input reference,

the output dividers are synchronized and then released to operation. By default, pin 8 is configured as RESETN

pin (see gpio0_dir_sel and gpio0_input_sel). The start of the initialization sequence, as well the as serial

interface, can be kept in reset using RESETN= LOW. When pin 8 is not configured as RESETN, the device

initialization relies on the POR triggered by application of VDDREF.

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Initialization Setup (continued)

Power-On-Reset

(POR)

Delay

Low

RESETN?

High

EEPROM

Base

Defaults

Configuration?

Operational

Mode

REFSEL = Low or High

Fall-Back

Mode

REFSEL = Middle

EEPROMSEL = Low or High

EEPROMSEL = Middle

Low

High

EEPROM

Page?

EEPROM

Page 0

EEPROM

Page 1

Control Pin

Configuration

Control Pin

Configuration

I²C or

Output Enables

I²C

Status

^/}v(]P 5}vꢀ_

PLL

Configuration

PLL

Configuration

Status

^/}v(]P 5}vꢀ_

VCO Cal.

Bypass

VCO

Calibration

Status

^/ꢁo]ꢂŒꢁš]}v 5}vꢀ_

PLL

Locked?

Status

^t[[ [}ꢃlꢀꢄ_

Yes

Syn-

chronization

Bypass

Synchronize

Clock

Distribution

Status

^{Çvꢃ 5}vꢀ_

Normal

Operation

Figure 91. Initialization Flow Chart

The pins 8, 11, 12, 19, and 20 are general-purpose inputs and outputs (GPIO). The functions are determined

through the register settings saved in the selected EEPROM page. See GENERIC0, GENERIC1, and

GENERIC2 for the relevant bit-fields.

The EEPROM allows to choose between two modes of operation: pin Mode and serial interface mode. This is

done using mode.

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10 Power Supply Recommendations

10.1 Power-Up Sequence

There are no restrictions from the device for applying power to the supply pins. From an application perspective,

TI recommends to either apply all VDDs at the same time or apply VDDREF first. The digital core is connected to

VDDREF, and thus the settings of the EEPROM are applied automatically. All VDDs should reach 95% of final

value within 2 ms. RESETN should be held low before VDDREF reaches 95% of the final value. TI recommends

adding a 4.7-kΩ pullup resistor on RESETN and a 470-nF capacitor to ground to provide additional delay in

release of RESETN at power-up.

10.2 De-Coupling

TI recommends isolating all power supplies using a ferrite bead and provide decoupling for each of the supplies.

TI also recommends optimizing the decoupling for the respective layout and consider the power supply

impedance and optimize for the individual frequency plan.

An example for a decoupling per supply pin: 1x 4.7 µF, 1x 470 nF, and 1x 100 nF.

11 Layout

11.1 Layout Guidelines

For this example, follow these guidelines:

•

Isolate inputs and outputs using a GND shield. Figure 92 routes all inputs and outputs as differential pairs.

Isolate outputs to adjacent outputs when generating multiple frequencies.

Isolate the crystal area, connect the GND pads of the crystal package and flood the adjacent area. Figure 93

shows a foot print which supports multiple crystal sizes.

•

Try to avoid impedance jumps in the fan-in and fan-out areas when possible.

Use five VIAs to connect the thermal pad to a solid GND plane. Full-through VIAs are prefered.

Place decoupling capacitors with small capacitance values very close to the supply pins. Try to place them

very close on the same layer or directly on the backside layer. Larger values can be placed more far away.

Figure 93 shows three de-coupling capacitors close to the device. Ferrite beads are recommended to isolate

the different frequency domains and the VDDVCO domain.

•

Preferably use multiple VIAs to connect wide supply traces to the respective power planes.

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11.2 Layout Examples

Figure 92. Layout Example, Top Layer

Figure 93. Layout Example, Bottom Layer

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Layout Examples (continued)

Land Pattern Example

2.45 mm

0.6 mm

0.2 mm

Figure 94. Layout Example, Land Pattern

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12 器件和文档支持

12.1 器件支持

12.1.1 开发支持

请联系您的 TI 代表了解更多信息。

12.1.2 器件命名规则

CDCI6214 – 62= 时钟发生器；1 = 1 个 PLL；4 = 4 路输出；I = 独立输出使能

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 社区资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

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PACKAGE OUTLINE

RGE0024B

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

B

A

0.5

0.3

PIN 1 INDEX AREA

4.1

3.9

0.3

0.2

DETAIL

OPTIONAL TERMINAL

TYPICAL

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 2.5

(0.2) TYP

2.45 0.1

7

12

EXPOSED

THERMAL PAD

SEE TERMINAL

DETAIL

6

13

2X

SYMM

25

2.5

18

1

0.3

24X

20X 0.5

0.2

19

24

0.1

C A B

SYMM

24X

PIN 1 ID

(OPTIONAL)

0.05

0.5

0.3

4219013/A 05/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

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EXAMPLE BOARD LAYOUT

RGE0024B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.45)

SYMM

24

19

24X (0.6)

1

18

24X (0.25)

(R0.05)

TYP

25

SYMM

(3.8)

20X (0.5)

13

6

(

0.2) TYP

VIA

7

12

(0.975) TYP

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4219013/A 05/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

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EXAMPLE STENCIL DESIGN

RGE0024B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.08)

(0.64) TYP

19

24

24X (0.6)

1

25

18

24X (0.25)

(R0.05) TYP

SYMM

(0.64)

TYP

(3.8)

20X (0.5)

6

13

METAL

TYP

7

12

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219013/A 05/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

98

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	CDCI6214RGER
厂家：	TEXAS INSTRUMENTS
描述：	支持 PCIe 第 4 代标准且带四个可编程输出和 EEPROM 的超低功耗时钟发生器 \| RGE \| 24 \| -40 to 85 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟 PC 外围集成电路晶体时钟发生器
文件：	总103页 (文件大小：1824K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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