CDCLVD1208RHDR [TI]

2:8 Low Additive Jitter LVDS Buffer; 2 ： 8的低附加抖动LVDS缓冲器


型号：	CDCLVD1208RHDR
厂家：	TEXAS INSTRUMENTS
描述：	2:8 Low Additive Jitter LVDS Buffer 2 ： 8的低附加抖动LVDS缓冲器
文件：	总21页 (文件大小：786K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CDCLVD1208

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SCAS899 –AUGUST 2010

2:8 Low Additive Jitter LVDS Buffer

Check for Samples: CDCLVD1208

FEATURES

DESCRIPTION

•

2:8 Differential Buffer

•

Low Additive Jitter: <300 fs RMS in

10 kHz to 20 MHz

The CDCLVD1208 clock buffer distributes one of two

selectable clock inputs (IN0, IN1) to 8 pairs of

differential LVDS clock outputs (OUT0, OUT7)

with minimum skew for clock distribution. The

CDCLVD1208 can accept two clock sources into an

input multiplexer. The inputs can either be LVDS,

LVPECL, or LVCMOS.

•

Low Output Skew of 45 ps (Max)

Universal Inputs Accept LVDS, LVPECL,

LVCMOS

•

Selectable Clock Inputs through Control Pin

8 LVDS Outputs, ANSI EIA/TIA-644A Standard

Compatible

The CDCLVD1208 is specifically designed for driving

50 Ω transmission lines. If the input is in single ended

mode, the appropriate bias voltage (V_{AC_REF}) should

be applied to the unused negative input pin.

•

Clock Frequency up to 800 MHz

2.375–2.625V Device Power Supply

The IN_SEL pin selects the input which is routed to

the outputs. If this pin is left open it disables the

outputs (static). The part supports a fail safe function.

It incorporates an input hysteresis, which prevents

random oscillation of the outputs in absence of an

input signal

LVDS Reference Voltage, V_{AC_REF}, Available for

Capacitive Coupled Inputs

•

Industrial Temperature Range –40°C to 85°C

Packaged in 5mm × 5mm 28-Pin QFN (RHD)

ESD Protection Exceeds 3 kV HBM, 1 kV CDM

The device operates in 2.5 V supply environment and

is characterized from –40°C to 85°C (ambient

temperature). The CDCLVD1208 is packaged in

small 28-pin, 5-mm × 5-mm QFN package.

APPLICATIONS

•

Telecommunications/Networking

Medical Imaging

Test and Measurement Equipment

Wireless Communications

General Purpose Clocking

125 MHz

PHY2

125 MHz

Oscillator

PHY2

PHY 7

CDCLVD1208

LVDS Buffer

IN_SEL

FPGA

Figure 1. Application Example

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CDCLVD1208

SCAS899 –AUGUST 2010

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

AC_REF0

Reference

Generator

AC_REF1

INP0

OUTP [0..7]

OUTN [0..7]

INN0

INP1

LVDS

INN1

200 kW

IN_SEL

GND

Figure 2. CDCLVD1208 Block Diagram

QFN PACKAGE

(TOP VIEW)

OUTP4

OUTN4

OUTP5

OUTN5

OUTP6

OUTN6

GND

5mm x5mm

28 pin QFN

OUTN0

OUTP0

V_{AC_REF0}

INN 0

INP 0

Thermal Pad

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SCAS899 –AUGUST 2010

PIN FUNCTIONS

NAME

NO.

8, 15, 28

1, 14

TYPE

Power

Ground

Input

DESCRIPTION

V_CC

2.5V supplies for the device

Device ground

GND

INP0, INN0

9, 10

Differential input pair or single ended input

Differential redundant input pair or single ended input

Differential LVDS output pair no. 0

Differential LVDS output pair no. 1

Differential LVDS output pair no. 2

Differential LVDS output pair no. 3

Differential LVDS output pair no. 4

Differential LVDS output pair no. 5

Differential LVDS output pair no. 6

Differential LVDS output pair no. 7

INP1, INN1

5, 6

Input

OUTP0, OUTN0

OUTP1, OUTN1

OUTP2, OUTN2

OUTP3, OUTN3

OUTP4, OUTN4

OUTP5, OUTN5

OUTP6, OUTN6

OUTP7, OUTN7

12, 13

16, 17

18, 19

20, 21

22, 23

24, 25

26, 27

2, 3

Output

Bias voltage output for capacitive coupled inputs. If used, it is recommended to

use a 0.1µF to GND on this pin.

V_{AC_REF0}

V_{AC_REF1}

Output

Bias voltage output for capacitive coupled inputs. If used, it is recommended to

use a 0.1µF to GND on this pin.

Output

Input with internal

IN_SEL

200kΩ pull-up and Input Selection – selects input port; (See Table 1)

pull-down

Thermal Pad

See thermal management recommendations

Table 1. Input Selection Table

IN_SEL

ACTIVE CLOCK INPUT

INP0, INN0

INP1, INN1

(1)

Open

None

(1) The input buffers are disabled and the outputs are static.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE

UNIT

Supply voltage range, V_CC

–0.3 to 2.8

Input voltage range, V_I

–0.2 to (V_CC+ 0.2)

Output voltage range, V_O

(2)

Driver short circuit current, I_OSD

Electrostatic discharge (Human Body Model, 1.5 kΩ, 100 pF)

See Note

>3000

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) The outputs can handle permanent short.

RECOMMENDED OPERATING CONDITIONS

MIN

2.375

–40

TYP

MAX

2.625

UNIT

Device supply voltage, V_CC

Ambient temperature, T_A

2.5

°C

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UNITS

THERMAL INFORMATION

CDCLVD1208

THERMAL METRIC⁽¹⁾

RHD (28 PINS)

q_JA

Junction-to-ambient thermal resistance

q_JC(top)

q_JB

Junction-to-case(top) thermal resistance

Junction-to-board thermal resistance

°C/W

y_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case(bottom) thermal resistance

0.4

y_JB

q_JC(bottom)

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

ELECTRICAL CHARACTERISTICS

At V_CC= 2.375V to 2.625V, T_A= –40°C to 85°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IN_SEL CONTROL INPUT CHARACTERISTICS

V_dI3

3 State

Open

0.5×V_CC

V_dIH

Input high voltage

Input low voltage

Input high current

Input low current

Input pull-up/ pull-down resistor

0.7×V_CC

V_dIL

0.2×V_CC

I_dIH

V_CC= 2.625V, V_IH= 2.625V

V_CC= 2.625V, V_IL= 0V

kΩ

I_dIL

-30

R_{pull(IN_SEL)}

200

2.5V LVCMOS (see Figure 7) INPUT CHARACTERISTICS

f_IN

Input frequency

200

1.5

MHz

External threshold voltage applied to

complementary input

V_th

Input threshold voltage

1.1

V_IH

V_IL

Input high voltage

Input low voltage

Input high current

Input low current

Input edge rate

V_th+ 0.1

V_CC

V_th– 0.1

I_IH

V_CC= 2.625 V, V_IH= 2.625 V

V_CC= 2.625 V, V_IL= 0 V

20%–80%

V/ns

I_IL

–10

ΔV/ΔT

C_IN

1.5

Input capacitance

2.5

DIFFERENTIAL INPUT CHARACTERISTICS

f_IN

Input frequency

Clock input

800

1.6

MHz

V_PP

V_{IN, DIFF}

Differential input voltage

peak-to-peak

V_ICM= 1.25 V

0.3

V_ICM

I_IH

Input common mode voltage range

Input high current

V_{IN, DIFF, PP}> 0.4 V

V_CC= 2.625 V, V_IH= 2.625 V

V_CC= 2.625, V_IL= 0 V

20%–80%

V_CC– 0.3

I_IL

Input low current

–10

ΔV/ΔT

C_IN

Input edge rate

0.75

V/ns

Input capacitance

2.5

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ELECTRICAL CHARACTERISTICS (continued)

At V_CC= 2.375V to 2.625V, T_A= –40°C to 85°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LVDS OUTPUT CHARACTERISTICS

|V_OD

Differential output voltage magnitude

250

–15

450

Change in differential output voltage

magnitude

ΔV_OD

V_{IN, DIFF, PP}= 0.3V, R_L= 100 Ω

Steady-state common mode output

voltage

V_OC(SS)

ΔV_OC(SS)

1.1

1.375

Steady-state common mode output

voltage

V_{IN, DIFF, PP}= 0.6V, R_L= 100 Ω

–15

V_ring

V_OS

I_OS

Output overshoot and undershoot

Output ac common mode

Short-circuit output current

Propagation delay

Percentage of output amplitude V_OD

V_{IN, DIFF, PP}= 0.6V, R_L= 100 Ω

V_OD= 0 V

10%

mV_PP

±24

2.5

600

t_PD

V_{IN, DIFF, PP}= 0.3 V

1.5

t_{SK, PP}

t_{SK, O}

Part-to-part Skew

Output skew

Pulse skew (with 50% duty cycle

input)

Crossing-point-to-crossing-point

distortion

t_SK,P

t_RJIT

–50

Random additive jitter (with 50% duty Edge speed 0.75 V/ns,

cycle input)

0.3 ps, RMS

10 kHz – 20 MHz

t_R/t_F

Output rise/fall time

Static supply current

Supply current

20% to 80%, 100 Ω, 5 pF

300

I_CCSTAT

I_CC100

I_CC800

Outputs unterminated, f = 0 Hz

All outputs, R_L= 100 Ω, f = 100 MHz

All outputs, R_L= 100 Ω, f = 800 MHz

Supply current

111

V_{AC_REF}CHARACTERISTICS

V_{AC_REF}

Reference output voltage

V_CC= 2.5 V I_load= 100 µA

1.1

1.25

1.35

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Typical Additive Phase Noise Characteristics for 100 MHz Clock

PARAMETER

MIN

TYP

-132.9

-138.8

-147.4

-153.6

-155.2

-156.2

-156.6

171

MAX

UNIT

dBc/Hz

fs, RMS

phn₁₀₀

phn_1k

Phase noise at 100 Hz offset

Phase noise at 1 kHz offset

phn_10k

phn_100k

phn_1M

phn_10M

phn_20M

t_RJIT

Phase noise at 10 kHz offset

Phase noise at 100 kHz offset

Phase noise at 1 MHz offset

Phase noise at 10 MHz offset

Phase noise at 20 MHz offset

Random additive jitter from 10 kHz to 20 MHz

Typical Additive Phase Noise Characteristics for 737.27 MHz Clock

PARAMETER

MIN

TYP

-80.2

-114.3

-138

MAX

UNIT

dBc/Hz

fs, RMS

phn₁₀₀

phn_1k

Phase noise at 100 Hz offset

Phase noise at 1 kHz offset

phn_10k

phn_100k

phn_1M

phn_10M

phn_20M

t_RJIT

Phase noise at 10 kHz offset

Phase noise at 100 kHz offset

Phase noise at 1 MHz offset

Phase noise at 10 MHz offset

Phase noise at 20 MHz offset

Random additive jitter from 10 kHz to 20 MHz

-143.9

-145.2

-146.5

-146.6

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TYPICAL CHARACTERISTICS

INPUT- AND OUTPUT-CLOCK PHASE NOISES

FREQUENCY FROM the CARRIER

(T_A= 25°C and V_CC= 2.5V)

Input clock RMS jitter is 32 fs from 10 kHz to 20 MHz and additive RMS jitter is 152 fs

Figure 3. 100 MHz Input and Output Phase Noise Plot

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TYPICAL CHARACTERISTICS (continued)

Differential Output Voltage

Frequency

350

= 25^oC

340

330

320

310

300

290

280

270

260

250

2.625V

2.5V

2.375V

100 200 300 400 500 600 700 800

Frequency − MHz

Figure 4.

TEST CONFIGURATIONS

Oscilloscope

100 W

LVDS

Figure 5. LVDS Output DC Configuration During Device Test

Phase Noise

Analyzer

LVDS

50 W

Figure 6. LVDS Output AC Configuration During Device Test

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TYPICAL CHARACTERISTICS (continued)

Figure 7. DC Coupled LVCMOS Input During Device Test

OUTNx

OUTPx

80%

(= 2 x V

)

20%

0 V

OUT,DIFF,PP

Figure 8. Output Voltage and Rise/Fall Time

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TYPICAL CHARACTERISTICS (continued)

INNx

INPx

PLH0

PHL0

PHL1

OUTN0

OUTP0

PLH1

OUTN1

OUTP1

PLH2

PHL2

OUTN2

OUTP2

PHL7

PLH7

OUTN7

OUTP7

A. Output skew is calculated as the greater of the following: As of the difference between the fastest and the slowest

t_PLHnor the difference between the fastest and the slowest t_PHLn(n = 0, 1, 2, ..7)

B. Part to part skew is calculated as the greater of the following: As the difference between the fastest and the slowest

t_PLHnor the difference between the fastest and the slowest t_PHLnacross multiple devices (n = 0, 1, 2, ..7)

Figure 9. Output Skew and Part-to-Part Skew

ring

OUTNx

0 V Differential

OUTPx

Figure 10. Output Overshoot and Undershoot

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TYPICAL CHARACTERISTICS (continued)

GND

Figure 11. Output AC Common Mode

APPLICATION INFORMATION

THERMAL MANAGEMENT

For reliability and performance reasons, the die temperature should be limited to a maximum of 125°C.

The device package has an exposed pad that provides the primary heat removal path to the printed circuit board

(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a

ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must be

soldered down to ensure adequate heat conduction to of the package. Figure 12 shows a recommended land

and via pattern.

3,0 mm (min)

0,33 mm (typ)

0,75 mm (typ)

Figure 12. Recommended PCB Layout

POWER SUPPLY FILTERING

High-performance clock buffers are sensitive to noises on the power supply, which can dramatically increase the

additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when

jitter/phase noise is critical to the application.

Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass

capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against

the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the

device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, they

must be placed close to the power-supply pins and laid out with short loops to minimize inductance. It is

recommended to add as many high-frequency (for example, 0.1 mF) bypass capacitors as there are supply pins

in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply and

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the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these

beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with

low dc resistance because it is imperative to provide adequate isolation between the board supply and the chip

supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for

proper operation.

Chip

Supply

Board

Supply

Ferrite Bead

1µF

10µF

0.1µF

(x3)

Figure 13. Power Supply Filtering

LVDS OUTPUT TERMINATION

The proper LVDS termination for signal integrity over two 50 Ω lines is 100 Ω between the outputs on the

receiver end. Either dc-coupled termination or ac-coupled termination can be used for LVDS outputs. It is

recommended to place termination resister close to the receiver. If the receiver is internally biased to a voltage

different than the output common mode voltage of the CDCLVD1208, ac-coupling should be used. If the LVDS

receiver has internal 100 Ω termination, external termination must be omitted.

Unused outputs can be left open without connecting any trace to the output pins.

Z = 50 W

100 W

LVDS

CDCLVD1208

Z = 50 W

Figure 14. LVDS Output DC Termination

100 nF

Z = 50 W

100 W

LVDS

CDCLVD1208

Z = 50 W

100 nF

Figure 15. LVDS Output AC Termination with Receiver Internally Biased

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INPUT TERMINATION

The CDCLVD1208 inputs can be interfaced with LVDS, LVPECL, or LVCMOS drivers.

LVDS Driver can be connected to CDCLVD1208 inputs with dc or ac coupling as shown Figure 16 and Figure 17

respectively.

Z = 50 W

100 W

LVDS

CDCLVD1208

Z = 50 W

Figure 16. LVDS Clock Driver Connected to CDCLVD1208 Input (DC coupled)

100 nF

Z = 50 W

LVDS

CDCLVD1208

Z = 50 W

100 nF

50 W

AC_REF

Figure 17. LVDS Clock Driver Connected to CDCLVD1208 Input (AC coupled)

Figure 18 shows how to connect LVPECL inputs to the CDCLVD1208. The series resistors are required to

reduce the LVPECL signal swing if the signal swing is >1.6 Vpp.

75 W

100 nF

Z = 50 W

CDCLVD1208

LVPECL

Z = 50 W

100 nF

50 W

75 W

150 W

50 W

AC_REF

Figure 18. LVPECL Clock Driver Connected to CDCLVD1208 Input

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Figure 19 illustrates how to couple a 2.5 V LVCMOS clock input to the CDCLVD1208 directly. The series

resistance (R_S) should be placed close to the LVCMOS driver if needed. 3.3 V LVCMOS clock input swing needs

to be limited to V_IH≤ V_CC

LVCMOS

(2.5V)

Z = 50 W

CDCLVD1208

Figure 19. 2.5V LVCMOS Clock Driver Connected to CDCLVD1208 Input

For unused input, it is recommended to ground both input pins (INP, INN) using 1 kΩ resistors.

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PACKAGE OPTION ADDENDUM

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23-Sep-2010

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

CDCLVD1208RHDR

CDCLVD1208RHDT

ACTIVE

VQFN

RHD

3000

250

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

Purchase Samples

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

Purchase Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Feb-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CDCLVD1208RHDR

CDCLVD1208RHDT

VQFN

RHD

3000

250

330.0

12.4

5.3

1.5

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Feb-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

CDCLVD1208RHDR

CDCLVD1208RHDT

VQFN

RHD

3000

250

338.1

20.6

Pack Materials-Page 2

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specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Audio

Applications

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

www.ti.com/security

Medical

Logic

Security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense www.ti.com/space-avionics-defense

microcontroller.ti.com

www.ti-rfid.com

Video and Imaging

www.ti.com/video

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community Home Page

e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

CDCLVD1208RHDR [TI]

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