CDCLVP1102RGTR [TI]
Two LVPECL Output, High-Performance Clock Buffer; 两个LVPECL输出，高性能时钟缓冲器
| 型号： | CDCLVP1102RGTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Two LVPECL Output, High-Performance Clock Buffer |
| 文件： | 总22页 (文件大小：753K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCLVP1102
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SCAS884C –AUGUST 2009–REVISED AUGUST 2011
Two LVPECL Output,
High-Performance Clock Buffer
Check for Samples: CDCLVP1102
1
FEATURES
DESCRIPTION
The CDCLVP1102 is a highly versatile, low additive
2
•
•
•
1:2 Differential Buffer
Single Clock Input
jitter buffer that can generate two copies of LVPECL
clock outputs from one LVPECL, LVDS, or LVCMOS
input for a variety of communication applications. It
has a maximum clock frequency up to 2 GHz. The
overall additive jitter performance is less than 0.1 ps,
RMS from 10 kHz to 20 MHz, and overall output
skew is as low as 10 ps, making the device a perfect
choice for use in demanding applications.
Universal Inputs Can Accept LVPECL, LVDS,
LVCMOS/LVTTL
•
•
•
•
Two LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 33 mA
Very Low Additive Jitter: <100 fs,rms in 10-kHz
to 20-MHz Offset Range
The CDCLVP1102 clock buffer distributes a single
clock input (IN) to two pairs of differential LVPECL
clock outputs (OUT0, OUT1) with minimum skew for
clock distribution. The inputs can be LVPECL, LVDS,
or LVCMOS/LVTTL.
•
•
•
•
2.375 V to 3.6 V Device Power Supply
Maximum Propagation Delay: 450 ps
Maximum Output Skew: 10 ps
The CDCLVP1102 is specifically designed for driving
50-Ω transmission lines. When driving the inputs in
single-ended mode, the LVPECL bias voltage
(VAC_REF) should be applied to the unused negative
input pin. However, for high-speed performance up to
2 GHz, differential mode is strongly recommended.
LVPECL Reference Voltage, VAC_REF, Available
for Capacitive-Coupled Inputs
•
•
Industrial Temperature Range: –40°C to +85°C
Available in 3-mm × 3-mm QFN-16 (RGT)
Package
•
ESD Protection Exceeds 2 kV (HBM)
The CDCLVP1102 is characterized for operation
from –40°C to +85°C and is available in a QFN-16,
3-mm × 3-mm package.
APPLICATIONS
•
•
•
•
Wireless Communications
Telecommunications/Networking
Medical Imaging
Test and Measurement Equipment
VCC
OUTP[1,0]
INP
INN
2
LVPECL
OUTN[1,0]
2
Reference
Generator
VAC_REF
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2011, Texas Instruments Incorporated
CDCLVP1102
SCAS884C –AUGUST 2009–REVISED AUGUST 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS(1)
TA
PACKAGED DEVICES
CDCLVP1102RGTT
CDCLVP1102RGTR
FEATURES
16-pin QFN (RGT) package, small tape and reel
16-pin QFN (RGT) package, tape and reel
–40°C to +85°C
(1) For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or
refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted).(1)
CDCLVP1102
–0.5 to 4.6
–0.5 to VCC + 0.5
–0.5 to VCC + 0.5
20
UNIT
V
VCC
VIN
Supply voltage range(2)
(3)
Input voltage range
V
(3)
VOUT
IIN
IOUT
TA
Output voltage range
V
Input current
mA
mA
°C
°C
°C
kV
Output current
50
Specified free-air temperature range (no airflow)
Storage temperature range
Maximum junction temperature
Electrostatic discharge (HBM)
–40 to +85
–65 to +150
+125
TSTG
TJ
ESD
2
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All supply voltages must be supplied simultaneously.
(3) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted).
CDCLVP1102
PARAMETER
Supply voltage
Ambient temperature
MIN
2.375
–40
TYP
MAX
3.60
+85
UNIT
V
VCC
TA
2.50/3.30
°C
PACKAGE DISSIPATION RATINGS(1) (2)
VALUE
TEST
2 × 2 VIAS
PARAMETER
CONDITIONS
ON PAD
UNIT
0 LFM
51.8
45
°C/W
°C/W
°C/W
°C/W
θJA
Thermal resistance, junction-to-ambient
Thermal resistance, junction-to-pad
150 LFM
400 LFM
40.8
6.12
(3)
θJP
(1) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC 2S2P (high-K board).
(2) Connected to GND with four thermal vias (0.3-mm diameter).
(3) θJP (junction-to-pad) is used for the QFN package, because the primary heat flow is from the junction to the GND pad of the QFN
package.
2
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ELECTRICAL CHARACTERISTICS: LVCMOS Input(1)
At VCC = 2.375 V to 3.6 V and TA = –40°C to +85°C (unless otherwise noted).
CDCLVP1102
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fIN
Input frequency
200
MHz
External threshold voltage applied to
complementary input
Vth
Input threshold voltage
1.1
1.8
V
VIH
Input high voltage
Input low voltage
Input high current
Input low current
Input edge rate
Vth + 0.1
0
VCC
th – 0.1
40
V
V
VIL
V
IIH
VCC = 3.6 V, VIH = 3.6 V
VCC = 3.6 V, VIL = 0 V
20% to 80%
μA
μA
V/ns
pF
IIL
–40
ΔV/ΔT
ICAP
1.5
Input capacitance
5
(1) Figure 3 and Figure 4 show dc test setup.
ELECTRICAL CHARACTERISTICS: Differential Input(1)
At VCC = 2.375 V to 3.6 V and TA = –40°C to +85°C (unless otherwise noted).
CDCLVP1102
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
2000
1.5
UNIT
MHz
V
fIN
Input frequency
Clock input
fIN ≤ 1.5 GHz
0.1
0.2
1.0
VIN, DIFF, PP
Differential input peak-peak voltage
1.5 GHz ≤ fIN ≤ 2 GHz
1.5
V
VICM
IIH
Input common-mode level
Input high current
Input low current
V
CC – 0.3
V
VCC = 3.6 V, VIH = 3.6 V
VCC = 3.6 V, VIL = 0 V
20% to 80%
40
μA
μA
V/ns
pF
IIL
–40
ΔV/ΔT
ICAP
Input edge rate
1.5
Input capacitance
5
(1) Figure 5 and Figure 6 show dc test setup. Figure 7 shows ac test setup.
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ELECTRICAL CHARACTERISTICS: LVPECL Output(1)
At VCC = 2.375 V to 2.625 V and TA = –40°C to +85°C (unless otherwise noted).
CDCLVP1102
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
CC – 0.9
CC – 1.3
1.35
UNIT
V
VOH
Output high voltage
V
CC – 1.26
V
V
VOL
Output low voltage
V
CC – 1.7
V
VOUT, DIFF, PP
VAC_REF
Differential output peak-peak voltage
Input bias voltage(2)
fIN ≤ 2 GHz
0.5
V
IAC_REF = 2 mA
VIN, DIFF, PP = 0.1V
VIN, DIFF, PP = 0.3V
V
CC – 1.6
VCC – 1.1
V
450
ps
ps
ps
ps
tPD
Propagation delay
450
tSK,PP
tSK,O
Part-to-part skew
Output skew
100
10
Crossing-point-to-crossing-point
distortion, fOUT = 100 MHz
tSK,P
Pulse skew (with 50% duty cycle input)
–50
50
ps
fOUT = 100 MHz, VIN,SE = VCC
Vth = 1.25 V, 10 kHz to 20 MHz
,
0.089
0.093
0.037
0.094
0.091
ps, RMS
ps, RMS
ps, RMS
ps, RMS
ps, RMS
fOUT = 100 MHz, VIN,SE = 0.9 V,
Vth = 1.1 V, 10 kHz to 20 MHz
Random additive jitter (with 50% duty
cycle input)
fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V,
VICM = 1 V, 10 kHz to 20 MHz
tRJIT
fOUT = 100 MHz, VIN,DIFF,PP = 0.15 V,
VICM = 1 V, 10 kHz to 20 MHz
fOUT = 100 MHz, VIN,DIFF,PP = 1 V,
VICM = 1 V, 10 kHz to 20 MHz
tR/tF
IEE
Output rise/fall time
20% to 80%
200
33
ps
Supply internal current
Outputs unterminated
mA
mA
ICC
Output and internal supply current
All outputs terminated, 50 Ω to VCC – 2
100
(1) Figure 8 and Figure 9 show dc and ac test setup.
(2) Internally generated bias voltage (VAC_REF) is for 3.3-V operation only. It is recommended to apply externally generated bias voltage for
VCC < 3.0 V.
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ELECTRICAL CHARACTERISTICS: LVPECL Output(1)
At VCC = 3.0 V to 3.6 V and TA = –40°C to +85°C (unless otherwise noted).
CDCLVP1102
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
CC – 0.9
CC – 1.3
1.35
UNIT
V
VOH
Output high voltage
V
CC – 1.26
V
V
VOL
Output low voltage
V
CC – 1.7
V
VOUT, DIFF, PP
VAC_REF
Differential output peak-peak voltage
Input bias voltage
fIN ≤ 2 GHz
0.65
V
IAC_REF = 2 mA
VIN, DIFF, PP = 0.1V
VIN, DIFF, PP = 0.3V
V
CC – 1.6
VCC – 1.1
V
450
ps
ps
ps
ps
tPD
Propagation delay
450
tSK,PP
tSK,O
Part-to-part skew
Output skew
100
10
Crossing-point-to-crossing-point
distortion, fOUT = 100 MHz
tSK,P
Pulse skew (with 50% duty cycle input)
–50
50
ps
fOUT = 100 MHz, VIN,SE = VCC
Vth = 1.65 V, 10 kHz to 20 MHz
,
0.081
0.097
0.050
0.098
0.095
ps, RMS
ps, RMS
ps, RMS
ps, RMS
ps, RMS
fOUT = 100 MHz, VIN,SE = 0.9 V,
Vth = 1.1 V, 10 kHz to 20 MHz
Random additive jitter (with 50% duty
cycle input)
fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V,
VICM = 1 V, 10 kHz to 20 MHz
tRJIT
fOUT = 100 MHz, VIN,DIFF,PP = 0.15 V,
VICM = 1 V, 10 kHz to 20 MHz
fOUT = 100 MHz, VIN,DIFF,PP = 1 V,
VICM = 1 V, 10 kHz to 20 MHz
tR/tF
IEE
Output rise/fall time
20% to 80%
200
33
ps
Supply internal current
Outputs unterminated
mA
mA
ICC
Output and internal supply current
All outputs terminated, 50 Ω to VCC – 2
100
(1) Figure 8 and Figure 9 show dc and ac test setup.
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RGT PACKAGE
QFN-16
(TOP VIEW)
13
14
15
16
8
7
6
5
VAC_REF
INN
NC
NC
NC
CDCLVP1102
INP
Thermal Pad(1)
GND
VCC
(1) Thermal pad must be soldered to ground.
PIN DESCRIPTIONS
CDCLVP1102 Pin Descriptions
TERMINAL
NAME
TERMINAL
NO.
TYPE
Power
Ground
Input
DESCRIPTION
VCC
5
2.5-V/3.3-V supply for the device
GND
1, 16
6, 7
Device ground
INP, INN
Differential input pair or single-ended input
OUTP1, OUTN1
OUTP0 OUTN0
11, 12
9, 10
Output
Output
Differential LVPECL output pair no. 1. Unused output pair can be left floating.
Differential LVPECL output pair no. 0. Unused output pair can be left floating.
Bias voltage output for capacitive-coupled input pair no. 0. Do not use VAC_REF at VCC
<
VAC_REF
8
Output
3.0 V. If used, it is recommended to use a 0.1-μF capacitor to GND on this pin. The output
current is limited to 2 mA.
2, 3, 4,
13, 14, 15
NC
—
Do not connect
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TYPICAL CHARACTERISTICS
At TA = –40°C to +85°C (unless otherwise noted).
DIFFERENTIAL OUTPUT PEAK-TO-PEAK VOLTAGE
vs FREQUENCY
1.0
VCC = 2.375 V
TA = -40°C to +85°C
0.9
VICM = 1 V
VIN,DIFF,PP = Min
0.8
0.7
0.6
0.5
0.4
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Frequency (GHz)
Figure 1.
DIFFERENTIAL OUTPUT PEAK-TO-PEAK VOLTAGE
vs FREQUENCY
1.1
1.2
1.3
1.0
0.9
0.8
0.7
0.6
0.5
0.4
VCC = 3.0 V
TA = -40°C to +85°C
VICM = 1 V
VIN,DIFF,PP = Min
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Frequency (GHz)
Figure 2.
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TEST CONFIGURATIONS
This section describes the function of each block for the CDCLVP1102. Figure 3 through Figure 9 illustrate how
the device should be setup for a variety of test configurations.
IN
VIH
Vth
VIL
IN
Vth
Figure 3. DC-Coupled LVCMOS Input During Device Test
VCC
VIHmax
Vthmax
VILmax
VIH
Vth
Vth
VIL
VIHmin
Vthmin
VILmin
GND
Figure 4. Vth Variation over LVCMOS Levels
VCC
VCC
130 W
130 W
CDCLVP1102
LVPECL
82 W
82 W
Figure 5. DC-Coupled LVPECL Input During Device Test
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100 W
CDCLVP1102
LVDS
Figure 6. DC-Coupled LVDS Input During Device Test
VCC
VCC
82 W
82 W
CDCLVP1102
Differential
130 W
130 W
Figure 7. AC-Coupled Differential Input to Device
Oscilloscope
LVPECL
50 W
50 W
VCC - 2 V
Figure 8. LVPECL Output DC Configuration During Device Test
Phase Noise
Analyzer
LVPECL
150 W
150 W
50 W
Figure 9. LVPECL Output AC Configuration During Device Test
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Figure 10 shows the output voltage and rise/fall time. Output and part-to-part skew are shown in Figure 11.
VOH
OUTNx
VOD
VOL
OUTPx
80%
20%
0 V
VOUT,DIFF,PP (= 2 ´ VOD)
tR
tF
Figure 10. Output Voltage and Rise/Fall Time
INN
INP
tPLH0
tPLH0
OUTN0
OUTP0
tPLH1
tPLH1
OUTN1
OUTP1
(1) Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn
(n = 0, 1), or as the difference between the fastest and the slowest tPHLn (n = 0, 1).
(2) Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest
tPLHn (n = 0, 1) across multiple devices, or the difference between the fastest and the slowest tPHLn (n = 0, 1) across
multiple devices.
Figure 11. Output and Part-to-Part Skew
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APPLICATION INFORMATION
Thermal Management
Power consumption of the CDCLVP1102 can be high enough to require attention to thermal management. For
reliability and performance reasons, the die temperature should be limited to a maximum of +125°C. That is, as
an estimate, ambient temperature (TA) plus device power consumption times θJA should not exceed +125°C.
The device package has an exposed pad that provides the primary heat removal path to the printed circuit board
(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a
ground plane must be incorporated into the PCB within the footprint of the package. The exposed pad must be
soldered down to ensure adequate heat conduction out of the package. Figure 12 shows a recommended land
and via pattern.
1,6 mm (min)
0,33 mm (typ)
0,5 mm (typ)
Figure 12. Recommended PCB Layout
Power-Supply Filtering
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter/phase noise is very critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system
against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required
by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors,
they must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. It
is recommended to add as many high-frequency (for example, 0.1-μF) bypass capacitors as there are supply
pins in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply
and the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these
beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with
very low dc resistance because it is imperative to provide adequate isolation between the board supply and the
chip supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required
for proper operation.
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Figure 13 illustrates this recommended power-supply decoupling method.
VCC
Board
Ferrite Bead
Supply
Chip
Supply
C
10 mF
C
1 mF
C
0.1 mF
Figure 13. Power-Supply Decoupling
LVPECL Output Termination
The CDCLVP1102 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are
required to ensure correct operation of the device and to minimize signal integrity. The proper termination for
LVPECL outputs is a 50 Ω to (VCC –2) V, but this dc voltage is not readily available on PCB. Therefore, a
Thevenin equivalent circuit is worked out for the LVPECL termination in both direct-coupled (dc) and ac-coupled
configurations. These configurations are shown in Figure 14a and b for VCC = 2.5 V and Figure 15a and b for VCC
= 3.3 V, respectively. It is recommended to place all resistive components close to either the driver end or the
receiver end. If the supply voltage for the driver and receiver is different, ac coupling is required.
VCC
VCC
250 W
250 W
CDCLVP1102
LVPECL
62.5 W
62.5 W
(a) Output DC Termination
VBB
CDCLVP1102
LVPECL
86 W
86 W
50 W
50 W
(b) Output AC Termination
Figure 14. LVPECL Output DC and AC Termination for VCC = 2.5 V
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VCC
VCC
130 W
130 W
CDCLVP1102
LVPECL
82 W
82 W
(a) Output DC Termination
VBB
CDCLVP1102
LVPECL
150 W
150 W
50 W
50 W
(b) Output AC Termination
Figure 15. LVPECL Output DC and AC Termination for VCC = 3.3 V
Input Termination
The CDCLVP1102 inputs can be interfaced with LVPECL, LVDS, or LVCMOS drivers. Figure 16 illustrates how
to dc couple an LVCMOS input to the CDCLVP1102. The series resistance (RS) should be placed close to the
LVCMOS driver; its value is calculated as the difference between the transmission line impedance and the driver
output impedance.
VIH
Vth
VIL
RS
LVCMOS
CDCLVP1102
VIH + VIL
Vth
=
2
Figure 16. DC-Coupled LVCMOS Input to CDCLVP1102
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Figure 17 shows how to dc couple LVDS inputs to the CDCLVP1102. Figure 18 and Figure 19 describe the
method of dc coupling LVPECL inputs to the CDCLVP1102 for VCC = 2.5 V and VCC = 3.3 V, respectively.
100 W
CDCLVP1102
LVDS
Figure 17. DC-Coupled LVDS Inputs to CDCLVP1102
VCC
VCC
250 W
250 W
CDCLVP1102
LVPECL
62.5 W
62.5 W
Figure 18. DC-Coupled LVPECL Inputs to CDCLVP1102 (VCC = 2.5 V)
VCC
VCC
130 W
130 W
CDCLVP1102
LVPECL
82 W
82 W
Figure 19. DC-Coupled LVPECL Inputs to CDCLVP1102 (VCC = 3.3 V)
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Figure 20 and Figure 21 show the technique of ac coupling differential inputs to the CDCLVP1102 for VCC = 2.5
V and VCC = 3.3 V, respectively. It is recommended to place all resistive components close to either the driver
end or the receiver end. If the supply voltages of the driver and receiver are different, ac coupling is required.
VCC
VCC
96 W
96 W
CDCLVP1102
Differential
105 W
105 W
Figure 20. AC-Coupled Differential Inputs to CDCLVP1102 (VCC = 2.5 V)
VCC
VCC
82 W
82 W
CDCLVP1102
Differential
130 W
130 W
Figure 21. AC-Coupled Differential Inputs to CDCLVP1102 (VCC = 3.3 V)
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May, 2010) to Revision C
Page
•
•
•
•
•
•
Corrected VIL parameter description in Electrical Characteristics table for LVCMOS inputs ............................................... 3
Added footnote (2) to Electrical Characteristics table for LVPECL Output, VCC = 2.375 V to 2.625 V ................................ 4
Revised description of pin 8 .................................................................................................................................................. 6
Changed recommended resistor values in Figure 14(a) .................................................................................................... 12
Changed resistor values in Figure 18 ................................................................................................................................. 14
Changed resistor values in Figure 19 ................................................................................................................................. 14
Changes from Revision A (October, 2009) to Revision B
Page
•
Changed description of OUTN1 and OUTN0 pins in Pin Descriptions table ........................................................................ 6
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Product Folder Link(s): CDCLVP1102
PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
CDCLVP1102RGTR
CDCLVP1102RGTT
ACTIVE
ACTIVE
QFN
QFN
RGT
RGT
16
16
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCLVP1102RGTR
CDCLVP1102RGTT
QFN
QFN
RGT
RGT
16
16
3000
250
330.0
330.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CDCLVP1102RGTR
CDCLVP1102RGTT
QFN
QFN
RGT
RGT
16
16
3000
250
338.1
338.1
338.1
338.1
20.6
20.6
Pack Materials-Page 2
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