CDCU877ARHARG4 [TI]
1.8-V PHASE LOCK LOOP CLOCK DRIVER;型号: | CDCU877ARHARG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | 1.8-V PHASE LOCK LOOP CLOCK DRIVER 驱动 逻辑集成电路 |
文件: | 总23页 (文件大小:1183K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CDCU877, CDCU877A
1.8-V PHASE LOCK LOOP CLOCK DRIVER
www.ti.com
SCAS688D–JUNE 2005–REVISED JULY 2007
FEATURES
•
•
Low Static Phase Offset: ±50 ps
•
1.8-V Phase Lock Loop Clock Driver for
Double Data Rate (DDR II) Applications
Distributes One Differential Clock Input to Ten
Differential Outputs
•
•
•
•
•
•
•
Spread Spectrum Clock Compatible
Operating Frequency: 10 MHz to 400 MHz
Low Current Consumption: <135 mA
Low Jitter (Cycle-Cycle): ±30 ps
Low Output Skew: 35 ps
•
•
52-Ball μBGA (MicroStar™ Junior BGA,
0,65-mm pitch) and 40-Pin MLF
External Feedback Pins (FBIN, FBIN) are Used
to Synchronize the Outputs to the Input
Clocks
•
•
Meets or Exceeds JESD82-8 PLL Standard for
PC2-3200/4300
Low Period Jitter: ±20 ps
Low Dynamic Phase Offset: ±15 ps
Fail-Safe Inputs
DESCRIPTION
The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock
input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock
outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks
(FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the
clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in
frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions
as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running.
When AVDD is grounded, the PLL is turned off and bypassed for test purposes.
When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection
circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low
power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being
logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the
PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within
the specified stabilization time.
The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from
—40°C to 85°C.
ORDERING INFORMATION
(1)
TA
52-BALL BGA
CDCU877ZQL
CDCU877AZQL
CDCU877GQL
CDCU877AGQL
40-Pin MLF
CDCU877RHA
CDCU877ARHA
CDCU877RTB
CDCU877ARTB
-40°C to 85°C
(1) For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see the
TI website at www.ti.com.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CDCU877, CDCU877A
1.8-V PHASE LOCK LOOP CLOCK DRIVER
www.ti.com
SCAS688D–JUNE 2005–REVISED JULY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
MicroStar Junior (ZQL) Package
(TOP VIEW)
1
2
3
4
5
6
A
B
Y6
Y1
GND
GND
C
D
NB
NB
Y7
Y2
GND
GND
Y7
Y2
V
OS
DDQ
DDQ
CK
V
V
DDQ
NB
NB
NB
NB
E
FBIN
V
V
DDQ
DDQ
F
FBIN
OE
CK
V
DDQ
G
FBOUT
AGND
V
V
DDQ
DDQ
V
V
DDQ
DDQ
NB
NB
H
J
FBOUT
GND
AV
DD
GND
Y8
Y3
GND
GND
K
A. NC = No Connection
B. NB = No Ball
RHA/RTB Package (MLF PAckage
(TOP VIEW)
40 39 38 37 36 35 34 33 32 31
1
30
29
28
27
26
25
24
23
22
21
VDDQ
Y2
Y7
2
Y7
3
Y2
VDDQ
FBIN
FBIN
FBOUT
FBOUT
VDDQ
OE
4
CK
5
CK
GND
6
VDDQ
AGND
AVDD
VDDQ
GND
7
8
9
10
OS
11 12 13 14 15 16 17 18 19 20
40-pin HP-VFQFP-N (6,0 x 6,0 mm Body Size,
0,5 mm Pitch, M0#220, Variation VJJD-2,
E2 = D2 = 2,9 mm ± 0,15 mm) Package Pinouts
2
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1.8-V PHASE LOCK LOOP CLOCK DRIVER
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SCAS688D–JUNE 2005–REVISED JULY 2007
TERMINAL FUNCTIONS
TERMINAL
GQL/ZQL
I/O
DESCRIPTION
NAME
RHA/RTB
AGND
AVDD
CK
G1
H1
E1
7
8
4
Analog ground
Analog power
I
I
Clock input with a (10 kΩ to 100 kΩ) pulldown resistor
Complementary clock input with a (10 kΩ to 100 kΩ) pulldown
resistor
CK
F1
5
FBIN
FBIN
FBOUT
FBOUT
OE
E6
F6
H6
G6
F5
D5
27
26
24
25
22
21
I
I
Feedback clock input
Complementary feedback clock input
Feedback clock output
O
O
I
Complementary feedback clock output
Output enable (asynchronous)
OS
I
Output select (tied to GND or VDD
)
B2, B3, B4, B5,
C2, C5, H2, H5,
J2, J3, J4, J5
GND
10
Ground
D2, D3, D4, E2,
E5, F2, G2, G3,
G4, G5
1, 6, 9, 15, 20, 23,
28, 31, 36
VDDQ
Y[0:9]
Y[0:9]
Logic and output power
Clock outputs
A2, A1, D1, J1, K3, 3, 11, 14, 16, 19,
A5, A6, D6, J6, K4 29, 33, 34, 38, 39
O
O
A3, B1, C1, K1,
2, 12, 13, 18, 17,
K2, A4, B6, C6,
30, 32, 35, 37, 40
K6, K5
Complementary clock outputs
FUNCTION TABLE
INPUTS
OUTPUTS
AVDD
OE
H
OS
X
CK
L
CK
H
Y
L
Y
H
L
FBOUT
FBOUT
PLL
GND
GND
GND
L
H
L
H
L
Bypassed/Off
Bypassed/Off
Bypassed/Off
H
X
H
L
H
LZ
L
H
L
H
LZ
H
LZ
LZ
GND
L
L
L
L
H
L
H
L
L
H
L
H
L
L
H
L
Bypassed/Off
Y7 Active
Y7 Active
1.8 V Nominal
1.8 V Nominal
LZ
LZ
On
On
LZ
LZ
H
H
Y7 Active
Y7 Active
1.8 V Nominal
1.8 V Nominal
1.8 V Nominal
X
H
H
X
X
X
X
X
X
L
H
L
H
L
L
H
H
L
L
H
L
On
On
Off
H
L
LZ
LZ
LZ
LZ
H
H
Reserved
3
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1.8-V PHASE LOCK LOOP CLOCK DRIVER
www.ti.com
SCAS688D–JUNE 2005–REVISED JULY 2007
Figure 1. LOGIC DIAGRAM (POSITIVE LOGIC)
4
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CDCU877, CDCU877A
1.8-V PHASE LOCK LOOP CLOCK DRIVER
www.ti.com
SCAS688D–JUNE 2005–REVISED JULY 2007
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)(3)
VDDQ or AVDD
–0.5
2.5
–0.5 VDDQ + 0.5
V
VO
IIK
Output voltage range(2)(3)
–0.5 VDDQ + 0.5
V
Input clamp current
VI < 0 or VI > VDDQ
VO < 0 or VO > VDDQ
VO = 0 to VDDQ
±50
±50
mA
mA
mA
mA
°C
IOK
IO
Output clamp current
Continuous output current
Continuous current through each VDDQ or GND
Storage temperature range
±50
±100
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This value is limited to 2.5 V maximum.
Recommended Operating Conditions
MIN
NOM
1.8
MAX
UNIT
V
Output supply voltage, VDDQ
1.7
1.9
VCC
(1)
Supply Voltage, AVDD
VDDQ
V
VIL
VIH
IOH
IOL
VIX
VI
Low-level input voltage(2)
High-level input voltage(2)
OE, OS
CK, CK
0.35 x VDDQ
V
0.65 x VDDQ
V
High-level output current (see Figure 2)
Low-level output current (see Figure 2)
Input differential-pair cross voltage
Input voltage level
-9
9
mA
mA
V
(VDDQ/2) - 0.15
(VDDQ/2) + 0.15
VDDQ + 0.3
VDDQ + 0.4
VDDQ + 0.4
85
-0.3
0.3
0.6
-40
V
Input differential voltage(2)
(see Figure 9 )
DC
AC
V
VID
TA
V
Operating free-air temperature
°C
(1) The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the
recommended operating conditions and no timing parameters are specified.
(2) VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 9 for definition. The CK and
CK, VIH and VIL limits define the dc low and high levels for the logic detect state.
5
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1.8-V PHASE LOCK LOOP CLOCK DRIVER
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SCAS688D–JUNE 2005–REVISED JULY 2007
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
AVDD
VDDQ
,
PARAMETER
TEST CONDITIONS
II = 18 mA
MIN TYP(1)
MAX UNIT
VIK
Input
1.7
-1.2
V
V
IOH = –100 μA
IOH = –9 mA
1.7 to 1.9 VDDQ – 0.2
VOH
High-level output voltage
Low-level output voltage
1.7
1.1
IOL = 100 μA
0.1
0.6
VOL
V
IOL = 9 mA
1.7
1.7
1.7
1.9
IO(DL)
VOD
Low-level output current, dissabled
Differential output voltage(1)
CK, CK
VO(DL) = 100 mV, OE = L
100
0.5
μA
V
±250
±10
II
Input current
μA
μA
OE, OS,
FBIN, FBIN
1.9
1.9
IDD(LD)
Supply current, static (IDDQ + IADD
)
CK and CK = L
500
CK and CK = 270 MHz. All
outputs are open (not connected
to a PCB)
1.9
135
Supply current, dynamic (IDDQ + IADD
)
IDD
mA
pF
(see Note (2) for CPD calculation)
All outputs are loaded with 2 pF
and 120-Ω termination resistor
1.9
235
CK, CK
1.8
1.8
1.8
1.8
2
2
3
3
CI
Input capacitance
VI = VDD or GND
VI = VDD or GND
FBIN, FBIN
CK, CK
0.25
0.25
CI(Δ)
Change in input current
FBIN, FBIN
(1) VOD is the magnitude of the difference between the true and complimentary outputs. See Figure 9 for a definition.
(2) Total IDD = IDDQ + IADD = fCK × CPD × VDDQ, solving for CPD = (IDDQ + IADD)/(fCK × VDDQ) where fCK is the input frequency, VDDQ is the
power supply, and CPD is the power dissipation capacitance.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
10
MAX
400
340
60%
12
UNIT
MHz
MHz
Clock frequency (operating)(1)(2)
Clock frequency (application)(1)(3)
Duty cycle, input clock
fCK
160
40%
AVDD, VDD = 1.8 V ±0.1 V
tDC
tL
(4)
Stabiliztion time
μs
(1) The PLL must be able to handle spread spectrum induced skew.
(2) Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other
timing parameters (used for low speed system debug).
(3) Application clock frequency indicates a range over which the PLL must meet all timing parameters.
(4) Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after
power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of
its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active
operation. CK and CK may be left floating after they have been driven low for one complete clock cycle.
6
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1.8-V PHASE LOCK LOOP CLOCK DRIVER
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SCAS688D–JUNE 2005–REVISED JULY 2007
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see (1)) AVDD, VDD = 1.8 V ± 0.1 V
PARAMETER
TEST CONDITIONS
See Figure 11
MIN
TYP
MAX
8
UNIT
ns
ten
Enable time, OE to any Y/Y
Disable time, OE to any Y/Y
tdis
See Figure 11
8
ns
tjit(cc+)
tjit(cc-)
tjit(cc+)
tjit(cc-)
t(ω)
0
0
40
-40
30
-30
50
15
35
30
20
115
70
40
60
Cycle-to-cycle period jitter(2)
160 MHz to 190 MHz, see Figure 4
ps
ps
0
Cycle-to-cycle period jitter(2)
Static phase offset time(3)
160 MHz to 340 MHz, see Figure 4
0
See Figure 5
-50
-15
ps
ps
ps
t(ω)dyn Dynamic phase offset time
See Figure 10
tsk(o)
Output clock skew
See Figure 6
160 MHz to 190 MHz, see Figure 7
190 MHz to 340 MHz, see Figure 7
160 MHz to 190 MHz, see Figure 8
190 MHz to 250 MHz, see Figure 8
250 MHz to 300 MHz, see Figure 8
300 MHz to 340 MHz, see Figure 8
See Figure 3 and Figure 9
See Figure 3 and Figure 9
See Figure 3 and Figure 9
-30
-20
-115
-70
-40
-60
0.5
1
(4)(2)
tjit(per) Period jitter
ps
tjit(hper) Half-period jitter(4)(2)
ps
Slew rate, OE
SR
Input clock slew rate
Output clock slew rate(5)(6) (no load)
2.5
2.5
4
3
V/ns
V
1.5
(VDDQ/2) -
0.1
(VDDQ/2) +
0.1
CDCU877, See Figure 2
(7)
VOX
Output differential-pair cross voltage
CDCU877A(8), See Figure 2
(0 - 85°C)
(VDDQ/2) -
0.1
(VDDQ/2) +
0.1
SSC modulation frequency
SSC clock input frequency deviation
PLL loop bandwidth
30
0%
2
33
kHz
-0.5%
MHz
(1) There are two different terminations that are used with the following tests. The load/board in Figure 2 is used to measure the input and
output differential-pair cross voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length
cables must be used.
(2) This parameter is specifieded by design and characterization.
(3) Phase static offset time does not include jitter.
(4) Period jitter, half-period jitter specifications are separate specifications that must be met independently of each other.
(5) The output slew rate is determined from the IBIS model with a 120-Ω load only.
(6) To eliminate the impact of input slew rates on static phase offset, the input skew rates of reference clock input CK and CK and feedback
clock inputs FBIN and FBIN are recommended to be nearly equal. The 2.5-V/ns skew rates are shown as a recommended target.
Compliance with these typical values is not mandatory if it can adequately shown that alternative characteristics meet the requirements
of the registered DDR2 DIMM application.
(7) Output differential-pair cross voltage specified at the DRAM clock input or the test load.
(8) VOX of CDCU877A is on average 30 mV lower than that of CDCU877 for the same application.
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1.8-V PHASE LOCK LOOP CLOCK DRIVER
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SCAS688D–JUNE 2005–REVISED JULY 2007
PARAMETER MEASUREMENT INFORMATION
V
DD
CU877
SCOPE
GND
C = 10 pF
Z = 60 W
L = 2.97”
R = 1 MW
R = 1 MW
C = 1 pF
Z = 120 W
Z = 60 W
V
TT
L = 2.97”
C = 1 pF
C = 10 pF
GND
V
TT
Note: V = GND
TT
Figure 2. Output Load Test Circuit 1
V /2
DD
CU877
SCOPE
−V /2
DD
C = 10 pF
Z = 60 W
Z = 50 W
L = 2.97”
R = 10 W
R = 50 W
V
V
TT
Z = 60 W
Z = 50 W
L = 2.97”
R = 10 W
R = 50 W
C = 10 pF
−V /2
TT
DD
Note: V = GND
TT
−V /2
DD
Figure 3. Output Load Test Circuit 2
Yx, FBOUT
Yx, FBOUT
t
t
cycle n+1
cycle n
t
= t
− t
cycle n+1
jit(cc)
cycle n
Figure 4. Cycle-To-Cycle Period Jitter
8
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1.8-V PHASE LOCK LOOP CLOCK DRIVER
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SCAS688D–JUNE 2005–REVISED JULY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
tjn
tjn+1
Figure 5. Static Phase Offset
å1n = N
N
tjn
tj =
(N is the large number of samples)
(N > 1000 samples)
(1)
Figure 6. Output Skew
Figure 7. Period Jitter
1
t
= t
-
cycle n
jit(per)
f
O
(fO average input frequency measured at CK/CK
(2)
9
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1.8-V PHASE LOCK LOOP CLOCK DRIVER
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SCAS688D–JUNE 2005–REVISED JULY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. Half-Period Jitter
1
t
= t
-
half period n
jit(hper)
2 x f
O
n = any half cycle
(fO average input frequency measured at CK/CK
(3)
80%
80%
VID, VOD
20%
20%
Clock Inputs
and Outputs, OE
tr(i), tr(o)
tf(i), tf(o)
Figure 9. Input and Output Slew Rates
V
- V
V
- V
20%
80%
t
20%
80%
slrr
=
slrf
=
(i/o)
(i/o)
t
f(i/o)
r(i/o)
(4)
tj
tj
tjdyn
tjdyn
tjdyn
tjdyn
Figure 10. Dynamic Phase Offset
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1.8-V PHASE LOCK LOOP CLOCK DRIVER
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SCAS688D–JUNE 2005–REVISED JULY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 11. Time Delay Between OE and Clock Output (Y, Y)
RECOMMENDED AVDD FILTERING
Bead
0603
CARD
VIA
AV DD
VDDQ
1 W
0.1 mF
4.7 mF
2200 pF
0603
PLL
0603
1206
GND
AGND
CARD
VIA
A. Place the 2200-pF capacitor close to the PLL.
B. Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect
trace to one GND via (farthest from the PLL).
C. Recommended bead: Fair-Rite PN 2506036017Y0 or equilvalent (0.8 Ω dc maximum, 600 Ω at 100 MHz).
Figure 12. Recommended AVDD Filtering
11
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PACKAGE OPTION ADDENDUM
www.ti.com
22-Nov-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
NMK
NMK
RHA
Qty
1000
250
(1)
(2)
(3)
(4/5)
(6)
CDCU877ANMKR
CDCU877ANMKT
CDCU877ARHAR
CDCU877ARHARG4
CDCU877ARHAT
CDCU877AZQLR
ACTIVE
NFBGA
NFBGA
VQFN
VQFN
VQFN
52
52
40
40
40
52
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
CDCU877A
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
SNAGCU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
CDCU877A
CDCU877A
CDCU877A
CDCU877A
CDCU877A
2500
2500
250
Green (RoHS
& no Sb/Br)
RHA
Green (RoHS
& no Sb/Br)
RHA
Green (RoHS
& no Sb/Br)
BGA
ZQL
1000
Green (RoHS
& no Sb/Br)
MICROSTAR
JUNIOR
CDCU877AZQLT
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQL
52
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-2-260C-1 YEAR
-40 to 85
CDCU877A
CDCU877RHAR
CDCU877RHARG4
CDCU877RHAT
CDCU877RHATG4
CDCU877RTBR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
RHA
RHA
RHA
RHA
RHA
40
40
40
40
40
2500
2500
250
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
CDCU877
CDCU877
CDCU877
CDCU877
CDCU877
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
2500
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Nov-2020
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Nov-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCU877ANMKR
CDCU877ANMKT
CDCU877ARHAR
CDCU877ARHAT
CDCU877AZQLR
NFBGA
NFBGA
VQFN
NMK
NMK
RHA
RHA
ZQL
52
52
40
40
52
1000
250
330.0
180.0
330.0
180.0
330.0
16.4
16.4
16.4
16.4
16.4
4.8
4.8
6.3
6.3
4.8
7.3
7.3
6.3
6.3
7.3
1.5
1.5
1.1
1.1
1.5
8.0
8.0
16.0
16.0
16.0
16.0
16.0
Q2
Q1
Q2
Q2
Q1
2500
250
12.0
12.0
8.0
VQFN
BGA MI
CROSTA
R JUNI
OR
1000
CDCU877AZQLT
BGA MI
CROSTA
R JUNI
OR
ZQL
52
250
180.0
16.4
4.8
7.3
1.5
8.0
16.0
Q1
CDCU877RHAR
CDCU877RHAT
VQFN
VQFN
RHA
RHA
40
40
2500
250
330.0
180.0
16.4
16.4
6.3
6.3
6.3
6.3
1.1
1.1
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Nov-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CDCU877ANMKR
CDCU877ANMKT
CDCU877ARHAR
CDCU877ARHAT
CDCU877AZQLR
NFBGA
NFBGA
VQFN
NMK
NMK
RHA
RHA
ZQL
52
52
40
40
52
1000
250
336.6
213.0
367.0
853.0
350.0
336.6
191.0
367.0
449.0
350.0
28.6
55.0
38.0
35.0
43.0
2500
250
VQFN
BGA MICROSTAR
JUNIOR
1000
CDCU877AZQLT
BGA MICROSTAR
JUNIOR
ZQL
52
250
213.0
191.0
55.0
CDCU877RHAR
CDCU877RHAT
VQFN
VQFN
RHA
RHA
40
40
2500
250
367.0
853.0
367.0
449.0
38.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
NMK0052A
4.6
4.4
B
A
BALL A1 CORNER
7.1
6.9
1 MAX
C
SEATING PLANE
0.25
0.15
0.1 C
BALL TYP
3.25
TYP
(0.63) TYP
SYMM
K
(0.58) TYP
J
H
G
F
SYMM
5.85
TYP
E
D
C
B
A
0.35
0.25
52X Ø
0.15
0.05
C
C
A B
0.65 TYP
0.65 TYP
1
2
3
4
5
6
4225135/A 08/2019
NanoFree is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
NMK0052A
(0.65) TYP
1
2
3
4
5
6
(0.65) TYP
A
B
C
D
E
F
52X (Ø0.35)
SYMM
G
H
J
K
SYMM
LAND PATTERN EXAMPLE
SCALE: 10X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED
METAL
SOLDER MASK
OPENING
(Ø0.35)
SOLDER MASK
OPENING
(Ø0.35) EXPOSED
METAL
METAL
NON- SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225135/A 08/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
NMK0052A
(0.65) TYP
1
2
3
4
5
6
(0.65) TYP
A
B
C
D
E
F
52X (Ø0.35)
SYMM
G
H
J
K
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4225135/A 08/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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