CDCUA877_V01 [TI]

1.8-V PHASE LOCK LOOP CLOCK DRIVER;


型号：	CDCUA877_V01
厂家：	TEXAS INSTRUMENTS
描述：	1.8-V PHASE LOCK LOOP CLOCK DRIVER 驱动
文件：	总16页 (文件大小：615K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CDCUA877

www.ti.com

SCAS769A–AUGUST 2006–REVISED JUNE 2007

1.8-V PHASE LOCK LOOP CLOCK DRIVER

FEATURES

•

Distributes One Differential Clock Input to Ten

Differential Outputs

•

1.8-V/1.9-V Phase Lock Loop Clock Driver for

Double Data Rate (DDR II) Applications

52-Ball μBGA (MicroStar Junior™ BGA,

0,65-mm pitch)

•

Spread Spectrum Clock Compatible

Operating Frequency: 125 MHz to 410 MHz

Application Frequency: 160 MHz to 410 MHz

Low Current Consumption: <200 mA Typ

Low Jitter (Cycle-Cycle): ±40 ps

Low Output Skew: 35 ps

External Feedback Pins (FBIN, FBIN) are Used

to Synchronize the Outputs to the Input

Clockst

•

Meets or Exceeds CUA877/CAU878

Specification PLL Standard for

PC2-3200/4300/5300/6400o

Stabilization Time <6 μs

Fail-Safe Inputs

DESCRIPTION

The CDCUA877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock

input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock

outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks

(FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AV_DD). When OE is low, the

clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in

frequency. OS (output select) is a program pin that must be tied to GND or V_DD. When OS is high, OE functions

as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running.

When AV_DDis grounded, the PLL is turned off and bypassed for test purposes.

When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection

circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low

power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being

logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the

PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within

the specified stabilization time.

The CDCUA877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from

–40°C to 85°C).

AVAILABLE OPTIONS

T_A

52-Ball BGA⁽¹⁾

–40°C to 85°C

CDCUA877ZQL

(1) For the most current package and ordering information, see the

Package Option Addendum at the end of this document, or see the

TI website at www.ti.com.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MicroStar Junior is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CDCUA877

www.ti.com

SCAS769A–AUGUST 2006–REVISED JUNE 2007

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CDCUA877

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SCAS769A–AUGUST 2006–REVISED JUNE 2007

Table 1. Terminal Functions

NAME

BGA

MLF

I/O

DESCRIPTION

AGND

Analog ground

Analog power

AV_DD

Clock input with a (10 kΩ to 100 kΩ) pulldown resistor

Complementary clock input with a (10 kΩ to 100 kΩ) pulldown resistor

Feedback clock input

FBIN

FBOUT

Complementary feedback clock input

Feedback clock output

Complementary feedback clock output

Output enable (asynchronous)

Output select (tied to GND or VDD)

Ground

GND

B2, B3, B4,

B5, C2, C5,

H2, H5, J2, J3,

J4, J5

V_DDQ

D2, D3, D4,

E2, E5, F2,

G2, G3, G4,

1, 6, 9, 15, 20,

23, 28, 31, 36

Logic and output power

Y[0:9]

A2, A1, D1,

J1, K3, A5, A6, 34, 33, 29, 19, 16

D6, J6, K4

38, 39, 3, 11, 14,

Clock outputs

A3, B1, C1,

K1, K2, A4,

37, 40, 2, 12, 13,

35, 32, 30, 18, 17

Complementary clock outputs

B6, C6, K6, K5

Table 2. Function Table

INPUTS

OUTPUTS

PLL

AV_DD

FBOUT

GND

Bypassed/Off

L_Z

Y7 Active

1.8 V Nomnal

L_Z

Y7 Active

1.8 V Nomnal

Off

L_Z

Reserved

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CDCUA877

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SCAS769A–AUGUST 2006–REVISED JUNE 2007

Figure 1. Logic Diagram (Positive Logic)

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

VALUE

UNIT

V_DDQ

Supply voltage range

A_VDD

–0.5 to 2.5

V_I

Input voltage range^{(2) (3)}

–0.5 to V_DDQ+ 0.5

V_O

I_IK

Output voltage range^{(2) (3)}

–0.5 to V_DDQ+ 0.5

Input clamp current, (V_I< 0 or V_I> V_DDQ

)

±50

I_OK

I_O

Output clamp voltage, (V_O< 0 or V_O> V_DDQ

Continuous output current, (V_O= 0 to V_DDQ

)

±50

I_DDC

Continuous current through each V_DDQor GND

Thermal resistance, junction-to-ambient⁽⁴⁾

±100

No airflow

151.9

146.1

102.4

–65 to 150

R_θJA

Airllflow 150 ft/min

No airflow

K/W

R_θJC

T_STG

Thermal resistance, junction-to-case⁽⁴⁾

Storage temperature range

°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3) This value is limited to 2.5 V maximum.

(4) The package thermal impedance is calculated in accordance with JESD51 and JEDEC2S1P (high-k board).

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SCAS769A–AUGUST 2006–REVISED JUNE 2007

RECOMMENDED OPERATING CONDITIONS

MIN

NOM

1.8

MAX

UNIT

V_DDQ

AV_DD

V_IL

Output supply voltage

Supply voltage⁽¹⁾

Low-level input voltage⁽²⁾

1.7

1.9

V_DDQ

CK, CK, OE,

0.35 × V_DDQ

V_IH

High-level input voltage⁽²⁾

CK, CK, OE,

0.65 × V_DDQ

I_OH

I_OL

V_IX

V_I

High-level output current (see Figure 2)

Low-level output current (see Figure 2)

Input differential-pair cross voltage

Input voltage level

–9

(V_DDQ/2)-0.15

(V_DDQ/2)+0.15

V_DDQ+0.3

V_DDQ+0.4

–0.3

0.3

V_ID

T_A

Input differential voltage⁽²⁾(see Figure 10)

Operating free-air temperature

0.6

–40

°C

(1) The PLL is turned off and bypassed for test purposes when AV_DDis grounded. During this test mode, V_DDQremains within the

recommended operating conditions and no timing parameters are ensured.

(2) V_IDis the magnitude of the difference between the input level on CK and the input level on CK, see Figure 10 for definition. The CK and

CK V_IHand V_ILlimits define the dc low and high levels for the logic detect state.

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SCAS769A–AUGUST 2006–REVISED JUNE 2007

ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range

AV_DD

V_DDG

PARAMETER

Input (cl inputs)

TEST CONDITIONS

MIN TYP MAX

UNIT

V_IK

I_I= –18 mA

1.7 V

–1.2

I_OH= -100 ＝A

1.7 V to 1.9 V

VDDQ

– 0.2

V_OHHigh-level output voltage

I_OH= –9 mA

1.7 V

1.1

I_OL= 100 μA

0.1

0.6

V_OLLow-level output voltage

I_OL= 9 mA

1.7 V

1.9 V

I_O(DL)Low-level output current, disabled

V_ODDifferential output voltage⁽¹⁾

CK, CK

V_O(DL)= 100 mV, OE = L

100

0.5

μA

±250

±10

I_I

Input current

μA

OE, OS, FBIN,

FBIN

I_DD(L

CK and CK = L

1.9 V

500

225

Supply current, static (I_DDQ+ I_ADD

)

μA

CK and CK = 410 MHz,

All outputs are open

(not connected to a PCB)

Supply current, dynamic ( I_DDQ+ I_ADD

)

I_DD

(see ⁽²⁾for C_PDcalculation)

All outputs are loaded with 2 pF

and 120-Ω termination resistor,

CK and CK = 410 MHz

CK, CK

Input capacitance

V_I= V_DDor GND

1.8 V

C_I

FBIN, FBIN

CK, CK

0.25

Change in input

current

C_I(Δ)

FBIN, FBIN

(1) V_ODis the magnitude of the difference between the true and complimentary outputs. See Figure 10 for a definition.

(2) Total I_DD= I_DDQ+ I_ADD= f_CK× C_PD× V_DDQ, solving for C_PD= (I_DDQ+ I_ADD)/(f_CK× V_DDQ) where f_CKis the input frequency, V_DDQis the

power supply, and C_PDis the power dissipation capacitance.

TIMING REQUIREMENTS

over recommended operating free-air temperature range

PARAMETER

Clock frequency (operating)^{(1) (2)}

Clock frequency (application)^{(1) (3)}

Duty cycle, input clock

TEST CONDITIONS

AV_DD, V_DD= 1.8 V ±0.1 V

MIN TYP

125

MAX UNIT

410

60%

MHz

f_CK

AV_DD, V_DD= 1.8 V ±0.1 V

160

t_DC

t_L

40%

Stabilization time⁽⁴⁾

μs

(1) The PLL must be able to handle spread spectrum induced skew.

(2) Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other

timing parameters (used for low speed system debug).

(3) Application clock frequency indicates a range over which the PLL must meet all timing parameters.

(4) Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal,

within the value specified by the static phase offset t_(φ), after power up. During normal operation, the stabilization time is also the time

required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic

low state, enter the power-down mode, and later return to active operation. CK and CK may be left floating after they have been driven

low for one complete clock cycle.

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SCAS769A–AUGUST 2006–REVISED JUNE 2007

SWITCHING CHARACTERISTICS

over recommended operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

See Figure 12

MIN

TYP

MAX

UNIT

t_en

Enable time, OE to any Y/Y

Disable time, OE to any Y/Y

t_dis

See Figure 12

t_jit(cc+)

t_jit(cc-)

t_(φ)

–40

Cycle-to-cycle period jitter⁽²⁾

Static phase offset time⁽³⁾

160 MHz to 410 MHz, See Figure 5

See Figure 6

–50

–20

t_(φ)dynDynamic phase offset time,⁽⁴⁾

See Figure 11

t_sk(o)

Output clock skew⁽⁴⁾

See Figure 7

160 MHz to 270 MHz, see Figure 8

271 MHz to 410 MHz, see Figure 8

160 MHz to 270 MHz, see Figure 9

271 MHz to 410 MHz, see Figure 9

271 MHz to 410 MHz

–30

–20

–75

–50

(2)(5)

t_jit(per)Period jitter

(2) (5)

t_jit(hper)Half-period jitter

(6)

Σt_(su)

Σt_(h)

|t_jit(per)| + |t_(φ)dyn| + t_sk(o)

(6)

|t_(φ)dyn| + + t_sk(o)

271 MHz to 410 MHz

Slew rate, OE

See Figure 3 and Figure 8

0.5

Input clock skew rate

Output clock slew rate⁽⁷⁾⁽⁸⁾

2.5

V/ns

1.5

Output differential-pair cross

voltage⁽⁹⁾

V_OX

See Figure 2

(V_DDQ/2) – 0.1

(V_DDQ/2) + 0.1

SSC modulation frequency

kHz

SSC clock input frequency

deviation

–0.5%

PLL loop bandwidth

MHz

(1) There are two different terminations that are used with the following tests. The load/board in Figure 2 is used to measure the input and

output differential-pair cross voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length

cables must be used.

(2) This parameter is assured by design and characterization.

(3) Phase static offset time does not include jitter.

(4) For full frequency range of 160MHz to 410MHz.

(5) Period jitter, half-period jitter specifications are separate specifications that must be met independently of each other.

(6) In the frequency range of 271 MHz to 410 MHz, the minimum and maximum values of t_jit(per)and t_(φ)dynand the maximum value for t_sk(o)

must not exceed the corresponding minimum and maximum values of the 160 MHz to 270 MHz range. In addition, the sum of the

and t_sk(o)must meet the requirements for the Σt_(h)

(7) The output slew rate is determined from the IBIS model into the load shown in Figure 4.

(8) To eliminate the impact of input slew rates on static phase offset, the input skew rates of reference clock input CK and CK and feedback

clock inputs FBIN and FBIN are recommended to be nearly equal. The 2.5-V/ns skew rates are shown as a recommended target.

Compliance with these typical values is not mandatory if it can adequately shown that alternative characteristics meet the requirements

of the registered DDR2 DIMM application.

(9) Output differential-pair cross voltage specified at the DRAM clock input or the test load.

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CDCUA877

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SCAS769A–AUGUST 2006–REVISED JUNE 2007

Figure 2. Output Load Test Circuit 1 (Using High-Impedance Probe)

Figure 3. Output Load Test Circuit 2 (Using SMA Coaxial Cable)

Figure 4. IBIS Model Output Load

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SCAS769A–AUGUST 2006–REVISED JUNE 2007

c(n+1)

c(n)

c(n+1)

Figure 5. Cycle-To-Cycle Period Jitter

( )n

Figure 6. Static Phase Offset

Figure 7. Output Skew

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SCAS769A–AUGUST 2006–REVISED JUNE 2007

(n)

Figure 8. Period Jitter

(half period)n

Figure 9. Half-Period Jitter

Figure 10. Input and Output Slew Rates

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SCAS769A–AUGUST 2006–REVISED JUNE 2007

t_{( )}

t_{( )dyn}

Figure 11. Dynamic Phase Offset

t_{( )dyn}

Figure 12. Time Delay Between OE and Clock Output (Y, Y)

A. Place the 2200-pF capacitor close to the PLL.

B. Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect

trace to one GND via (farthest from the PLL).

C. Recommended bead: Fair-Rite PN 2506036017Y0 or equilvalent (0.8Ω dc maximum, 600Ω at 100 MHz).

Figure 13. Recommended AV_DDFiltering

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PACKAGE OPTION ADDENDUM

www.ti.com

22-Nov-2008

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

CDCUA877ZQLR

ACTIVE

BGA MI

CROSTA

R JUNI

ZQL

1000 Green (RoHS &

no Sb/Br)

SNAGCU

Level-2-260C-1 YEAR

CDCUA877ZQLT

ACTIVE

BGA MI

CROSTA

R JUNI

ZQL

250 Green (RoHS &

no Sb/Br)

SNAGCU

Level-2-260C-1 YEAR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Jun-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

CDCUA877ZQLR

BGA MI

CROSTA

R JUNI

ZQL

1000

330.0

16.4

4.8

7.3

1.5

8.0

16.0

CDCUA877ZQLT

BGA MI

CROSTA

R JUNI

ZQL

250

330.0

16.4

4.8

7.3

1.5

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Jun-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

CDCUA877ZQLR

BGA MICROSTAR

JUNIOR

ZQL

1000

333.2

345.9

28.6

CDCUA877ZQLT

BGA MICROSTAR

JUNIOR

ZQL

250

333.2

345.9

28.6

Pack Materials-Page 2

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CDCUA877_V01 [TI]

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