CDCV857DGGG4 [TI]
1:10 DDR Phase-Lock Loop Clock Driver 48-TSSOP 0 to 70;
| 型号： | CDCV857DGGG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1:10 DDR Phase-Lock Loop Clock Driver 48-TSSOP 0 to 70 驱动 双倍数据速率 光电二极管 逻辑集成电路 |
| 文件： | 总14页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
DGG PACKAGE
(TOP VIEW)
Phase-Lock Loop Clock Driver for Double
Data-Rate Synchronous DRAM
Applications
GND
Y0
GND
Y5
1
48
47
46
45
44
Spread Spectrum Clock Compatible
Operating Frequency: 60 to 200 MHz
Low Jitter (cyc–cyc): ±75 ps
2
Y0
Y5
3
V
V
4
DDQ
Y1
DDQ
Y6
5
Distributes One Differential Clock Input to
Ten Differential Outputs
Y1
GND
GND
Y2
6
43 Y6
7
42 GND
41 GND
40 Y7
Three-State Outputs When the Input
Differential Clocks Are <20 MHz
8
9
Operates From Dual 2.5-V Supplies
48-Pin TSSOP Package
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Y2
Y7
V
V
DDQ
DDQ
Consumes < 200-µA Quiescent Current
V
PWRDWN
FBIN
DDQ
CLK
External Feedback PIN (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
CLK
FBIN
V
V
DDQ
DDQ
AV
FBOUT
FBOUT
GND
Y8
DD
description
AGND
GND
Y3
The CDCV857 is a high-performance, low-skew,
low-jitter zero delay buffer that distributes a
differential clock input pair (CLK, CLK) to ten
differential pairs of clock outputs (Y[0:9], Y[0:9])
and one differential pair of feedback clock output
(FBOUT, FBOUT). The clock outputs are
controlled by the clock inputs (CLK, CLK), the
feedback clocks (FBIN, FBIN), and the analog
Y3
Y8
V
V
DDQ
Y4
DDQ
Y9
Y4
Y9
GND
GND
power input (AV ). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When
DD
PWRDWNislow, alloutputsaredisabledtohighimpedancestate(3-state), andthePLLisshutdown(lowpower
mode). The device also enters this low power mode when the input frequency falls below a suggested detection
frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low
frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and
enables the outputs.
When AV
is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857 is also able
DD
to track spread spectrum clocking for reduced EMI.
Since the CDCV857 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up. The CDCV857 is characterized for operation from 0°C
to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
FUNCTION TABLE
(Select Functions)
INPUTS
PWRDWN
OUTPUTS
Y[0:9] FBOUT
PLL
AV
DD
CLK
L
CLK
Y[0:9]
FBOUT
GND
GND
H
H
L
H
L
L
H
Z
Z
L
H
L
L
H
Z
Z
L
H
L
Bypassed/Off
H
Bypassed/Off
X
L
H
L
Z
Z
H
L
Z
Z
H
L
Off
Off
On
On
Off
X
L
H
2.5 V (nom)
2.5 V (nom)
2.5 V (nom)
H
H
X
L
H
L
H
H
Z
H
Z
<20 MHz <20 MHz
Z
Z
functional block diagram
3
Y0
2
Y0
5
Y1
37
PWRDWN
6
Powerdown
and Test
Logic
Y1
16
AV
DD
10
Y2
9
Y2
20
Y3
19
Y3
22
Y4
23
Y4
46
Y5
47
Y5
13
14
CK
CK
44
Y6
43
Y6
PLL
FBIN 36
39
Y7
35
FBIN
40
Y7
29
Y8
30
Y8
27
Y9
26
Y9
32
FBOUT
33
FBOUT
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
Terminal Functions
TERMINAL
NAME
AGND
AV
I/O
DESCRIPTION
NO.
17
Ground for 2.5-V analog supply
2.5-V Analog supply
16
DD
CLK, CLK
FBIN, FBIN
FBOUT, FBOUT
GND
13, 14
35, 36
32, 33
I
I
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
O
1, 7, 8, 18,
24, 25, 31,
41, 42, 48
PWRDWN
37
I
Output enable for Y and Y
2.5-V Supply
V
DDQ
4, 11, 12,
15, 21, 28,
34, 38, 45
Y[0:9]
Y[0:9]
3, 5, 10,
20, 22, 27,
29, 39, 44,
46
O
O
Buffered output copies of input clock, CLK
Buffered output copies of input clock, CLK
2, 6, 9, 19,
23, 26, 30,
40, 43, 47
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
AV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V
,
DDQ
DD
Input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
0.5 V
0.5 V
I
DDQ
DDQ
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
IK
I
I
DDQ
O
Output clamp current, I
(V < 0 or V > V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
DDQ
OK
O
Continuous output current, I (V = 0 to V
Continuous current to GND or V
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
Storage temperature range T
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
O
O
DDQ
JA
stg
DDQ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
recommended operating conditions (see Note 4)
MIN
TYP
MAX
UNIT
Supply voltage, V
DDQ,
AV
DD
2.3
2.7
V
CLK, CLK, FBIN, FBIN
PWRDWN
V
DDQ
/2 – 0.18
0.7
Low level input voltage, V
V
IL
–0.3
CLK, CLK, FBIN, FBIN
PWRDWN
V
DDQ
/2 + 0.18
High level input voltage, V
V
V
V
IH
DC input signal voltage (see Note 5)
1.7
–0.3
0.36
0.7
V
+ 0.3
DDQ
V
DDQ
+ 0.6
DC
AC
CLK, FBIN
CLK, FBIN
V
V
DDQ
Differential input signal voltage, V (see Note 6)
ID
+ 0.6
DDQ
Output differential cross-voltage, V
OX
(see Note 7)
V
/2 – 0.2
V
DDQ
/2
V
/2 + 0.2
/2 + 0.2
–12
V
V
DDQ
DDQ
Input differential pair cross-voltage, V (see Note 7)
IX
V
DDQ
/2 – 0.2
V
DDQ
High-level output current, I
mA
mA
V/ns
°C
OH
Low-level output current, I
Input slew rate, SR
12
OL
1
0
4
Operating free-air temperature, T
85
A
NOTES: 4. Unused inputs must be held high or low to prevent them from floating.
5. DC input signal voltage specifies the allowable dc execution of differential input.
6. Differentialinput signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level
and VCP is the complementary input level.
7. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be
crossing.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
Input voltage
All inputs
V
V
V
V
V
V
V
= 2.3 V,
I = –18 mA
–1.2
V
IK
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
I
= min to max, I
= –1 mA
= –12 mA
= 1 mA
= 12 mA
= 1 V
V
– 0.1
1.7
OH
OH
OL
OL
DDQ
High-level output voltage
Low-level output voltage
V
V
OH
= 2.3 V,
I
= min to max, I
0.1
0.6
V
OL
= 2.3 V,
= 2.3 V,
= 2.3 V,
I
I
I
High-level output current
Low-level output current
Output voltage swing
V
–18
26
–32
35
mA
mA
OH
O
O
V
= 1.2 V
OL
V
O
1.1
V
– 0.4
DDQ
Differential outputs are terminated with
120 Ω
V
Output differential
cross-voltage
V
OX
V
/2 – 0.2
V
/2
V
/2 + 0.2
±10
DDQ
DDQ
DDQ
I
I
Input current
V
V
= 2.7 V,
= 2.7 V,
V = 0 V to 2.7 V
I
µA
µA
I
DDQ
High-impedance-state
output current
V
O
= V or GND
DDQ
±10
OZ
DDQ
Power down current on
CLK and CLK = 0 MHz; PWRDWN = Low;
Σ of I and AI
I
100
200
µA
DDPD
V
DDQ
+ AV
DD
DD
DD
all outputs loaded
as shown in
Figure 3
f
= 200 MHz
= 167 MHz
275
250
330
300
O
O
I
Dynamic current on V
mA
DD
DDQ
f
f
f
= 200 MHz
= 167 MHz
10
8
12
10
3
O
AI
DD
Supply current on AV
mA
DD
O
C
C
Input capacitance
Output capacitance
V
V
= 2.5 V
= 2.5 V
V = V
or GND
2
2.5
3
pF
pF
I
CC
I
CC
= V or GND
CC
V
O
2.5
3.5
O
CC
†
‡
All typical values are at respective nominal V
.
DDQ
is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120-Ω resistor, where VTR is the true input
The value of V
OC
signal voltage and VCP is the complementary input signal voltage.
§
Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
Operating clock frequency
Application clock frequency
Input clock duty cycle
f
60
200
MHz
CK
40%
60%
10
Stabilization time (PLL mode)
µs
Stabilization time (Bypass mode)
30
ns
¶
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phasereferencesignalmustbepresentatCLK. Untilphaselockisobtained, thespecificationsforpropagationdelay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
switching characteristics
PARAMETER
TEST CONDITIONS
Test mode/CLK to any output
Test mode/CLK to any output
66 MHz
MIN TYP
4.5
4.5
MAX
UNIT
ns
t
t
Low to high level propagation delay time
High-to low level propagation delay time
PLH
ns
PHL
–90
–75
90
75
ps
t
t
t
Jitter (period), See Figure 6
jit(per)
100/133/167/200 MHz
66 MHz
ps
–180
–75
180
75
Jitter (cycle-to-cycle), See Figure 3
Half-period jitter, See Figure 7
ps
ps
jit(cc)
100/133/167/200 MHz
66 MHz
–160
–100
1
160
100
4
jit(hper)
100/133/167/200 MHz
t
t
Input clock slew rate, See Figure 8
Output clock slew rate, See Figure 8
V/ns
V/ns
slr(i)
1
2
slr(o)
66 MHz
SSC off 100/133 MHz
167/200 MHz
–180
–130
–90
180
130
90
Dynamic phase offset (this includes jitter), See
Figure 4(b)
t
ps
d(Ø)
66 MHz
–230
–170
–100
–100
–150
230
170
100
100
50
SSC on 100/133 MHz
167/200 MHz
66/100/133/167 MHz
200 MHz
t
Static phase offset, See Figure 4(a)
ps
(Ø)
tsk
(o)
tr, tf
Output skew, See Figure 5
75
ps
ps
Output rise and fall times (20% – 80%)
Load: 120 Ω/14 pF
650
900
†
All typical values are at a respective nominal V
Refers to transition of noninverting output.
This parameter is assured by design but can not be 100% production tested.
.
DDQ
‡
§
¶
All differential output pins are terminated with 120 Ω/14 pF.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
PARAMETER MEASUREMENT INFORMATION
V
DD
V
(CK)
R = 60 Ω
R = 60 Ω
V
DD
/2
V
(CK)
CDCV857
GND
Figure 1. IBIS Model Output Load (used for slew rate measurement)
V
DD
/2
C = 14 pF
SCOPE
CDCV857
–V /2
DD
R = 10 Ω
Z = 50 Ω
Z = 60 Ω
Z = 60 Ω
R = 50 Ω
(TT)
V
R = 10 Ω
Z = 50 Ω
R = 50 Ω
(TT)
C = 14 pF
V
–V /2
DD
–V /2
DD
NOTE: V
(TT)
= GND
Figure 2. Output Load Test Circuit
Yx, FBOUT
Yx, FBOUT
t
t
c(n+1)
c(n)
t
= t
– t
jit(cc) c(n) c(n+1)
Figure 3. Cycle-to-Cycle Jitter
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
PARAMETER MEASUREMENT INFORMATION
CK
CK
FBIN
FBIN
t
t
(
) n
(
) n+1
n = N
1
∑
t
(
) n
t
=
)
(
N
(N is a large number of samples)
(a) Static Phase Offset
CK
CK
FBIN
FBIN
t
t
(
)
( )
t
t
d(
)
d( )
t
t
d(
)
d( )
(b)
Dynamic Phase Offset
Figure 4. Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
t
sk(o)
Figure 5. Output Skew
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
PARAMETER MEASUREMENT INFORMATION
Yx, FBOUT
Yx, FBOUT
t
c(n)
Yx, FBOUT
Yx, FBOUT
1
f
o
1
t
= t –
jit(per) cn
f
o
Figure 6. Period Jitter
Yx, FBOUT
Yx, FBOUT
t
t
(hper_n+1)
(hper_n)
1
f
o
1
t
= t
jit(hper) (hper_n) –
2xf
o
Figure 7. Half-Period Jitter
80%
80%
V , V
ID OD
20%
20%
Clock Inputs
and Outputs
t
, t
slrr(i) slrr(o)
t
, t
slrf(i) slrf(o)
Figure 8. Input and Output Slew Rates
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
MECHANICAL DATA
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2005
PACKAGING INFORMATION
Orderable Device
CDCV857DGG
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
48
48
48
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
CDCV857DGGG4
CDCV857DGGR
CDCV857DGGRG4
TSSOP
TSSOP
TSSOP
DGG
DGG
DGG
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CDCV857DGGR
TSSOP
DGG
48
2000
330.0
24.4
8.6
15.8
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DGG 48
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
CDCV857DGGR
2000
Pack Materials-Page 2
IMPORTANT NOTICE
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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
Logic
Military
Power Mgmt
Microcontrollers
RFID
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
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