CDCVF2509 [TI]
3.3-V PHASE-LOCK LOOP CLOCK DRIVER; 3.3 -V锁相环时钟驱动器![CDCVF2509](http://pdffile.icpdf.com/pdf1/p00047/img/icpdf/CDCVF2509_245371_icpdf.jpg)
型号: | CDCVF2509 |
厂家: | ![]() |
描述: | 3.3-V PHASE-LOCK LOOP CLOCK DRIVER |
文件: | 总11页 (文件大小:146K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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CDCVF2509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS637 – DECEMBER 1999
PW PACKAGE
(TOP VIEW)
Designed to Meet and Exceed PC133
SDRAM Registered DIMM Specification
Rev. 1.1
AGND
CLK
AV
1
24
23
22
21
20
19
18
17
16
15
14
13
Spread Spectrum Clock Compatible
V
2
CC
CC
Operating Frequency 50 MHz to 175 MHz
1Y0
1Y1
1Y2
GND
GND
1Y3
V
3
CC
Static Phase Error Distribution at 66MHz to
166 MHz is ±125 ps
2Y0
2Y1
GND
GND
2Y2
2Y3
4
5
6
Jitter (cyc – cyc) at 66 MHz to 166 MHz is
|70| ps
7
8
Advanced Deep Sub-Micron Process
Results in More Than 40% Lower Power
Consumption Versus Current Generation
PC133 Devices
1Y4
9
V
10
11
12
V
CC
CC
1G
FBOUT
2G
FBIN
Available in Plastic 24-Pin TSSOP
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
Distributes One Clock Input to One Bank of
Five and One Bank of Four Outputs
Separate Output Enable for Each Output
Bank
External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input
25-Ω On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3 V
description
The CDCVF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDCVF2509 operates at 3.3 V V . It also
CC
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output
signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled
or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in
phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDCVF2509 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDCVF2509 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AV
to ground.
CC
The CDCVF2509 is characterized for operation from 0°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF2509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS637 – DECEMBER 1999
description (continued)
For application information refer to application reports High Speed Distribution Design Techniques for
CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread
Spectrum Clocking (SSC) (literature number SCAA039).
FUNCTION TABLE
INPUTS
2G
OUTPUTS
2Y
1Y
(0:4)
1G
CLK
FBOUT
(0:3)
X
L
X
L
L
H
H
H
H
L
L
L
L
L
H
H
H
H
L
H
L
L
H
H
H
H
H
L
H
H
functional block diagram
11
1G
3
4
5
8
9
1Y0
1Y1
1Y2
1Y3
1Y4
14
2G
21
20
2Y0
2Y1
17
16
24
2Y2
CLK
PLL
13
2Y3
FBIN
12
FBOUT
23
AV
CC
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF2509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS637 – DECEMBER 1999
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
(PW)
0°C to 85°C
CDCVF2509PWR
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME
NO.
Clockinput. CLKprovidestheclocksignaltobedistributedbytheCDCVF2509clockdriver. CLKisused
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.
CLK
24
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally
zero phase error between CLK and FBIN.
FBIN
1G
13
I
I
Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4) are
disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same
frequency as CLK.
11
Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are
disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same
frequency as CLK.
2G
14
12
I
Feedbackoutput. FBOUTisdedicatedforexternalfeedback. ItswitchesatthesamefrequencyasCLK.
When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an
integrated 25-Ω series-damping resistor.
FBOUT
1Y (0:4)
2Y (0:3)
O
O
O
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via the
1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input. Each
output has an integrated 25-Ω series-damping resistor.
3, 4, 5, 8, 9
21, 20, 17, 16
23
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via the
2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input. Each
output has an integrated 25-Ω series-damping resistor.
Analogpowersupply.AV
CC
providesthepowerreferencefortheanalogcircuitry.Inaddition,AV
can
is strapped to ground, PLL is bypassed and
CC
AV
CC
Power be used to bypass the PLL for test purposes. When AV
CLK is buffered directly to the device outputs.
CC
AGND
1
Ground Analog ground. AGND provides the ground reference for the analog circuitry.
V
CC
GND
2, 10, 15, 22
6, 7, 18, 19
Power Power supply
Ground Ground
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF2509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS637 – DECEMBER 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, AV
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.3 V
< V
+0.7 V
CC
CC
CC
Supply voltage range, V
CC
Input voltage range, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Voltage range applied to any output in the high or low state,
V
(see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, I
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V
Maximum power dissipation at T = 55°C (in still air) (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, T
IK
OK
I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
O O CC
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. AV
must not exceed V + 0.7 V
CC
CC
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 4.6 V maximum.
4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation, refertothePackageThermalConsiderationsapplicationnoteintheABTAdvancedBiCMOSTechnologyData
Book, literature number SCBD002.
DISSIPATION RATING TABLE
‡
BOARD
TYPE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
POWER RATING
A
A
PACKAGE
R
θJA
†
POWER RATNG
ABOVE T = 25°C
POWER RATING
A
JEDEC low-K
JEDEC high-K
114.5°C/W
62.1°C/W
920 mW
8.7 mW/°C
520 mW
390 mW
PW
1690 mW
16.1 mW/°C
960 mW
720 mW
†
‡
JECEC high-K board has better thermal performance due to multiple internal copper planes.
This is the inverse of the traditional junction-to-ambient thermal resistance (R ).
θJA
recommended operating conditions (see Note 5)
MIN
3
MAX
UNIT
V
V
V
V
V
, AV
CC
Supply voltage
3.6
CC
High-level input voltage
Low-level input voltage
Input voltage
2
V
IH
0.8
V
IL
0
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Operating free-air temperature
–12
12
mA
mA
°C
OH
OL
T
A
85
NOTE 5: Unused inputs must be held high or low to prevent them from floating.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
50
MAX
175
60%
1
UNIT
f
Clock frequency
MHz
clk
Input clock duty cycle
40%
†
Stabilization time
ms
†
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phasereferencesignalmustbepresentatCLK. Untilphaselockisobtained, thespecificationsforpropagationdelay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF2509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS637 – DECEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
TYP
PARAMETER
TEST CONDITIONS
V
CC
, AV
CC
MIN
MAX
UNIT
V
IK
Input clamp voltage
I = –18 mA
I
3 V
–1.2
V
I
I
I
I
I
I
= –100 µA
= –12 mA
= –6 mA
= 100 µA
= 12 mA
= 6 mA
MIN to MAX
3 V
V
CC
–0.2
OH
OH
OH
OL
OL
OL
V
High-level output voltage
Low-level output voltage
High-level output current
2.1
2.4
V
V
OH
3 V
MIN to MAX
3 V
0.2
0.8
V
OL
3 V
0.55
V
V
V
V
V
V
= 1 V
3 V
–28
30
O
O
O
O
O
O
I
= 1.65 V
= 3.135 V
= 1.95 V
= 1.65 V
= 0.4 V
3.3 V
3.6 V
3 V
–36
40
mA
mA
OH
–8
I
Low-level output current
Input current
3.3 V
3.6 V
3.6 V
OL
10
I
I
V = V
or GND
or GND,
±5
µA
µA
I
I
CC
CC
Supply current
(static, output not switching)
V = V
Outputs: low or high
I
O
= 0,
I
§
0 V, 3.6 V
40
CC
One input at V – 0.6 V,
CC
Other inputs at V
∆I
Change in supply current
3.3 V to 3.6 V
500
µA
CC
or GND
CC
or GND
C
C
Input capacitance
Output capacitance
V = V
3.3 V
3.3 V
2.5
2.8
pF
pF
i
I
CC
= V or GND
CC
V
O
o
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
For dynamic I vs Frequency, refer to Figures 8 and 9.
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF2509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS637 – DECEMBER 1999
switching characteristics over recommended ranges of supply voltage and operating free-air
‡
temperature, C = 25 pF (see Note 6 and Figures 1 and 2)
L
V
, AV
± 0.3 V
= 3.3 V
CC
CC
FROM
(INPUT)/CONDITION
TO
(OUTPUT)
PARAMETER
UNIT
MIN
TYP
MAX
Phase error time – static
(normalized)
(see Figures 3 – 6)
CLK↑ = 66 MHz to166 MHz
FBIN↑
–125
125
ps
ps
§
t
Output skew time
Any Y
Any Y
100
50
sk(o)
Phase error time – jitter
(see Note 7)
Any Y or FBOUT
–50
CLK = 66 MHz to 166 MHz
CLK = 100 MHz to 166 MHz
ps
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
|70|
|65|
Jitter
(see Figure 7)
(cycle-cycle)
Duty cycle
Rise time
Fall time
f
> 60 MHz
= 0.4 V to 2 V
= 0.4 V to 2 V
45%
0.5
55%
2.5
(CLK)
t
t
V
ns/V
ns/V
r
O
O
V
0.5
2.5
f
Low-to-high propagation
delay time, bypass mode
t
CLK
CLK
Any Y or FBOUT
Any Y or FBOUT
0.4
0.4
2.3
2.3
ns
ns
PLH(bypass mode)
High-to-low propagation
delay time, bypass mode
t
PHL(bypass mode)
‡
§
These parameters are not production tested.
The t
specification is only valid for equal loading of all outputs.
sk(o)
NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
7. Calculated per PC DRAM SPEC (t , static – jitter ).
phase error (cycle-to-cycle)
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF2509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS637 – DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
Input
50% V
CC
t
pd
From Output
Under Test
V
V
OH
2 V
0.4 V
2 V
Output
500
50% V
CC
0.4 V
25 pF
OL
t
t
f
r
LOAD CIRCUIT FOR OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 133 MHz, Z = 50 Ω, t ≤ 1.2 ns, t ≤ 1.2 ns.
O
r
f
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
CLKIN
FBIN
t
phase error
FBOUT
Any Y
t
sk(o)
Any Y
Any Y
t
sk(o)
Figure 2. Phase Error and Skew Calculations
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF2509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS637 – DECEMBER 1999
TYPICAL CHARACTERISTICS
STATIC PHASE ERROR
vs
STATIC PHASE ERROR
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
600
400
600
400
V
= 3.3 V
V
= 3.3 V
CC
= 100 MHz
CC
f = 133 MHz
c
f
C
c
= 25 pF || 500 Ω
(LY1–n)
= 25°C
C
= 25 pF || 500 Ω
(LY1–n)
T = 25°C
A
T
A
See Notes A, B, and C
See Notes A, B, and C
200
0
200
0
CLK to Y1–n
CLK to Y1–n
–200
–200
CLK to FBOUT
CLK to FBOUT
–400
–600
–400
–600
3
8
13
18
23
28
33
38
3
8
13
18
23
28
33
38
C
– Lumped Feedback Capacitance at FBIN – pF
C
– Lumped Feedback Capacitance at FBIN – pF
(LF)
(LF)
Figure 3
Figure 4
STATIC PHASE ERROR
vs
SUPPLY VOLTAGE AT FBOUT
STATIC PHASE ERROR
vs
CLOCK FREQUENCY
0
0
–50
f
C
C
= 133 MHz
c
V
C
C
= 3.3 V
CC
= 25 pF || 500 Ω
= 12 pF || 500 Ω
= 25°C
(LY)
(LF)
= 25 pF || 500 Ω
= 12 pF || 500 Ω
–50
(LY)
(LF)
= 25°C
T
A
T
A
–100
–100
See Notes A, B, and C
See Notes A, B, and C
–150
–200
–250
–150
–200
–250
CLK to FBOUT
CLK to FBOUT
–300
–350
–400
–300
–350
–400
3
3.1
3.2
3.3
3.4
3.5
3.6
50
75
100
125
150
175
200
V
CC
– Supply Voltage – V
f
– Clock Frequency – MHz
c
Figure 5
Figure 6
NOTES: A. Trace length FBOUT to FBIN = 5 mm, Z = 50 Ω
O
B.
C.
C
C
= Lumped capacitive load Y
(LY)
1–n
= Lumped feedback capacitance at FBOUT = FBIN
(LFx)
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF2509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS637 – DECEMBER 1999
TYPICAL CHARACTERISTICS
JITTER
ANALOG SUPPLY CURRENT
vs
vs
CLOCK FREQUENCY AT FBOUT
CLOCK FREQUENCY
140
120
100
25
V
= 3.3 V
CC
AV
CC
= V
= 3.6 V
CC
Bias = 0/3 V
C
C
T
= 25 pF || 500 Ω
= 12 pF || 500 Ω
(LY)
(LF)
C
C
T
= 25 pF || 500 Ω
= 12 pF || 500 Ω
(LY)
(LF)
A
= 25°C
20
15
10
A
See Notes C and D
= 25°C
See Notes A and B
80
60
Cycle to Cycle
40
5
0
20
0
50
75
100
125
150
175
200
0
25
50
75 100 125 150
175 200
f
– Clock Frequency – MHz
c
f
– Clock Frequency – MHz
c
Figure 7
Figure 8
SUPPLY CURRENT
vs
CLOCK FREQUENCY
250
AV
= V
= 3.6 V
CC
CC
Bias = 0/3 V
C
C
= 25 pF || 500 Ω
= 12 pF || 500 Ω
= 25°C
(LY)
(LF)
200
150
100
T
A
See Notes A and B
50
0
0
25
50
75 100 125 150
175 200
f
– Clock Frequency – MHz
c
Figure 9
NOTES: A. Trace length FBOUT to FBIN = 5 mm, Z = 50 Ω
O
B. Total current = I
+ AI
CC
CC
C.
D.
C
C
= Lumped capacitive load Y
1–n
(LFx)
(LY)
= Lumped feedback capacitance at FBOUT = FBIN
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF2509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS637 – DECEMBER 1999
MECHANICAL INFORMATION
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,30
0,19
0,65
M
0,10
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
0,75
A
0,50
Seating Plane
0,10
1,20 MAX
0,05 MIN
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/E 08/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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In order to minimize risks associated with the customer’s applications, adequate design and operating
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