CDCVF855PWR [TI]
2.5V 锁相环路 DDR 时钟驱动器 | PW | 28 | -40 to 85;
| 型号： | CDCVF855PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.5V 锁相环路 DDR 时钟驱动器 | PW | 28 | -40 to 85 时钟 驱动 双倍数据速率 光电二极管 逻辑集成电路 时钟驱动器 |
| 文件： | 总14页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCVF855
www.ti.com
SCAS839A–APRIL 2007–REVISED MAY 2007
2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER
FEATURES
DESCRIPTION
•
•
•
Spread-Spectrum Clock Compatible
The CDCVF855 is a high-performance, low-skew,
low-jitter, zero-delay buffer that distributes
differential clock input pair (CLK, CLK) to
a
4
Operating Frequency: 60 MHz to 220 MHz
Low Jitter (Cycle-Cycle): ±60 ps (±40 ps at 200
MHz)
differential pairs of clock outputs (Y[0:3], Y[0:3]) and
one differential pair of feedback clock outputs
(FBOUT, FBOUT). The clock outputs are controlled
by the clock inputs (CLK, CLK), the feedback clocks
(FBIN, FBIN), and the analog power input (AVDD).
When PWRDWN is high, the outputs switch in phase
and frequency with CLK. When PWRDWN is low, all
outputs are disabled to a high-impedance state
(3-state) and the PLL is shut down (low-power
mode). The device also enters this low-power mode
when the input frequency falls below a suggested
detection frequency that is below 20 MHz (typical 10
MHz). An input frequency-detection circuit detects
the low-frequency condition and, after applying a
>20-MHz input signal, this detection circuit turns the
PLL on and enables the outputs.
•
•
•
•
•
•
•
•
Low Static Phase Offset: ±50 ps
Low Jitter (Period): ±60 ps (±30 ps at 200 MHz)
1-to-4 Differential Clock Distribution (SSTL2)
Best in Class for VOX = VDD/2 ±0.1 V
Operates From Dual 2.6-V or 2.5-V Supplies
Available in a 28-Pin TSSOP Package
Consumes < 100-µA Quiescent Current
External Feedback Pins (FBIN, FBIN) Are Used
to Synchronize the Outputs to the Input
Clocks
•
•
•
Meets/Exceeds JEDEC Standard (JESD82-1)
For DDRI-200/266/333 Specification
When AVDD is strapped low, the PLL is turned off
and bypassed for test purposes. The CDCVF855 is
also able to track spread-spectrum clocking for
reduced EMI.
Meets/Exceeds Proposed DDRI-400
Specification (JESD82-1A)
Enters Low-Power Mode When No CLK Input
Signal Is Applied or PWRDWN Is Low
Because the CDCVF855 is based on PLL circuitry, it
requires a stabilization time to achieve phase-lock of
the PLL. This stabilization time is required following
power up. The CDCVF855 is characterized for both
commercial and industrial temperature ranges.
APPLICATIONS
•
•
DDR Memory Modules (DDR400/333/266/200)
Zero-Delay Fan-Out Buffer
AVAILABLE OPTIONS
TA
TSSOP (PW)
–40°C to 85°C
CDCVF855PW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
CDCVF855
www.ti.com
SCAS839A–APRIL 2007–REVISED MAY 2007
FUNCTION TABLE
(Select Functions)
INPUTS
OUTPUTS
Y[0:3] FBOUT
PLL
AVDD
GND
PWRDWN
CLK
CLK
Y[0:3]
FBOUT
H
H
L
L
H
L
H
Z
Z
L
H
L
L
H
Z
Z
L
H
L
Bypassed/off
GND
H
L
Bypassed/off
X
L
H
Z
Z
H
L
Z
Z
H
L
Off
Off
On
On
Off
X
L
H
L
2.5 V (nom)
2.5 V (nom)
2.5 V (nom)
H
H
X
L
H
H
L
H
Z
H
Z
<20 MHz
<20 MHz
Z
Z
PW PACKAGE
(TOP VIEW)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
Y0
GND
Y3
2
3
Y0
VDDQ
Y3
VDDQ
4
GND
CLK
5
PWRDWN
FBIN
6
7
CLK
VDDQ
FBIN
VDDQ
8
AVDD
9
FBOUT
FBOUT
VDDQ
AGND
VDDQ
10
11
12
13
14
Y1
Y1
Y2
Y2
GND
GND
P0043-02
FUNCTIONAL BLOCK DIAGRAM
3
2
Y0
Y0
12
13
24
9
Y1
Y1
PWRDWN
AVDD
Powerdown
and Test
Logic
17
16
Y2
Y2
26
27
Y3
Y3
19
20
6
7
CLK
CLK
FBOUT
FBOUT
PLL
23
22
FBIN
FBIN
B0196-02
2
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CDCVF855
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SCAS839A–APRIL 2007–REVISED MAY 2007
Table 2. TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AGND
10
–
–
I
Ground for 2.5-V analog supply
2.5-V analog supply
AVDD
9
CLK, CLK
FBIN, FBIN
FBOUT, FBOUT
GND
6, 7
22, 23
19, 20
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
I
O
–
I
1, 5, 14, 15, 28
PWRDWN
VDDQ
24
Output enable for Y and Y
2.5-V supply
4, 8, 11, 18, 21, 25
2, 3
–
O
O
O
O
Y0, Y0
Buffered output copies of input clock, CLK, CLK
Buffered output copies of input clock, CLK, CLK
Buffered output copies of input clock, CLK, CLK
Buffered output copies of input clock, CLK, CLK
Y1, Y1
12, 13
Y2, Y2
16, 17
Y3, Y3
26, 27
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VDDQ, AVDD
Supply voltage range
0.5 V to 3.6 V
–0.5 V to VDDQ + 0.5 V
–0.5 V to VDDQ + 0.5 V
±50 mA
VI
Input voltage range(2)(3)
Output voltage range(2)(3)
Input clamp current
VO
IIK
VI < 0 or VI > VDDQ
VO < 0 or VO > VDDQ
VO = 0 to VDDQ
IOK
IO
IDDS
Tstg
Output clamp current
±50 mA
Continuous output current
Continuous current to GND or VDDQ
Storage temperature range
±50 mA
±100 mA
–65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
(3) This value is limited to 3.6 V maximum.
THERMAL CHARACTERISTICS
R
θJA for TSSOP Package(1)
Airflow
High K
94.4°C/W
82.8°C/W
0 ft/min (0 m/min)
150 ft/min (45.72 m/min)
(1) The package thermal impedance is calculated in accordance with JESD 51.
3
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SCAS839A–APRIL 2007–REVISED MAY 2007
RECOMMENDED OPERATING CONDITIONS
MIN
2.3
NOM
MAX UNIT
VDDQ PC1600 – PC3200
2.7
V
Supply voltage
AVDD
VDDQ – 0.12
2.7
CLK, CLK, FBIN, FBIN
VIL Low-level input voltage
VDDQ/2 – 0.18
V
PWRDWN
–0.3
0.7
CLK, CLK, FBIN, FBIN
VIH High-level input voltage
VDDQ/2 + 0.18
V
V
PWRDWN
1.7
–0.3
0.36
0.25
0.7
VDDQ + 0.3
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
VDDQ + 0.6
VDDQ + 0.6
DC input signal voltage(1)
VDDQ = 2.3 V – 2.7V
VDDQ = 2.425 V – 2.7 V
VDDQ = 2.3 V – 2.7 V
VDDQ = 2.425 V – 2.7 V
DC
AC
CLK, FBIN
CLK, FBIN
VID Differential input signal voltage(2)
V
0.49
Input differential pair cross
VIX
VDDQ/2 – 0.2
VDDQ/2 + 0.2
V
voltage(3)(4)
IOH High-level output current
IOL Low-level output current
SR Input slew rate
–12
12
4
mA
mA
V/ns
°C
1
TA Operating free-air temperature
–40
85
(1) The unused inputs must be held high or low to prevent them from floating.
(2) The dc input signal voltage specifies the allowable dc execution of the differential input.
(3) The differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input
level and VCP is the complementary input level.
(4) The differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must cross.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
VDDQ = 2.3 V, II = –18 mA
MIN TYP
MAX UNIT
VIK
Input voltage, all inputs
–1.2
V
VDDQ = min to max, IOH = –1 mA
VDDQ = 2.3 V, IOH = –12 mA
VDDQ = min to max, IOL = 1 mA
VDDQ = 2.3 V, IOL = 12 mA
VDDQ – 0.1
VOH
High-level output voltage
Low-level output voltage
V
1.7
0.1
0.6
VOL
V
(2)
VOD
VOX
II
Output voltage swing
1.1
VDDQ – 0.4
V
V
Differential outputs are terminated with 120 Ω,
CL = 14 pF (See Figure 3)
Output differential cross-voltage
VDDQ/2 – 0.1 VDDQ/2 VDDQ/2 + 0.1
(3)
Input current
VDDQ = 2.7 V, VI = 0 V to 2.7 V
VDDQ = 2.7 V, VO = VDDQ or GND
±10
±10
µA
µA
High-impedance-state output
current
IOZ
Power-down current on VDDQ
AVDD
+
CLK and CLK = 0 MHz; PWRDWN = Low; Σ of
IDD and AIDD
IDDPD
20
100
µA
fO = 170 MHz
6
8
8
10
AIDD
CI
Supply current on AVDD
Input capacitance
mA
pF
fO = 200 MHz
VDDQ = 2.5 V, VI = VDDQ or GND
2
2.5
3.5
(1) All typical values are at a nominal VDDQ
.
(2) The differential output signal voltage specifies the differential voltage |VTR – VCP|, where VTR is the true output level and VCP is the
complementary output level.
(3) The differential cross-point voltage tracks variations of VDDQ and is the voltage at which the differential signals must cross.
4
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CDCVF855
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SCAS839A–APRIL 2007–REVISED MAY 2007
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating free-air temperature range (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
fO = 170 MHz
fO = 200 MHz
fO = 170 MHz
fO = 200 MHz
fO = 170 MHz
fO = 200 MHz
65
75
80
90
Without load
110
120
130
140
140
mA
150
Differential outputs terminated
with 120 Ω, CL = 0 pF
IDD
Dynamic current on VDDQ
160
170
Differential outputs terminated
with 120 Ω, CL = 14 pF
Part-to-part input capacitance
variation
∆C
VDDQ = 2.5 V, VI = VDDQ or GND
VDDQ = 2.5 V, VI = VDDQ or GND
1
pF
pF
Input capacitance difference
between CLK and CLK, FBIN
and FBIN
CI(∆)
0.25
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature
PARAMETER
MIN
60
MAX
UNIT
Operating clock frequency
220
220
60%
10
fCLK
MHz
Application clock frequency
90
Input clock duty cycle
40%
Stabilization time (PLL mode)(1)
Stabilization time (bypass mode)(2)
µs
30
ns
(1) The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be
obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK and VDD must be applied. Until phase lock is obtained,
the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This
parameter does not apply for input modulation under SSC application.
(2) A recovery time is required when the device goes from power-down mode into bypass mode (AVDD at GND).
5
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SCAS839A–APRIL 2007–REVISED MAY 2007
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Low- to high-level propagation delay
time
(1)
tPLH
Test mode/CLK to any output
Test mode/CLK to any output
3.5
ns
High- to low-level propagation delay
time
(1)
tPHL
3.5
ns
ps
100/133/167 MHz
(PC1600/2100/2700)
–65
–30
65
30
(2)
tjit(per)
Jitter (period), see Figure 7
200 MHz (PC3200)
100/133/167 MHz
(PC1600/2100/2700)
–60
60
(2)
tjit(cc)
Jitter (cycle-to-cycle), see Figure 4
Half-period jitter, see Figure 8
ps
ps
200 MHz (PC3200)
–40
40
100/133/167 MHz
(PC1600/2100/2700)
–100
100
(2)
tjit(hper)
200 MHz (PC3200)
–75
1
75
2
tslr(o)
t(φ)
Output clock slew rate, see Figure 9 Load: 120 Ω, 14 pF
V/ns
ps
Static phase offset, see Figure 5
100/133/167/200 MHz
–50
50
Load: 120 Ω, 14 pF;
100/133/167/200 MHz
tsk(o)
Output skew, see Figure 6
40
ps
(1) Refers to the transition of the noninverting output.
(2) This parameter is assured by design but cannot be 100% production tested.
PARAMETER MEASUREMENT INFORMATION
VDD
VYx
R = 60 W
R = 60 W
VDD/2
VYx
CDCVF855
GND
S0229-02
Figure 1. IBIS Model Output Load
6
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CDCVF855
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SCAS839A–APRIL 2007–REVISED MAY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
V
DD/2
Scope
–VDD/2
C = 14 pF
Z = 60 W
R = 10 W
Z = 50 W
R = 50 W
V(TT)
Z = 60 W
R = 10 W
Z = 50 W
R = 50 W
C = 14 pF
V(TT)
CDCVF855
–VDD/2
–VDD/2
V(TT) = GND
S0230-02
Figure 2. Output Load Test Circuit
VDD
Probe
C = 14 pF
GND
Z = 60 W
C = 1 pF
R = 1 MW
R = 120 W
V(TT)
Z = 60 W
C = 1 pF
R = 1 MW
C = 14 pF
CDCVF855
GND
V(TT)
GND
V(TT) = GND
S0231-02
Figure 3. Output Load Test Circuit for Crossing Point
Yx, FBOUT
Yx, FBOUT
tc(n)
tc(n +1)
tjit(cc) = tc(n) – tc(n+1)
T0174-01
Figure 4. Cycle-to-Cycle Jitter
7
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CDCVF855
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SCAS839A–APRIL 2007–REVISED MAY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
CLK
CLK
FBIN
FBIN
t(f)n
t(f)n+1
S1n = N
t(f)n
t(f)
=
N
(N > 1000 Samples)
T0175-01
Figure 5. Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
tsk(o)
T0176-01
Figure 6. Output Skew
Yx, FBOUT
Yx, FBOUT
tc(n)
Yx, FBOUT
Yx, FBOUT
1
f0
1
tjit(per) = tc(n)
–
f0 = Average Input Frequency Measured at CLK/CLK
f0
T0177-01
Figure 7. Period Jitter
8
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SCAS839A–APRIL 2007–REVISED MAY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Yx, FBOUT
Yx, FBOUT
t(hper_n)
t(hper_n+1)
1
f0
n = Any Half Cycle
1
tjit(hper) = t(hper_n)
–
f0 = Average Input Frequency Measured at CLK/CLK
2´f0
T0178-01
Figure 8. Half-Period Jitter
VOH, VIH
80%
80%
20%
20%
Clock Inputs
and Outputs
VOL, VIL
tr
tf
V80% – V20%
V80% – V20%
tslr(I/O)
=
tslf(I/O) =
tr
tf
T0179-01
Figure 9. Input and Output Slew Rates
Bead(2)
0603
Card
Via
AVDD
VDDQ
4.7 mF
1206
0.1 mF
0603
2200 pF(1)
0603
PLL
GND
AGND
Card
Via
S0232-01
(1) Place the 2200-pF capacitor close to the PLL.
(2) Recommended bead: Fair-Rite P/N 2506036017Y0 or equilvalent (0.8 Ω dc maximum, 600 Ω at 100 MHz).
NOTE: Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect
trace to one GND via (farthest from the PLL).
Figure 10. Recommended AVDD Filtering
9
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PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
PACKAGING INFORMATION
Orderable Device
CDCVF855PW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
28
28
28
28
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CDCVF855PWG4
CDCVF855PWR
CDCVF855PWRG4
TSSOP
TSSOP
TSSOP
PW
PW
PW
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
(mm)
CDCVF855PWR
PW
28
MLA
0
0
7.1
10.4
1.3
12
16 PKGORN
T1TR-MS
P
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
MLA
Length (mm) Width (mm) Height (mm)
CDCVF855PWR
PW
28
342.9
336.6
28.58
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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logic.ti.com
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power.ti.com
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www.ti.com/telephony
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microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
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Video & Imaging
Wireless
www.ti.com/wireless
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