CLC520AD-MLS [TI]
1 CHANNEL, VIDEO AMPLIFIER, CDIP14, SIDE BRAZED PACAKGE-14;
| 型号： | CLC520AD-MLS |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1 CHANNEL, VIDEO AMPLIFIER, CDIP14, SIDE BRAZED PACAKGE-14 放大器 CD |
| 文件： | 总16页 (文件大小：505K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2001
CLC520
Amplifier with Voltage Controlled Gain, AGC +Amp
General Description
Features
n 160MHz, −3dB bandwidth
n 2000V/µsec slew rate
The CLC520 is a wideband DC-coupled amplifier with volt-
age controlled gain (AGC). The amplifier has a high imped-
ance, differential signal input; a high bandwidth, gain control
input; and a single-ended voltage output. Signal channel
performance is outstanding with 160MHz small signal band-
width, 0.5 degree linear phase deviation (to 60MHz) and
0.04% signal nonlinearity at 4VPP output.
n 0.04% signal nonlinearity at 4VPP output
n −43dB feedthrough at 30MHz
n User adjustable gain range
n Differential voltage input and single-ended voltage
output
Gain control is very flexible and easy to use. Maximum gain
may be set over a nominal range of 2 to 100 with one
external resistor. In addition, the gain control input provides
more than 40dB of voltage controlled gain adjustment from
the maximum gain setting. For example, a CLC520 may be
set for a maximum gain of 2 (or 6dB) for a voltage controlled
gain range from 40dB to less than 34dB. Alternatively, the
CLC520 could be set for a maximum gain of 100 or (40dB)
for a voltage controlled gain range from 40dB to less than
0dB.
Applications
n Wide bandwidth AGC systems
n Automatic signal leveling
n Video signal processing
n Voltage controlled filters
n Differential amplifier
n Amplitude modulation
Gain vs. Vg
The gain control bandwidth of 100MHz is superb for AGC/
ALC loop stabilization. And since the gain is minimum with a
zero volt input and maximum with a +2 volt input, driving the
control input is easy.
Finally, the CLC520 differential inputs, and ground refer-
enced voltage output take the trouble out of designing
DC-coupled AGC circuits for display normalizers; signal lev-
eling automatic circuits; etc.
Enhanced Solutions (Military/Aerospace)
SMD Number: 5962-91694
Space level versions also available.
For more information, visit http://www.national.com/mil
01275640
Connection Diagram
01275639
Gain vs. Vg
01275629
Pinout
DIP & SOIC
© 2001 National Semiconductor Corporation
DS012756
www.national.com
Ordering Information
Package
Temperature Range
Industrial
Part Number
Package
Marking
NSC
Drawing
N14A
14-pin plastic DIP
14-pin plastic SOIC
−40˚C to +85˚C
−40˚C to +85˚C
CLC520AJP
CLC520AJE
CLC520AJP
CLC520AJE
M14A
www.national.com
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Junction Temperature
+150˚C
−40˚C to +85˚C
−65˚C to +150˚C
10 sec
Operating Temperature Range
Storage Temperature Range
Lead Solder Duration (+300˚C)
ESD (human body model)
±
7V
Supply Voltage (VCC
IOUT
)
500V
Output is short circuit protected to
ground, but maximum reliability will
be maintained if IOUT does not
exceed...
Operating Ratings
Thermal Resistance
60mA
Package
MDIP
(θJC
)
(θJA)
±
Common Mode Input Voltage
VIN Differential Input Voltage
Vg Differential Input Voltage
Vref Differential Input Voltage
VCC
10V
VCC
VCC
55˚C/W
45˚C/W
105˚C/W
120˚C/W
SOIC
±
±
Electrical Characteristics
±
5V, RL = 100Ω, Rf = 1kΩ, Rg = 182Ω, Vg = +2V; unless specified
AV = +10, VCC
=
Symbol
Parameter
Conditions
CLC520AJ
Typ
Max/Min (Note 2)
Units
Ambient Temperature
Frequency Domain Response
+25˚C
−40˚C
+25˚C
+85˚C
<
>
>
>
>
>
>
>
>
>
SSBW
SSBW
LSBW
-3dB Bandwidth
VOUT 0.5VPP
160
140
140
110
120
100
100
120
100
100
MHz
MHz
MHz
<
VOUT 0.5VPP (AJE only)
90
85
<
VOUT 4.0VPP
<
-3dB Bandwidth
Gain Control Channel
Gain Flatness
Peaking
VOUT 0.5VPP
>
>
>
80
SBWC
VIN = +0.2V, Vg = +1VDC
100
80
80
MHz
<
VOUT 0.5VPP
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
GFPL
GFPH
GFRL
GFRH
LPD
FDTH
TRS
TRL
0.1MHz to 30MHz
0.1MHz to 20MHz
0.1MHz to 30MHz
0.1MHz to 60MHz
0.1MHz to 60MHz
Vg = 0V, VIN = -22dBm
0.5V Step
0
0
0.4
0.7
0.4
1.3
1.2
-31
3.7
0.3
0.5
0.3
0.4
0.7
0.4
1.3
1.2
-31
dB
dB
Peaking
Rolloff
0.1
0.5
0.5
-38
2.5
3.7
12
dB
Rolloff
1
1
dB
Linear Phase Deviation
Feedthrough
Rise and Fall Time
deg
dB
-31
3
5
3
5
ns
4.0V Step
5
ns
±
TS
Settling Time to 0.1%
2.0V Step
18
15
18
15
18
15
ns
OS
Overshoot
0.5V Step
0
%
>
<
<
>
<
<
>
1450
SR
Slew Rate
4V Step
2000
−47
−60
1450
1450
V/µsec
dBc
dBc
<
HD2
HD3
2nd Harmonic Distortion
3rd Harmonic Distortion
Equivalent Output Noise
2VPP, 20MHz
2VPP, 20MHz
(÷10 for input noise) (Note
3)
−40
−50
−40
−50
−35
−45
<
<
<
<
<
<
<
SNF
Noise floor
1MHz to 200MHz
−132
−130
1000
−130
1000
−129
1100
dBm
(1Hz)
µV
INV
DG
DP
Integrated noise
1MHz to 200MHz
at 3.58MHz
800
0.15
0.15
Differential Gain (Note 4)
Differential PIase (Note 4)
%
at 3.58MHz
deg
Static, DC Performance
<
<
<
0.2
SGNL
Integral Signal Nonlinearity
VOUT = 4VPP
0.04
0.1
0.1
%
Gain Accuracy
Rf = 1kΩ, Rg = 182Ω
<
<
<
<
<
<
<
<
±
±
±
±
0.5
GACCU
VOS
For Nominal Max Gain = 20dB
Output Offset Voltage (Note 5)
Average Temperature Coefficient
0
1.0
0.5
dB
mV
40
150
400
120
–
150
300
DVOS
100
µV/˚C
3
www.national.com
Electrical Characteristics (Continued)
±
5V, RL = 100Ω, Rf = 1kΩ, Rg = 182Ω, Vg = +2V; unless specified
AV = +10, VCC
=
Symbol
Parameter
Conditions
Typ
12
100
0.5
5
Max/Min (Note 2)
Units
µA
<
<
<
<
<
>
<
>
<
<
28
IB
Input Bias Current (Note 5)
Average Temperature Doefficient
Input Offset Current
61
28
-
<
165
DIB
415
nA/˚C
µA
<
<
IOS
4
2
2
<
DIOS
PSS
CMRR
ICC
Average Temperature Coefficient
Power Supply Sensitivity
Common Mode Rejection Ratio
Supply Current (Note 5)
VIN Signal Input
40
28
59
38
50
-
20
28
59
38
nA/˚C
mV/V
dB
<
>
<
<
>
<
Output Referred DC
Input Referred
No Load
10
70
28
200
1
28
59
38
mA
kΩ
>
>
RIN
Resistance
100
100
<
<
<
CIN
Capacitance
2
2
2
pF
±
±
250
±
±
DMIR
CMIR
RINC
CINC
VGHI
VGLO
RO
VIN Differential Voltage Range
Common Mode Voltage Range
Vg Control Input
Rg = 182Ω only
280
250
210
mV
V
>
>
>
<
<
>
<
>
±
2
>
<
<
>
<
0.2
>
±
3.2
>
±
50
±
±
±
2.2
750
1
1.4
2
>
Resistance
Capacitance
For Max Gain
For Min Gain
At DC
535
600
600
Ω
<
<
>
2
2
0
2
2
0
2
2
0
pF
Vg Input Voltage
1.6
0.4
0.1
kΩ
V
<
Output Impedance
Output Voltage Range
Output Current
0.3
0.2
Ω
>
>
±
±
±
VO
No Load
3.5
3
3.2
V
>
>
±
±
±
IO
60
35
50
mA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Max/min ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: Measured at A
= 10, V = +2V
g
VMAX
Note 4: Differential gain and phase are measured at: A = +20, V = +2V, R = 150Ω, R = 2kΩ, R = 182Ω, equivalent video signal of 0-100 IRE with 40 IRE
PP
V
g
L
f
g
at 3.58 MHz.
Note 5: AJ-level: spec. is 100% tested at +25˚C.
www.national.com
4
Typical Performance Characteristics
±
(TA = 25˚C, AV = +10, VCC
=
5V, RL = 100Ω, Rf =
1kΩ, Rg = 182Ω, Vg = +2V)
±
±
10
Frequency Response, AVMAX
=
2
Frequency Response, AVMAX
=
01275630
01275616
±
Frequency Response, AVMAX
=
100
Large Signal Frequency Response
01275619
01275621
Small Signal Gain vs. Rf
2nd Harmonic Distortion
01275641
01275601
5
www.national.com
±
5V, RL = 100Ω, Rf = 1kΩ, Rg
Typical Performance Characteristics (TA = 25˚C, AV = +10, VCC
=
= 182Ω, Vg = +2V) (Continued)
3rd Harmonic Distortion
2nd and 3rd Harmonic Distortion vs. Vg
01275603
01275602
Gain vs. Vg
Gain vs. Vg
01275640
01275639
Large and Small Signal Pulse Response
Settling Time, Vg = 2V
01275642
01275613
www.national.com
6
±
5V, RL = 100Ω, Rf = 1kΩ, Rg
Typical Performance Characteristics (TA = 25˚C, AV = +10, VCC
=
= 182Ω, Vg = +2V) (Continued)
Settling Time, Vg = 1.2V
Long-Term Settling Time
01275614
01275615
±
Settling Time vs. Capacitive Load, AVMAX
=
10
Gain Control Settling Time
01275617
01275604
Gain Control Channel Feedthrough
CMRR
01275618
01275605
7
www.national.com
±
5V, RL = 100Ω, Rf = 1kΩ, Rg
Typical Performance Characteristics (TA = 25˚C, AV = +10, VCC
=
= 182Ω, Vg = +2V) (Continued)
Differential Gain and Phase
PSRR
01275643
01275606
Output Noise vs. Vg
Linearity, Vg = 0.6V to 1.6V
01275644
01275622
Linearity, Vg = 0.75V to 1.4V
Linearity, Vg = 0.9V to 1.2V
01275645
01275646
www.national.com
8
Application Information
01275607
FIGURE 1. CLC520 Simplified Schematic
Simplified Circuit Description
A simplified schematic for the CLC520 is given in Figure 1.
+VIN and −VIN are buffered with closed-loop voltage follow-
ers inducing
a signal current in Rg proportional to
(+VIN)−(−VIN), the differential input voltage. This current con-
trols a current source which supplies two well matched tran-
sistors, Q1 and Q2.
01275608
FIGURE 2. CLC520 Typical Application Circuit
The current flowing through Q2 is converted to the final
output voltage using Rf and output amplifier, U1. By chang-
ing the fraction of the signal current I which flows through Q2
the gain is changed. This is done by changing the voltage
applied differentially to the bases of Q1 and Q2. For ex-
ample, with Vg = 0, Q1 is on and Q2 is off. With zero signal
current of flowing through Q2 into Rf, the CLC520 is set to
minimum gain. Conversely, with Vg = 2V, Q1 is off and all of
the signal current I flows through Q2 to Rf producing maxi-
mum gain. With Vg set to 1.1V, the bases of Q1 and Q2 are
set to approximately the same voltage, causing their collec-
tor currents to equally divide the signal current I, and estab-
lish the gain at one half the maximum gain.
Capacitors C1-C6 provide broadband power supply bypass-
ing. C2 and C5 should be tantalum capacitors. All other
capacitors should be high quality ceramic capacitors (CK-05
or equivalent).
Adjusting offset
Offset can be broken into two parts; an input-referred term
and an output-referred term. The input-referred offset shows
up as a variation in output voltage as Vg is changed. This can
be trimmed using the circuit in Figure 3 by placing a low
frequency square wave (VIN = 0 to 2V, into Vg with VIN = 0V,
the input referred Vos term shows up as a small square wave
riding a DC value. Adjust R1 to null the Vos square wave term
to zero. After adjusting the input-referred offset, adjust R2
(with VIN = 0, Vg = 0) until VOUT is zero. Finally, for inverting
applications VIN may be applied to pin 6 and the offset
adjustment to pin 3. This offset trim does not improve output
offset temperature coefficient.
Typical application circuit
Figure 2 illustrates a voltage-controlled gain block offering
broadband performance in a 50Ω system environment. The
input signal is applied to pin 3 of the CLC520 and terminating
resistor R2. Gain control signals are applied to pin 2. The net
gain control port input impedance is 50Ω, set by the parallel
combination of R1 and the 750Ω input impedance of pin 2 of
the CLC520. Rf is set to the standard value, 1kΩ, and Rg
sets the maximum voltage gain to 10V/V. Output impedance
is set by Ro to 50Ω so with 50Ω source and load termina-
tions, the gain is approximately 14dB.
01275628
FIGURE 3. CLC520 Offset Adjustment Circuitry
(other external elements not shown)
Selecting component values
Most applications of the CLC520 adjust the gain to maximize
the VOUT signal. When referred back to the input, this means
9
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capacitance across the feedback resistor should not be used
to compensate for this effect.
Application Information (Continued)
the input signal, signal-to-noise ratio is maximized. The
maximum allowed input amplitude and from system specifi-
cations, using maximum required gain Rf and Rg can be
calculated.
<
For best performance at low maximum gains (AVMAX 10)
Rg+ and Rg connections should be treated in a similar fash-
ion. Capacitance to ground should be minimized by remov-
ing the ground plane from under the resistor of Rg.
The output stage op amp is a current-feedback type amplifier
optimized for Rf = 1kΩ. Rg can then be computed as:
Parasitic or load capacitance directly on the output (pin 10)
degrades phase margin leading to frequency response
peaking. A small series resistor before this capacitance,
effectively reduces this effect (see Settling Time vs. Capaci-
tive Load).
Precision buffed resistors (PRP8351 series from Precision
Resistive Products) must be used for Rf for rated perfor-
mance. Precision buffed resistors are suggested for Rg for
To determine whether the maximum input amplitude will
overdrive the CLC520, compute:
<
low gain settings (AVMAX 10). Carbon composition resis-
tors and RN55D metal-film resistors may be used with re-
duced performance.
Vdmax = (Rg+3.0Ω) · 0.00135
the maximum differential input voltage for linear operation. If
the maximum input amplitude exceeds the above Vdmax limit,
then CLC520 should either be moved to a location in the
signal chain where input amplitudes are reduced, or the
CLC520 gain AVMAX should be reduced or the values for Rg
and Rf should be increased. The overall system performance
impact is different based on the choice made.
Evaluation PC boards (part no. 730021) for the CLC520 are
available.
Predicting the output noise
Seven noise sources (en, in, ii, iio, ino, eno, Ecore) are used to
model the CLC520 noise performance (Figure 4). en, in, and
ii model the equivalent input noise terms for the input buffer
while iio, ino, and eno model the noise terms for the output
buffer. To simplify the model en includes the effect of resistor
Rg (see Figure 5 for en vs. Rg). To simplify the model further,
Rbias is assumed noiseless and its noise contribution is
included in iio.
If the input amplitude is reduced, recompute the impact on
signal-to-noise ratio. If AVMAX is reduced,
An additional term Ecore mimics the active device noise
contribution from the Gilbert multiplier core. Core noise is
theoretically zero when the multiplier is set to maximum gain
>
<
or zero gain (Vg 1.6V or Vg 0.63V respectively at room
temperature) and reaches a maximum of 37nV/ at
VMAX/2.
A
01275647
FIGURE 4. CLC520 Noise Model
Post CLC520 amplifier gain, should be increased, or another
gain stage added to make up for reduced system gain..
To increase Rg and Rf, where Vdmax = (+VIN)−(−VIN) the
largest expected peak differential input voltage. Compute the
lowest acceptable value for Rg:
>
Rg 740 ˚ Vdmax −3Ω
Operating with Rg larger than this value insures linear op-
eration of the input buffers.
Rf may be computed from selected Rg and AVMAX
:
01275648
FIGURE 5. Equivalent Input Noise Voltage (en) vs. Rg
Several points should be made concerning this model. First,
external component noise contributions need to be factored
in when computing total output referred noise. The only
exception is Rg, where its noise contribution is already fac-
tored in. Second, the model ignores flicker noise contribu-
tions. Applications where noise below approximately 100kHz
must be considered should use this model with caution.
Third, this model very accurately predicts output noise volt-
age for the typical application circuit (see above) but accu-
racy will degrade the component values deviate further from
those in the typical application circuit. In general, however,
>
Rf should be = 1kΩ for overall best performance, however
<
Rf 1kΩ can be implemented if necessary using a loop gain
reducing resistor to ground on the inverting summing node of
the output amplifier (see application note QA-13 for details).
Printed Circuit Layout
A good high frequency PCB layout including ground plane
construction and power supply bypassing close to the pack-
age are critical to achieving full performance. The amplifier is
sensitive to stray capacitance to ground at the
Inverting-input (pin12); keep node trace area small. Shunt
www.national.com
10
Application Information (Continued)
the model should predict the equivalent output noise above
the flicker noise region to within a few dB of actual perfor-
mance over the normal range of AVMAX and component
values.
ino does not contribute to the output buffer noise because the
output buffer non-inverting input is grounded.
The core noise is already output referred and is 37nV/
at Vg =1.1 (AVMAX/2) and approaches zero as A goes to 0 or
AVMAX Summing the noise power for each term gives the
total output noise power.
The total output noise voltage is given by:
01275610
FIGURE 6. Typical Circuit
Where AV is the input to output voltage gain, which varies
with Vg.
C accounts for the variation in core noise contribution as Vg
is adjusted. C=1 when gain AV is AVMAX/2. C is zero at
AVMAX and AV = 0 and varies between 0 and 1 for all other
values.
Using these equations, total calculated output noise for the
circuit was 20nV/
mid-gain, and 53nV/
at minimum gain, 49nV/
at maximum gain.
at
01275611
FIGURE 7. Noise Model for Typical Circuit
Calculating CLC520 output noise in a typical circuit
To calculate the noise in a CLC520 application, the noise
terms given for the amplifier as well as the noise terms of the
external components must be included. To clarify the tech-
niques used, output noise in a typical circuit will be calcu-
lated. (Figure 6)
The noise model is depicted in Figure 7. The diagram as-
sumes spot noise source with Vrms
/
and Ampsrms/
units. The Thevenin equivalent of the source and input ter-
mination is used; 25Ω in series with a noise voltage source.
Rg is assumed noiseless since its effect is included in en.
The internal 5kΩ resistor at the CLC520 core output is also
assumed noiseless since its effect is included in iio, The
noise contribution from Rf is modeled as a noise source.
01275612
FIGURE 8. Automatic Gain Control (AGC) Loop
AGC circuits
Figure 8 shows a typical AGC circuit. The CLC520 is fol-
lowed up with a CLC401 for higher overall gain. The output
of the CLC401 is rectified and fed to an inverting integrator
using a CLC420 (wideband voltage feedback op amp).
When the output voltage, VOUT, is too large the integrator
output voltage ramps down reducing the net gain of the
CLC520 and VOUT. If the output voltage is too small, the
integrator ramps up increasing the net gain and the output
voltage. Actual output level is set with R1. To prevent shifts in
DC output voltage with DC changes in input signal level, trim
pot R2 is provided. AGC circuits are always limited in the
range of input signals over which constant output level can
be maintained. In this circuit, we would expect that reason-
able AGC action could be maintained over the gain adjust-
ment range of the CLC520 (at least 40dB). In practice,
rectifier dynamic range limits reduce this slightly.
The easiest way to analyze the output noise of this circuit is
to divide the noise power into three pieces; −input buffer
noise calculation, output buffer noise and core noise. The
input buffer varies with the gain. The output buffer term is
constant. The core noise term is zero at both maximum and
minimum gain and reaches peak at AVMAX/2.
Since we assume all noise terms are uncorrelated, the
equivalent input noise voltage squared is given by:
ii does not contribute to the output buffer noise because the
input buffer inverting input is grounded. en is taken from
Figure 5.
Evaluation Board
The equivalent output buffer noise is given by:
Evaluation PC boards (part number 730029 for through-hole
and 730023 for SOIC) for the CLC520 are available.
11
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Physical Dimensions inches (millimeters)
unless otherwise noted
14-Pin MDIP
NS Package Number N14A
14-Pin SOIC
NS Package Number M14A
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12
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
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Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
See Audio Products
Products > Analog - Amplifiers > Variable Gain Amplifiers > CLC520
CLC520 Product Folder
Amplifier with Voltage Controlled Gain, AGC +Amp
Generic P/N 520
General
Description
Package
& Models
Samples
& Pricing
Design
Tools
Application
Notes
Features
Datasheet
Parametric Table
Parametric Table
Output Current, typ (mA)
Vos, max (Volt)
Signal Channel BW, typ (MHz)
Gain Adjust Range (dB)
160
40
70
.12
Gain Control Interface
Voltage
Input Bias Current, Temp Max (nA)
Voltage Noise, typ (nV/Hz)
HD 2nd, typ (dB)
61000
Analog Control Channel BW (MHz)
Minimum Supply Voltage (Volt)
Maximum Supply Voltage (Volt)
Supply Current, typ (mA)
100
10
60
-47
14
HD 3rd, typ (dB)
-60
28
Diff Gain, typ (dB)
.15
Slew Rate, typ (Volts/usec)
2000
Diff Phase, typ (%)
.15
Special Features
Differential Input
Datasheet
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Date
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18-
May-
01
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CLC520 Amplifier with Voltage Controlled Gain, AGC
+Amp
451
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CLC520 Amplifier with Voltage Controlled Gain, AGC
+Amp (JAPANESE)
254
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90
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CLC520 Mil-Aero Datasheet MNCLC520A-X
If you have trouble printing or viewing PDF file(s), see Printing Problems.
Package Availability, Models, Samples & Pricing
Budgetary
Package
Type Pins MSL
Models
Samples &
Electronic
Orders
Std
Pack
Size
Pricing
$US
each
Package
Part
Status
Number
Marking
SPICE IBIS
Qty
rail
of
55
[logo]¢U¢Z¢2¢T
CLC520
SOIC
NARROW
Lifetime
buy
MSL
MSL
clc520.cir
clc520.cir
CLC520AJE
14
14
N/A
N/A
1K+ $4.9800
1K+ $4.9800
Buy Now
Buy Now
AJE
reel
of
2500
[logo]¢U¢Z¢2¢T
CLC520
SOIC
NARROW
CLC520AJE-
TR13
Lifetime
buy
AJE
[logo]¢Z¢S¢4¢A$E
CLC520AJ-QML
5962-
rail
5962-
9169401MCA
Full
production
CERDIP
MSL
clc520.cir
14
N/A
250+ $33.4000 of
25
9169401MCA
rail
of
N/A
[logo]¢Z¢S¢4¢A
CLC520AD
CLC520AD-
MLS
SIDEBRAZE
CERDIP
MSL
MSL
clc520.cir
clc520.cir
14
14
Preliminary
N/A
N/A
-MLS $E
rail
of
N/A
CLC520AJ-
MLS
Full
production
[logo]¢Z¢S¢4¢A$E
CLC520AJ-MLS
General Description
The CLC520 is a wideband DC-coupled amplifier with voltage controlled gain (AGC). The amplifier has a high
impedance, differential signal input; a high bandwidth, gain control input; and a single-ended voltage output.
Signal channel performance is outstanding with 160MHz small signal bandwidth, 0.5 degree linear phase
deviation (to 60MHz) and 0.04% signal nonlinearity at 4V output.
PP
Gain control is very flexible and easy to use. Maximum gain may be set over a nominal range of 2 to 100
with one external resistor. In addition, the gain control input provides more than 40dB of voltage controlled
gain adjustment from the maximum gain setting. For example, a CLC520 may be set for a maximum gain of
2 (or 6dB) for a voltage controlled gain range from 40dB to less than 34dB. Alternatively, the CLC520 could
be set for a maximum gain of 100 or (40dB) for a voltage controlled gain range from 40dB to less than 0dB.
The gain control bandwidth of 100MHz is superb for AGC/ALC loop stabilization. And since the gain is
minimum with a zero volt input and maximum with a +2 volt input, driving the control input is easy.
Finally, the CLC520 differential inputs, and ground referenced voltage output take the trouble out of
designing DC-coupled AGC circuits for display normalizers; signal leveling automatic circuits; etc.
Enhanced Solutions (Military/Aerospace)
SMD Number: 5962-91694
Space level versions also available.
For more information, visit http://www.national.com/mil
Features
●
●
●
160MHz, -3dB bandwidth
2000V/µsec slew rate
0.04% signal nonlinearity at 4V output
PP
●
●
●
-43dB feedthrough at 30MHz
User adjustable gain range
Differential voltage input and single-ended voltage output
Applications
●
●
●
●
●
●
Wide bandwidth AGC systems
Automatic signal leveling
Video signal processing
Voltage controlled filters
Differential amplifier
Amplitude modulation
Design Tools
Title
Size in Kbytes Date
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Amplifiers Selection Guide
software for Windows
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12-Jun-2002
7 Kbytes
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Application Notes
Size in
Kbytes
Title
Date
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CLC520EB: CLC520EB/CLC522EB
Evaluation Boards
24-Oct-
01
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121 Kbytes
121 Kbytes
193 Kbytes
337 Kbytes
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CLC522EB: CLC520EB/CLC522EB
Evaluation Boards
24-Oct-
01
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Email
OA-16: OA-16 Wideband AGC
Amplifier as a Differential Amplifier
10-Apr-
00
Receive via
Email
OA-18: OA-18 Simulation SPICE
Models for Comlinear's Op Amps
23-May-
00
OA-23: OA-23 CLC522 Advanced
Operating Considerations and Military 250 Kbytes
Specifications
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Email
29-Oct-
99
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[Information as of 5-Aug-2002]
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