CSD13380F3 [TI]
采用 0.6mm x 0.7mm LGA 封装、具有栅极 ESD 保护的单路、76mΩ、12V、N 沟道 NexFET™ 功率 MOSFET;
| 型号： | CSD13380F3 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 0.6mm x 0.7mm LGA 封装、具有栅极 ESD 保护的单路、76mΩ、12V、N 沟道 NexFET™ 功率 MOSFET 栅 开关 晶体管 栅极 |
| 文件： | 总14页 (文件大小：1861K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD13380F3
ZHCSFM0A –OCTOBER 2016 –REVISED FEBRUARY 2022
CSD13380F3 12V N 沟道FemtoFET™ MOSFET
产品概要
1 特性
TA = 25°C
VDS
典型值
单位
12
V
漏源电压
• 低导通电阻
Qg
0.91
0.15
nC
nC
栅极电荷总量(4.5V)
• 超低Qg 和Qgd
• 高漏极工作电流
• 超小尺寸
Qgd
栅极电荷（栅极到漏极）
VGS = 1.8V
96
73
63
– 0.73mm × 0.64mm
• 薄型封装
RDS(on)
VGS = 2.5V
VGS = 4.5V
mΩ
漏源导通电阻
VGS(th)
0.85
V
– 最大厚度为0.36mm
• 集成型ESD 保护二极管
阈值电压
器件信息(1)
介质
– 额定值> 3kV 人体放电模型(HBM)
– 额定值> 2kV 充电器件模型(CDM)
• 无铅且无卤素
器件
数量
封装
配送
CSD13380F3
3000
Femto
0.73mm × 0.64mm
基板栅格阵列(LGA)
卷带
包装
7 英寸卷带
CSD13380F3T
250
• 符合RoHS
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 针对负载开关应用进行了优化
• 针对通用开关应用进行了优化
• 电池应用
绝对最大额定值
TA = 25°C（除非另外注明）
值
12
8
单位
V
VDS
VGS
漏源电压
• 手持式和移动类应用
V
栅源电压
3 说明
持续漏极电流(1)
持续漏极电流(2)
脉冲漏极电流(2) (3)
功率耗散(1)
3.6
ID
A
A
2.1
13.5
1.4
0.5
3
该 63mΩ、12V N 沟道 FemtoFET™ MOSFET 经过设
计和优化，能够最大限度地减小在许多手持式和移动应
用中占用的空间。这项技术能够在替代标准小信号
MOSFET 的同时大幅减小封装尺寸。
IDM
PD
W
功率耗散(2)
人体放电模型(HBM)
充电器件模型(CDM)
。
V(ESD)
kV
°C
2
TJ、
Tstg
–55 至
150
工作结温、
贮存温度
0.36 mm
(1) 覆铜面积最大时的典型RθJA = 90°C/W（在0.06 英寸
(1.52mm) 厚的FR4 PCB 上安装1 平方英寸(6.45cm2)、
2oz、
0.071mm 厚的铜焊盘时）
(2) 覆铜面积最小时的典型RθJA = 255°C/W。
(3) 脉冲持续时间≤100μs，占空比≤1%。
0.73 mm
0.64 mm
典型器件尺寸
G
D
S
.
顶视图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLPS593
CSD13380F3
ZHCSFM0A –OCTOBER 2016 –REVISED FEBRUARY 2022
www.ti.com.cn
Table of Contents
6 Device and Documentation Support..............................7
6.1 Receiving Notification of Documentation Updates......7
6.2 Trademarks.................................................................7
7 Mechanical, Packaging, and Orderable Information....8
7.1 Mechanical Dimensions..............................................8
7.2 Recommended Minimum PCB Layout........................9
7.3 Recommended Stencil Pattern................................... 9
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Specifications.................................................................. 3
5.1 Electrical Characteristics.............................................3
5.2 Thermal Information....................................................3
5.3 Typical MOSFET Characteristics................................4
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (October 2016) to Revision A (February 2022)
Page
• 将超薄型封装要点中的厚度从0.35mm 更改为0.36mm..................................................................................... 1
• 将超薄型封装图片中的厚度从0.35mm 更新为0.36mm..................................................................................... 1
• Changed ultra-low profile image height from 0.35 mm to 0.36 mm....................................................................8
• Added FemtoFET Surface Mount Guide note.................................................................................................... 9
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5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage
12
V
nA
nA
V
VGS = 0 V, IDS = 250 μA
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
VGS = 0 V, VDS = 9.6 V
VDS = 0 V, VGS = 8 V
50
25
IGSS
VGS(th)
0.55
0.85
96
1.30
135
92
VDS = VGS, IDS = 250 μA
VGS = 1.8 V, IDS = 0.1 A
VGS = 2.5 V, IDS = 0.4 A
VGS = 4.5 V, IDS = 0.4 A
VDS = 1.2 V, IDS = 0.4 A
RDS(on)
Drain-to-source on resistance
Transconductance
73
mΩ
63
76
gfs
4.3
S
DYNAMIC CHARACTERISTICS
Ciss
Coss
Crss
RG
Input capacitance
120
81
156
105
pF
pF
pF
VGS = 0 V, VDS = 6 V,
ƒ= 1 MHz
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
9.6
16
12.5
Ω
Qg
0.91
0.15
0.19
0.15
0.81
4
1.2
nC
nC
nC
nC
nC
ns
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
VDS = 6 V, IDS = 0.4 A
VDS = 6 V, VGS = 0 V
Turnon delay time
Rise time
4
ns
VDS = 6 V, VGS = 4.5 V,
IDS = 0.4 A, RG = 2 Ω
td(off)
tf
Turnoff delay time
Fall time
11
ns
3
ns
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
ISD = 0.4 A, VGS = 0 V
0.71
2.1
8
1
V
nC
ns
VDS= 6 V, IF = 0.4 A, di/dt = 100 A/μs
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-ambient thermal resistance(1)
Junction-to-ambient thermal resistance(2)
MIN
TYP
MAX
UNIT
90
RθJA
°C/W
255
(1) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
(2) Device mounted on FR4 material with minimum Cu mounting area.
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5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
5
4.5
4
10
9
8
7
6
5
4
3
2
1
0
3.5
3
2.5
2
1.5
1
TC = 125°C
TC = 25°C
VGS = 1.8 V
VGS = 2.5 V
VGS = 4.5 V
0.5
TC = -55°C
0
0
0.2
0.4
0.6
0.8
1
1.2
VGS - Gate-to-Source Voltage (V)
1.4
1.6
1.8
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VDS - Drain-to-Source Voltage (V)
1
D003
D002
图5-1. Transient Thermal Impedance
图5-2. Saturation Characteristics
VDS = 5 V
图5-3. Transfer Characteristics
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1000
100
10
4.5
4
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
3.5
3
2.5
2
1.5
1
0.5
1
0
0
0
2
4
6
8
VDS - Drain-to-Source Voltage (V)
10
12
0.1
0.2
0.3
0.4
0.5
0.6
Qg - Gate Charge (nC)
0.7
0.8
0.9
D005
D004
图5-5. Capacitance
VDS = 6 V
ID = 0.4 A
图5-4. Gate Charge
1.15
1.05
0.95
0.85
0.75
0.65
0.55
0.45
200
180
160
140
120
100
80
TC = 25°C, ID = 0.4 A
TC = 125°C, ID = 0.4 A
60
40
20
0
-75 -50 -25
0
25
50
TC - Case Temperature (°C)
75 100 125 150 175
0
1
2
3
4
5
6
VGS - Gate-to-Source Voltage (V)
7
8
D006
D007
ID = 250 µA
图5-7. On-State Resistance vs Gate-to-Source
Voltage
图5-6. Threshold Voltage vs Temperature
10
1.5
TC = -55°C
TC = -40°C
TC = 25°C
TC = 125°C
TC = 150°C
VGS = 1.8 V
VGS = 4.5 V
1.4
1.3
1.2
1.1
1
1
0.1
0.01
0.9
0.8
0.7
0.001
0.0001
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VSD - Source-to-Drain Voltage (V)
1
-75 -50 -25
0
25
50
TC - Case Temperature (°C)
75 100 125 150 175
D009
D008
图5-9. Typical Diode Forward Voltage
ID = 0.4A
图5-8. Normalized On-State Resistance vs
Temperature
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100
10
1
10
TC = 25èC
TC = 125èC
100 ms
10 ms
1 ms
100 µs
0.1
0.1
1
0.01
1
10
VDS - Drain-to-Source Voltage (V)
100
0.1
TAV - Time in Avalanche (ms)
1
D010
D011
Single pulse, typical RθJA = 255°C/W (min Cu)
图5-11. Single Pulse Unclamped Inductive
Switching
图5-10. Maximum Safe Operating Area
3
2.5
2
1.5
1
0.5
0
-50
-25
0
25
50
TA - Ambient Temperature (°C)
75
100 125 150 175
D012
Typical RθJA = 255°C/W (min Cu)
图5-12. Maximum Drain Current vs Temperature
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6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Trademarks
FemtoFET™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Mechanical Dimensions
0.73
B
A
0.65
PIN 1 INDEX AREA
0.64
0.56
0.36 MAX
C
SEATING PLANE
0.4
0.225
2
3
0.175
0.51
0.35
0.49
1
0.16
2X
0.14
0.16
0.14
0.015
C B
A
0.015
C A
B
0.26
2X
0.24
A. All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994).
B. This drawing is subject to change without notice.
C. This package is a PB-free solder land design.
表7-1. Pin Configuration
POSITION
DESIGNATION
Pin 1
Gate
Pin 2
Source
Pin 3
Drain
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7.2 Recommended Minimum PCB Layout
(0.15)
2X (0.25)
0.05 MIN
ALL AROUND
TYP
2X (0.15)
1
3
SYMM
(0.35)
(0.5)
2
(R0.05) TYP
SOLDER MASK
OPENING
TYP
PKG
(0.4)
METAL UNDER
SOLDER MASK
TYP
(0.175)
A. All dimensions are in millimeters.
A. For more information, see FemtoFET Surface Mount Guide (SLRA003D).
7.3 Recommended Stencil Pattern
2X (0.25)
(0.15)
2X (0.2)
1
3
SYMM
(0.4)
(0.5)
2
2X (0.15)
(R0.05) TYP
PKG
2X SOLDER MASK EDGE
(0.175)
(0.4)
A. All dimensions are in millimeters.
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PACKAGE OPTION ADDENDUM
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11-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CSD13380F3
ACTIVE
ACTIVE
PICOSTAR
PICOSTAR
YJM
YJM
3
3
3000 RoHS & Green
250 RoHS & Green
NIAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
D
D
CSD13380F3T
NIAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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11-Jan-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD13380F3
CSD13380F3
CSD13380F3T
CSD13380F3T
PICOST
AR
YJM
YJM
YJM
YJM
3
3
3
3
3000
3000
250
178.0
180.0
180.0
178.0
8.4
8.4
8.4
8.4
0.7
0.7
0.7
0.7
0.79
0.79
0.79
0.79
0.44
0.44
0.44
0.44
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
PICOST
AR
PICOST
AR
PICOST
AR
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CSD13380F3
CSD13380F3
CSD13380F3T
CSD13380F3T
PICOSTAR
PICOSTAR
PICOSTAR
PICOSTAR
YJM
YJM
YJM
YJM
3
3
3
3
3000
3000
250
220.0
182.0
182.0
220.0
220.0
182.0
182.0
220.0
35.0
20.0
20.0
35.0
250
Pack Materials-Page 2
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CDIL
CSD1468Q
Small Signal Bipolar Transistor, 1A I(C), 1-Element, NPN, Silicon, TO-92, PLASTIC, TO-92, 3 PIN
CDIL
CSD1468R
Small Signal Bipolar Transistor, 1A I(C), 1-Element, NPN, Silicon, TO-92, PLASTIC, TO-92, 3 PIN
CDIL
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