CSD18510KTTT [TI]
采用 D2PAK 封装的单路、1.7mΩ、40V、N 沟道 NexFET™ 功率 MOSFET | KTT | 3 | -55 to 175;
| 型号： | CSD18510KTTT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 D2PAK 封装的单路、1.7mΩ、40V、N 沟道 NexFET™ 功率 MOSFET | KTT | 3 | -55 to 175 局域网 开关 脉冲 晶体管 |
| 文件： | 总13页 (文件大小：1248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD18510KTT
ZHCSFX7B –NOVEMBER 2016 –REVISED NOVEMBER 2022
CSD18510KTT 40V N 通道NexFETTM 功率MOSFET
产品概要
1 特性
TA = 25°C
典型值
单位
VDS
Qg
40
V
漏源电压
• 超低Qg 和Qgd
• 低热阻
• 雪崩级
• 无铅端子镀层
• 符合RoHS
• 无卤素
• D2PAK 塑料封装
119
21
nC
nC
栅极电荷总量(10V)
Qgd
栅极电荷（栅极到漏极）
漏源导通电阻
VGS = 4.5V
VGS = 10V
1.7
2.0
1.4
RDS(on)
VGS(th)
mΩ
V
阈值电压
器件信息(1)
介质
2 应用
器件
数量
500
50
封装
配送
D2PAK
塑料封装
CSD18510KTT
CSD18510KTTT
卷带包
装
• 次级侧同步整流器
• 电机控制
13 英寸卷带
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
3 说明
这款 40V、1.4mΩ、D2PAK (TO-263) NexFET™ 功率
MOSFET 旨在用于更大限度地降低功率转换应用中的
损耗。
绝对最大额定值
TA = 25°C
值
40
单位
V
VDS
VGS
漏源电压
Drain (Pin 2)
±20
V
栅源电压
200
274
持续漏极电流（受封装限制）
持续漏极电流（受芯片限制），TC = 25°C 时
测得
ID
A
持续漏极电流（受芯片限制），TC = 100°C 时
测得
193
Gate
(Pin 1)
脉冲漏极电流(1)
功率耗散
IDM
PD
400
250
A
W
TJ、
Tstg
工作结温、
贮存温度
°C
-55 至175
Source (Pin 3)
雪崩能量，单脉冲
ID = 81A，L = 0.1mH，RG = 25Ω
EAS
328
mJ
(1) 最大RθJC = 0.6°C/W，脉冲持续时间≤100μs，占空比≤
1%。
8
10
TC = 25°C, ID = 100 A
TC = 125°C, ID = 100 A
ID = 100 A, VDS = 20 V
9
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
0
2
4
6
VGS - Gate-to-Source Voltage (V)
8
10
12
14
16
18
20
0
20
40
Qg - Gate Charge (nC)
60
80
100
120
D007
D004
R
DS(on) 与VGS 之间的关系
栅极电荷
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLPS638
CSD18510KTT
ZHCSFX7B –NOVEMBER 2016 –REVISED NOVEMBER 2022
www.ti.com.cn
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Specifications.................................................................. 3
5.1 Electrical Characteristics.............................................3
5.2 Thermal Information....................................................3
5.3 Typical MOSFET Characteristics................................4
6 器件和文档支持................................................................. 7
6.1 接收文档更新通知....................................................... 7
6.2 支持资源......................................................................7
6.3 Trademarks.................................................................7
6.4 Electrostatic Discharge Caution..................................7
6.5 术语表......................................................................... 7
7 Mechanical, Packaging, and Orderable Information....8
7.1 KTT Package Dimensions.......................................... 8
7.2 Recommended PCB Pattern.......................................9
7.3 Recommended Stencil Opening (0.125 mm
Stencil Thickness)......................................................... 9
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (January 2017) to Revision B (November 2022)
Page
• Updated 图5-3 .................................................................................................................................................. 4
Changes from Revision * (November 2016) to Revision A (January 2017)
Page
• 在绝对最大额定值表中将TC = 25°C 时的芯片电流限制从237A 更改为274A..................................................1
• 在绝对最大额定值表中将TC = 100°C 时的芯片电流限制从167A 更改为193A................................................1
• 在绝对最大额定值表中将最大功耗从188W 更改为250W.................................................................................1
• Changed the charge values in the Dynamic Characteristics section of the Electrical Characteristics table.......3
• Changed max RθJC from 0.8°C/W : to 0.6°C/W in the Thermal Information table.............................................3
• Changed 图5-4 in the Typical MOSFET Characteristics section to reflect updated gate charges.....................4
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5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage
40
V
VGS = 0 V, ID = 250 μA
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
VGS = 0 V, VDS = 32 V
VDS = 0 V, VGS = 20 V
VDS = VGS, ID = 250 μA
VGS = 4.5 V, ID = 100 A
VGS = 10 V, ID = 100 A
VDS = 4 V, ID = 100 A
1
100
2.3
2.6
1.7
μA
nA
V
IGSS
VGS(th)
1.4
1.7
2.0
1.4
330
RDS(on)
gfs
Drain-to-source on resistance
Transconductance
mΩ
S
DYNAMIC CHARACTERISTICS
Ciss
Coss
Crss
RG
Input capacitance
8770 11400
pF
pF
pF
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge total (10 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
832
424
0.9
58
118
21
28
15
35
10
8
1080
551
1.8
VGS = 0 V, VDS = 20 V, ƒ= 1 MHz
Ω
Qg
75
nC
nC
nC
nC
nC
nC
ns
Qg
153
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
VDS = 20 V, ID = 100 A
VDS = 20 V, VGS = 0 V
Turnon delay time
Rise time
ns
VDS = 20 V, VGS = 10 V,
IDS = 100 A, RG = 0 Ω
td(off)
tf
Turnoff delay time
29
8
ns
Fall time
ns
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
ISD = 100 A, VGS = 0 V
0.85
70
1.0
V
nC
ns
VDS= 20 V, IF = 100 A,
di/dt = 300 A/μs
41
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-case thermal resistance
Junction-to-ambient thermal resistance
MIN
TYP
MAX UNIT
0.6 °C/W
62 °C/W
RθJC
RθJA
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5.3 Typical MOSFET Characteristics
TA =25°C (unless otherwise stated)
图5-1. Transient Thermal Impedance
200
180
160
140
120
100
80
200
180
160
140
120
100
80
60
60
40
40
VGS = 4.5 V
VGS = 6 V
VGS = 10 V
TC = 125°C
TC = 25°C
TC = -55°C
20
20
0
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
VDS - Drain-to-Source Voltage (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
D002
D003
图5-2. Saturation Characteristics
VDS = 5 V
图5-3. Transfer Characteristics
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5.3 Typical MOSFET Characteristics (continued)
TA =25°C (unless otherwise stated)
100000
10000
1000
10
9
8
7
6
5
4
3
2
1
0
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
100
0
4
8
12
16
20
24
28
VDS - Drain-to-Source Voltage (V)
32
36
40
0
20
40
60
80
Qg - Gate Charge (nC)
100
120
D005
D004
图5-5. Capacitance
VDS = 20 V
ID = 100 A
图5-4. Gate Charge
2.3
8
7
6
5
4
3
2
1
TC = 25°C, ID = 100 A
TC = 125°C, ID = 100 A
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.3
0
0
-75 -50 -25
0
25 50 75 100 125 150 175 200
TC - Case Temperature (°C)
2
4
6
8
10
12
14
VGS - Gate-to-Source Voltage (V)
16
18
20
D01026
D007
ID = 250 µA
图5-7. On-State Resistance vs Gate-to-Source Voltage
图5-6. Threshold Voltage vs Temperature
100
2.2
2
TC = 25°C
TC = 125°C
10
VGS = 4.5 V
VGS = 10 V
1.8
1.6
1.4
1.2
1
1
0.1
0.01
0.8
0.6
0.4
0.001
0.0001
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VSD - Source-to-Drain Voltage (V)
1
-75 -50 -25
0
25 50 75 100 125 150 175 200
TC - Case Temperature (°C)
D009
D008
图5-9. Typical Diode Forward Voltage
ID = 100 A
图5-8. Normalized On-State Resistance vs Temperature
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5.3 Typical MOSFET Characteristics (continued)
TA =25°C (unless otherwise stated)
1000
100
10
1
100
10
1
DC
10 ms
1 ms
100 µs
10 µs
TC = 25èC
TC = 125èC
0.1
0.1
1
10
VDS - Drain-to-Source Voltage (V)
100
0.01
0.1
TAV - Time in Avalanche (ms)
1
D010
D011
Single pulse, max RθJC = 0.6°C/W
图5-10. Maximum Safe Operating Area
240
图5-11. Single Pulse Unclamped Inductive Switching
200
160
120
80
40
0
-50 -25
0
25
50
TC - Case Temperature (°C)
75 100 125 150 175 200
D012
Max RθJC = 0.6°C/W
图5-12. Maximum Drain Current vs Temperature
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6 器件和文档支持
6.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
6.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
6.3 Trademarks
NexFET™, TI E2E™, and PowerPAD™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
6.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
6.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 KTT Package Dimensions
15.5
14.7
9.25
9.05
A
B
3
10.26
10.06
2X 5.08
2
1
1.36
1.23
2[.0]X
0.9
2[.0]X
1.75 MAX
0.77
0.25
C
A
B
1.4
1.17
0.47
0.34
4.7
4.4
8
0
C
0.25
0
1.32
1.22
2.6
2
0.25
GAGE PLANE
7.48
7.08
8°
0°
8.55
8.15
2.6
2
0.25
GAGE PLANE
OPTIONAL LEAD FORM
EXPOSED
THERMAL PAD
NOTE 3
Notes:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Features may not exist and shape may vary per different assembly sites.
表7-1. Pin Configuration
POSITION
DESIGNATION
Pin 1
Gate
Pin 2 / Tab
Pin 3
Drain
Source
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7.2 Recommended PCB Pattern
PKG
(3.4)
(6.9)
(R0.05) TYP
PKG
SYMM
(5.08)
(8.55)
2X (1.05)
2X (3.82)
(7.48)
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques
(SLPA005).
7.3 Recommended Stencil Opening (0.125 mm Stencil Thickness)
(1.17) TYP
42X (0.97)
(0.48) TYP
2X (3.82)
2X (1.05)
42X (0.95)
(R0.05) TYP
(1.15) TYP
SYMM
(5.08)
(6.9)
PKG
Notes:
1. This package is designed to be soldered to a thermal pad on the board. See PowerPAD™ Thermally
Enhanced Package (SLMA002) and PowerPADTM Made Easy (SLMA004) for more information.
2. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
3. Board assembly site may have different recommendations for stencil design.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
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证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
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TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
500
50
(1)
(2)
(3)
(4/5)
(6)
CSD18510KTT
CSD18510KTTT
ACTIVE
DDPAK/
TO-263
KTT
3
3
RoHS-Exempt
& Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 175
-55 to 175
CSD18510KTT
CSD18510KTT
ACTIVE
DDPAK/
TO-263
KTT
RoHS-Exempt
& Green
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2021
Addendum-Page 2
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