CSD18510Q5B [TI]
采用 5mm x 6mm SON 封装的单路、0.96mΩ、40V、N 沟道 NexFET™ 功率 MOSFET;
| 型号： | CSD18510Q5B |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 5mm x 6mm SON 封装的单路、0.96mΩ、40V、N 沟道 NexFET™ 功率 MOSFET |
| 文件： | 总14页 (文件大小：791K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CSD18510Q5B
ZHCSG53 –MARCH 2017
CSD18510Q5B N 通道 NexFET™功率金属氧化物半导体场效应晶体管
(MOSFET)
1 特性
产品概要
1
•
低 RDS(ON)
TA=25°C
VDS
典型值
40
单位
V
•
•
•
•
•
•
•
低热阻
漏源电压
雪崩额定值
Qg
栅极电荷总量 (10V)
118
21
nC
nC
逻辑电平
Qgd
栅极电荷（栅极到漏极）
VGS = 4.5V
VGS = 10V
1.7
1.2
无铅引脚镀层
RDS(on) 漏源导通电阻
VGS(th) 阈值电压
mΩ
0.79
符合 RoHS 环保标准
V
无卤素
小外形尺寸无引线 (SON) 5mm x 6mm 塑料封装
器件信息(1)
器件
数量
2500 13 英寸卷带
250 7 英寸卷带
包装介质
封装
运输
2 应用范围
CSD18510Q5B
CSD18510Q5BT
5.00mm × 6.00mm
SON 塑料封装
卷带封
装
•
•
•
直流 - 直流转换
次级侧同步整流器
电机控制
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
绝对最大额定值
TA = 25°C
值
40
单位
V
3 说明
VDS 漏源电压
VGS 栅源电压
这款采用 5mm × 6mm SON 封装的 40V、0.79mΩ、
NexFET™功率 MOSFET 的设计旨在追求以最大限度
降低功率转换应用中的功率 损耗。
±20
100
V
持续漏极电流（受封装限制）
持续漏极电流（受芯片限制），TC = 25°C 时
测得
ID
300
A
俯视图
持续漏极电流(1)
42
400
3.1
IDM
PD
脉冲漏极电流，TA = 25°C 时测得(2)
功率耗散(1)
A
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
W
功率耗散，TC = 25°C
156
TJ， 工作结温，
-55 至 150
°C
Tstg
储存温度
雪崩能量，单一脉冲
ID = 81，L = 0.1mH，RG = 25Ω
EAS
328
mJ
(1) RθJA = 40°C/W，这是在一块厚度为 0.06 英寸环氧树脂 (FR4)
印刷电路板 (PCB) 上的 1 英寸2，2 盎司铜焊盘上测得的典型
值。
D
D
(2) 最大 RθJC = 0.8°C/W，脉冲持续时间 ≤ 100μs，占空比 ≤ 1%。
P0093-01
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLPS632
CSD18510Q5B
ZHCSG53 –MARCH 2017
www.ti.com.cn
RDS(on) 与 VGS 间的关系
栅极电荷
10
9
8
7
6
5
4
3
2
1
0
5
4.5
4
ID = 32 A
VDS = 20 V
TC = 25°C, I D = 32 A
TC = 125°C, I D = 32 A
3.5
3
2.5
2
1.5
1
0.5
0
0
10 20 30 40 50 60 70 80 90 100 110 120
Qg - Gate Charge (nC)
0
2
4
6
8
10
12
14
16
18
20
VGS - Gate-to-Source Voltage (V)
D004
D007
2
版权 © 2017, Texas Instruments Incorporated
CSD18510Q5B
www.ti.com.cn
ZHCSG53 –MARCH 2017
目录
6.1 接收文档更新通知 ..................................................... 8
6.2 社区资源.................................................................... 8
6.3 商标........................................................................... 8
6.4 静电放电警告............................................................. 8
6.5 Glossary.................................................................... 8
机械、封装和可订购信息 ......................................... 9
7.1 Q5B 封装尺寸............................................................ 9
7.2 建议 PCB 布局 ........................................................ 10
7.3 建议模板布局........................................................... 10
7.4 Q5B 卷带信息.......................................................... 11
1
2
3
4
5
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 3
Specifications......................................................... 4
5.1 Electrical Characteristics........................................... 4
5.2 Thermal Information.................................................. 4
5.3 Typical MOSFET Characteristics.............................. 5
器件和文档支持........................................................ 8
7
6
4 修订历史记录
日期
修订版本
注释
2017 年 3 月
*
最初发布。
版权 © 2017, Texas Instruments Incorporated
3
CSD18510Q5B
ZHCSG53 –MARCH 2017
www.ti.com.cn
5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage
VGS = 0 V, ID = 250 μA
40
V
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
VGS = 0 V, VDS = 32 V
VDS = 0 V, VGS = 20 V
VDS = VGS, ID = 250 μA
VGS = 4.5 V, ID = 32 A
VGS = 10 V, ID = 32 A
VDS = 4 V, ID = 32 A
1
100
2.3
μA
nA
V
IGSS
VGS(th)
1.2
1.7
1.2
1.6
RDS(on)
gfs
Drain-to-source on resistance
Transconductance
mΩ
0.79
147
0.96
S
DYNAMIC CHARACTERISTICS
Ciss
Coss
Crss
RG
Input capacitance
8770 11400
pF
pF
pF
Ω
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge total (10 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
VGS = 0 V, VDS = 20 V, ƒ = 1 MHz
832
424
0.9
58
118
21
28
15
35
8
1080
551
1.8
Qg
75
nC
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qg
153
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
VDS = 20 V, ID = 32 A
VDS = 20 V, VGS = 0 V
Turnon delay time
Rise time
17
44
15
VDS = 20 V, VGS = 10 V,
IDS = 32 A, RG = 0 Ω
td(off)
tf
Turnoff delay time
Fall time
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
ISD = 32 A, VGS = 0 V
0.8
31
19
1.0
V
nC
ns
VDS= 20 V, IF = 32 A,
di/dt = 300 A/μs
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-case thermal resistance(1)
Junction-to-ambient thermal resistance(1)(2)
MIN
TYP
MAX
UNIT
°C/W
°C/W
RθJC
RθJA
0.8
50
(1)
R
θJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in (3.81-cm × 3.81-
cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
4
Copyright © 2017, Texas Instruments Incorporated
CSD18510Q5B
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ZHCSG53 –MARCH 2017
GATE
Source
GATE
Source
Max RθJA = 50°C/W
when mounted on 1 in2
(6.45 cm2) of
2-oz (0.071-mm) thick
Cu.
Max RθJA = 125°C/W
when mounted on a
minimum pad area of
2-oz (0.071-mm) thick
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
Figure 1. Transient Thermal Impedance
Copyright © 2017, Texas Instruments Incorporated
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Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
200
200
175
150
125
100
75
TC = 125°C
TC = 25°C
TC = -55°C
175
150
125
100
75
50
50
VGS = 4.5 V
VGS = 6 V
25
25
VGS = 10 V
0
0
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35 0.4
1
1.5
2
2.5
3
3.5
4
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
D002
D003
VDS = 5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
100000
10000
1000
10
9
8
7
6
5
4
3
2
1
0
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
100
0
10
20
30
40
0
10 20 30 40 50 60 70 80 90 100 110 120
Qg - Gate Charge (nC)
VDS - Drain-to-Source Voltage (V)
D005
D004
ID = 32 A
VDS = 20 V
Figure 5. Capacitance
Figure 4. Gate Charge
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
5
4.5
4
TC = 25°C, I D = 32 A
TC = 125°C, I D = 32 A
3.5
3
2.5
2
1.5
1
0.5
0
0
-75 -50 -25
0
25
50
75 100 125 150 175
2
4
6
8
10
12
14
16
18
20
TC - Case Temperature (°C)
VGS - Gate-to-Source Voltage (V)
D006
D007
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
6
Copyright © 2017, Texas Instruments Incorporated
CSD18510Q5B
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ZHCSG53 –MARCH 2017
Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
100
10
2
TC = 25°C
TC = 125°C
VGS = 4.5 V
VGS = 10 V
1.8
1.6
1.4
1.2
1
1
0.1
0.01
0.001
0.0001
0.8
0.6
0.4
-75 -50 -25
0
25
50
75 100 125 150 175
0
0.2
0.4
0.6
0.8
1
TC - Case Temperature (°C)
VSD - Source-to-Drain Voltage (V)
D008
D009
ID = 32 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
1000
100
100
10
1
DC
10 ms
1 ms
100 µs
10 µs
TC = 25èC
TC = 125èC
0.1
0.1
10
0.01
1
10
100
0.1
1
VDS - Drain-to-Source Voltage (V)
TAV - Time in Avalanche (ms)
D010
D011
Single pulse, max RθJC = 0.8°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
120
100
80
60
40
20
0
-50
-25
0
25
50
75
100 125 150 175
TC - Case Temperature (°C)
D012
Figure 12. Maximum Drain Current vs Temperature
Copyright © 2017, Texas Instruments Incorporated
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6 器件和文档支持
6.1 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
6.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.3 商标
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
6.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
8
版权 © 2017, Texas Instruments Incorporated
CSD18510Q5B
www.ti.com.cn
ZHCSG53 –MARCH 2017
7 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。要获得这份数据表的浏览器版本，请查阅左侧的导航栏。
7.1 Q5B 封装尺寸
K
c1
H
L
E1
•
d1
d2
Top View
Side View
Bottom View
•
Front View
毫米
DIM
最小值
0.80
0.36
0.15
0.15
0.20
4.90
4.12
3.90
0.20
标称值
最大值
1.05
0.46
0.25
0.25
0.30
5.10
4.32
4.10
0.30
A
b
1.00
0.41
0.20
0.20
0.25
5.00
4.22
4.00
0.25
c
c1
c2
D1
D2
D3
d
d1
d2
E
0.085 典型值
1.27 典型值
1.40 典型值
0.319
4.90
5.90
3.48
0.369
5.00
6.00
3.58
0.419
5.10
6.10
3.68
E1
E2
e
H
0.36
0.46
0.57
0°
0.46
0.56
0.67
—
0.56
0.66
0.77
—
L
L1
θ
K
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ZHCSG53 –MARCH 2017
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7.2 建议 PCB 布局
有关针对
PCB
设计的建议电路布局布线，请参见《通过
PCB
布局布线技巧来减少振铃》（文献编
号：SLPA005）。
7.3 建议模板布局
(0.020)
(0.014)
0.350
0.508
x4
(0.022)
0.562 x 4
(0.029)
0.746 x 8
(0.011)
0.286
(0.086)
(0.050)
2.186
1.270
4.318
(0.170)
0.300
(0.012)
(0.050)
1.270
(0.051)
1.294
x 8
(0.030)
0.766
(0.060)
1.525
(0.042)
1.072
(0.259)
6.586
10
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CSD18510Q5B
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ZHCSG53 –MARCH 2017
7.4 Q5B 卷带信息
K0
4.00 0.10 ꢀ(SS ꢁNoS 1ꢂ
0.30 0.05
2.00 0.05
+0.10
–0.00
Ø 1.50
B0
A0
8.00 0.10
R 0.30 MAX
Ø 1.50 MIꢁ
R 0.30 TYP
A0 = 6.50 0.10
B0 = 5.30 0.10
K0 = 1.40 0.10
M0138-01
注释：
1. 10 链齿孔距累积容差 ±0.2。
2. 每 100mm 长度的翘曲不能超过 1mm，在 250mm 长度上不累积。
3. 材料：黑色抗静电聚苯乙烯。
4. 全部尺寸单位为 mm（除非另外注明）
5. 高于孔眼底部 0.3mm 的平面上测量得到 A0 和 B0 值.
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11
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
250
(1)
(2)
(3)
(4/5)
(6)
CSD18510Q5B
CSD18510Q5BT
ACTIVE
VSON-CLIP
VSON-CLIP
DNK
8
8
RoHS-Exempt
& Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
CSD18510
CSD18510
ACTIVE
DNK
RoHS-Exempt
& Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
Addendum-Page 2
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