CSD18537NQ5AT [TI]
采用 5mm x 6mm SON 封装的单路、13mΩ、60V、N 沟道 NexFET™ 功率 MOSFET | DQJ | 8 | -55 to 150;
| 型号： | CSD18537NQ5AT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 5mm x 6mm SON 封装的单路、13mΩ、60V、N 沟道 NexFET™ 功率 MOSFET | DQJ | 8 | -55 to 150 局域网 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总12页 (文件大小：1361K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD18537NQ5A
www.ti.com
SLPS391 –JUNE 2013
60-V N-Channel NexFET™ Power MOSFETs
Check for Samples: CSD18537NQ5A
1
FEATURES
PRODUCT SUMMARY
2
•
•
•
•
•
•
•
Ultra Low Qg and Qgd
Low Thermal Resistance
Avalanche Rated
TA = 25°C
VDS
TYPICAL VALUE
UNIT
V
Drain to Source Voltage
Gate Charge Total (10V)
Gate Charge Gate to Drain
60
14
Qg
nC
nC
mΩ
mΩ
V
Qgd
2.3
Pb Free Terminal Plating
RoHS Compliant
VGS = 6V
13
10
RDS(on) Drain to Source On Resistance
VGS(th) Threshold Voltage
VGS = 10V
Halogen Free
3.0
SON 5-mm × 6-mm Plastic Package
ORDERING INFORMATION
APPLICATIONS
Device
Package
Media
Qty
Ship
•
•
High Side Synchronous Buck Converter
Motor Control
SON 5-mm × 6-mm
Plastic Package
13-Inch
Reel
Tape and
Reel
CSD18537NQ5A
2500
ABSOLUTE MAXIMUM RATINGS
DESCRIPTION
The NexFET™ power MOSFET has been designed
to minimize losses in power conversion applications.
TA = 25°C
VALUE
UNIT
V
VDS
VGS
Drain to Source Voltage
60
Gate to Source Voltage
±20
V
Top View
Continuous Drain Current (Package limited),
TC = 25°C
50
62
ID
Continuous Drain Current (Silicon limited),
TC = 25°C
Continuous Drain Current, TA = 25°C(1)
Pulsed Drain Current, TA = 25°C(2)
Power Dissipation(1)
A
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
11
72
IDM
PD
TJ,
A
3.2
W
Operating Junction and Storage
TSTG Temperature Range
–55 to 150
55
°C
D
Avalanche Energy, single pulse
ID = 33A, L = 0.1mH, RG = 25Ω
D
EAS
mJ
P0093-01
(1) Typical RθJA = 40°C/W on a 1-inch2, 2-oz. Cu pad on a 0.06-
inch thick FR4 PCB.
(2) Pulse duration ≤300μs, duty cycle ≤2%
RDS(on) vs VGS
GATE CHARGE
36
32
28
24
20
16
12
8
10
TC = 25°C Id = 12A
TC = 125ºC Id = 12A
ID = 12A
VDS = 30V
9
8
7
6
5
4
3
2
1
0
4
0
0
2
4
6
8
10
12
14
16
18
20
0
3
6
9
12
15
Qg - Gate Charge (nC)
VGS - Gate-to- Source Voltage (V)
G001
G001
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
CSD18537NQ5A
SLPS391 –JUNE 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
Static Characteristics
TEST CONDITIONS
MIN
TYP
MAX UNIT
BVDSS
IDSS
Drain to Source Voltage
VGS = 0V, ID = 250μA
60
V
Drain to Source Leakage Current
Gate to Source Leakage Current
Gate to Source Threshold Voltage
VGS = 0V, VDS = 48V
VDS = 0V, VGS = 20V
VDS = VGS, ID = 250μA
VGS = 6V, ID = 12A
VGS = 10V, ID = 12A
VDS = 30V, ID = 12A
1
100
3.5
17
μA
nA
V
IGSS
VGS(th)
2.6
3.0
13
10
62
mΩ
mΩ
S
RDS(on)
Drain to Source On Resistance
13
gfs
Transconductance
Dynamic Characteristics
Ciss
Coss
Crss
RG
Input Capacitance
1140
136
4
1480
177
5.2
pF
pF
pF
Ω
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Gate Charge Total (10V)
Gate Charge Gate to Drain
Gate Charge Gate to Source
Gate Charge at Vth
Output Charge
VGS = 0V, VDS = 30V, f = 1MHz
5.5
14
11.0
18
Qg
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
2.3
4.7
3.3
25
VDS = 30V, ID = 12A
VDS = 30V, VGS = 0V
Turn On Delay Time
Rise Time
5.8
4.0
14.4
3.2
VDS = 30V, VGS = 10V, IDS = 12A, RG = 0Ω
td(off)
tf
Turn Off Delay Time
Fall Time
Diode Characteristics
VSD
Qrr
trr
Diode Forward Voltage
ISD = 12A, VGS = 0V
0.8
54
40
1
V
Reverse Recovery Charge
Reverse Recovery Time
nC
ns
VDS= 30V, IF = 12A, di/dt = 300A/μs
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
Thermal Resistance Junction to Case(1)
Thermal Resistance Junction to Ambient(1)(2)
MIN
TYP
MAX
UNIT
°C/W
°C/W
RθJC
RθJA
1.6
50
(1)
R
θJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
2
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Product Folder Links: CSD18537NQ5A
CSD18537NQ5A
www.ti.com
SLPS391 –JUNE 2013
GATE
Source
GATE
Source
Max RθJA = 50°C/W
when mounted on
1 inch2 (6.45 cm2) of 2-
oz. (0.071-mm thick)
Cu.
Max RθJA = 125°C/W
when mounted on a
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
Copyright © 2013, Texas Instruments Incorporated
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SLPS391 –JUNE 2013
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
50
45
40
35
30
25
20
15
10
5
50
40
30
20
10
0
VDS = 5V
VGS =10V
VGS =8V
VGS =6V
TC = 125°C
TC = 25°C
TC = −55°C
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0
0
0
1
2
3
4
5
6
7
8
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
G001
G001
Figure 2. Saturation Characteristics
TEXT ADDED FOR SPACING
Figure 3. Transfer Characteristics
TEXT ADDED FOR SPACING
10
9
8
7
6
5
4
3
2
1
0
20000
10000
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
ID = 12A
VDS = 30V
1000
100
10
1
0
3
6
9
12
15
10
20
30
40
50
60
Qg - Gate Charge (nC)
VDS - Drain-to-Source Voltage (V)
G001
G001
Figure 4. Gate Charge
Figure 5. Capacitance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
3.6
3.4
3.2
3
36
32
28
24
20
16
12
8
ID = 250uA
TC = 25°C Id = 12A
TC = 125ºC Id = 12A
2.8
2.6
2.4
2.2
2
4
0
−75
−25
25
75
125
175
2
4
6
8
10
12
14
16
18
20
TC - Case Temperature (ºC)
VGS - Gate-to- Source Voltage (V)
G001
G001
Figure 6. Threshold Voltage vs. Temperature
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
4
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Product Folder Links: CSD18537NQ5A
CSD18537NQ5A
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SLPS391 –JUNE 2013
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
2.2
2
100
10
VGS = 6V
VGS = 10V
TC = 25°C
TC = 125°C
1.8
1.6
1.4
1.2
1
1
0.1
0.01
0.001
0.0001
0.8
0.6
0.4
ID =12A
175
−75
−25
25
75
125
0
0.2
0.4
0.6
0.8
1
TC - Case Temperature (ºC)
VSD − Source-to-Drain Voltage (V)
G001
G001
Figure 8. Normalized On-State Resistance vs. Temperature
Figure 9. Typical Diode Forward Voltage
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
5000
100
TC = 25ºC
TC = 125ºC
1ms
10ms
100ms
1s
DC
1000
100
10
1
0.1
0.01
Single Pulse
TypicalRthetaJA = 100ºC/W
10
0.01
0.01
0.1
1
10
100
0.1
1
VDS - Drain-to-Source Voltage (V)
TAV - Time in Avalanche (mS)
G001
G001
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
80
70
60
50
40
30
20
10
0
−50 −25
0
25
50
75
100 125 150 175
TC - Case Temperature (ºC)
G001
Figure 12. Maximum Drain Current vs. Temperature
Copyright © 2013, Texas Instruments Incorporated
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CSD18537NQ5A
SLPS391 –JUNE 2013
www.ti.com
MECHANICAL DATA
Q5A Package Dimensions
MILLIMETERS
NOM
DIM
MIN
0.90
0.33
0.20
4.80
3.61
5.90
5.70
3.38
3.03
1.17
0.27
0.15
0.41
1.10
0.51
0.06
0°
MAX
1.10
0.51
0.34
5.00
4.02
6.10
5.80
3.78
3.23
1.37
0.47
0.35
0.71
A
b
1.00
0.41
0.25
4.90
3.81
6.00
5.75
3.58
3.13
1.27
0.37
0.25
0.56
c
D1
D2
E
E1
E2
E3
e
e1
e2
H
K
L
0.61
0.13
0.71
0.20
12°
L1
θ
6
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Product Folder Links: CSD18537NQ5A
CSD18537NQ5A
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SLPS391 –JUNE 2013
MILLIMETERS
INCHES
Recommended PCB Pattern
DIM
MIN
MAX
6.305
4.56
4.56
0.7
MIN
MAX
0.248
0.18
F1
F1
F2
6.205
4.46
4.46
0.65
0.62
0.63
0.7
0.244
0.176
0.176
0.026
0.024
0.025
0.028
0.026
0.024
0.193
0.176
F7
F6
F3
0.18
F4
0.028
0.026
0.027
0.031
0.028
0.026
0.197
0.18
F5
0.67
0.68
0.8
F6
F7
F8
0.65
0.62
4.9
0.7
F9
0.67
5
F10
F11
4.46
4.56
F10
M0139-01
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
Recommended Stencil Opening
(0.020) 8x
0.500
(0.020)
0.500
0.500
(0.020) 8x
1.235
(0.049)
1.585
(0.062)
(0.024)
0.620
(0.170)
4.310
0.385
(0.015)
(0.062)
4x
1.570
(0.050)
1.270
0.615
1.105
(0.024)
(0.044)
3.020
(0.119)
Copyright © 2013, Texas Instruments Incorporated
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SLPS391 –JUNE 2013
www.ti.com
Q5A Tape and Reel Information
K0
4.00 0.10 ꢀ(SS ꢁNoS 1ꢂ
0.30 0.05
2.00 0.05
+0.10
–0.00
Ø 1.50
B0
A0
8.00 0.10
R 0.30 MAX
Ø 1.50 MIꢁ
R 0.30 TYP
A0 = 6.50 0.10
B0 = 5.30 0.10
K0 = 1.40 0.10
M0138-01
Notes:
1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified)
5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket
spacer
8
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
CSD18537NQ5A
ACTIVE
SON
DQJ
8
2500 Pb-Free (RoHS
Exempt)
CU SN
Level-1-260C-UNLIM
-55 to 150
18537N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD18537NQ5A
SON
DQJ
8
2500
330.0
12.4
6.3
5.3
1.2
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jul-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SON DQJ
SPQ
Length (mm) Width (mm) Height (mm)
340.0 340.0 38.0
CSD18537NQ5A
8
2500
Pack Materials-Page 2
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SI9137DB
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