CSD18543Q3A [TI]
采用 3mm x 3mm SON 封装的单路、9.9mΩ、60V、N 沟道 NexFET™ 功率 MOSFET;
| 型号： | CSD18543Q3A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 3mm x 3mm SON 封装的单路、9.9mΩ、60V、N 沟道 NexFET™ 功率 MOSFET 局域网 PC 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总14页 (文件大小：629K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CSD18543Q3A
ZHCSFS2 –DECEMBER 2016
CSD18543Q3A 60V、N 沟道 NexFET™ 功率 MOSFET
1 特性
.
1
•
•
•
•
•
•
•
•
超低 Qg 和 Qgd
低导通电阻 RDS(on)
产品概要
TA=25°C
VDS
典型值
60
单位
V
低热阻
漏源电压
雪崩额定值
无铅
Qg
栅极电荷总量 (10V)
栅极电荷（栅极到漏极）
11.1
1.7
nC
nC
Qgd
VGS = 4.5V
VGS = 10V
2.0
12.0
8.1
符合 RoHS 环保标准
无卤素
RDS(on) 漏源导通电阻
VGS(th) 阈值电压
mΩ
V
小外形尺寸无引线 (SON) 3.3mm × 3.3mm 塑料封
装
器件信息(1)
数量
器件
包装介质
封装
运输
2 应用范围
CSD18543Q3A
CSD18543Q3AT
13 英寸卷带 2500
小外形尺寸无引线
(SON)
•
•
•
•
•
固态继电器开关
直流 - 直流转换
次级侧同步整流器
经隔离转换器主级侧开关
电机控制
卷带式
3.30mm × 3.30mm
塑料封装
7 英寸卷带
250
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
绝对最大额定值
TA = 25°C
值
60
单位
V
VDS 漏源电压
VGS 栅源电压
3 说明
±20
35
V
这款采用 3.3mm × 3.3mm SON 封装的 60V、
8.1mΩ、 NexFET™功率 MOSFET 被设计成在功率转
换应用中大大降低 损耗。
持续漏极电流（受封装限制）
持续漏极电流（受芯片限制），TC = 25°C 时
测得
ID
60
A
持续漏极电流(1)
脉冲漏极电流(2)
功率耗散(1)
12
156
2.8
66
俯视图
IDM
PD
A
W
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
功率耗散，TC = 25°C
TJ， 工作结温，
-55 至 150
°C
Tstg
储存温度
雪崩能量，单一脉冲
ID = 33A，L = 0.1mH，RG = 25Ω
EAS
55
mJ
D
(1) RθJA = 45°C/W，这是在一块厚度为 0.06 英寸环氧树脂 (FR4)
印刷电路板 (PCB) 上的 1 英寸2，2 盎司铜焊盘上测得的典型
值。
D
P0093-01
(2) 最大 RθJC = 1.9°C/W，脉冲持续时间 ≤ 100μs，占空比 ≤ 1%。
.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLPS633
CSD18543Q3A
ZHCSFS2 –DECEMBER 2016
www.ti.com.cn
RDS(on) 与 VGS 间的关系
栅极电荷
30
27
24
21
18
15
12
9
10
9
8
7
6
5
4
3
2
1
0
ID = 12 A
VDS = 30 V
TC = 25°C, I D = 12 A
TC = 125°C, I D = 12 A
6
3
0
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
VGS - Gate-to-Source Voltage (V)
Qg - Gate Charge (nC)
D007
D004
2
版权 © 2016, Texas Instruments Incorporated
CSD18543Q3A
www.ti.com.cn
ZHCSFS2 –DECEMBER 2016
目录
6.1 接收文档更新通知 ..................................................... 8
6.2 社区资源.................................................................... 8
6.3 商标........................................................................... 8
6.4 静电放电警告............................................................. 8
6.5 Glossary.................................................................... 8
机械、封装和可订购信息 ......................................... 9
7.1 Q3A 封装尺寸............................................................ 9
7.2 Q3A 建议的 PCB 布局 ............................................ 10
7.3 Q3A 建议的模板布局............................................... 11
7.4 Q3A 卷带信息.......................................................... 11
1
2
3
4
5
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 3
Specifications......................................................... 4
5.1 Electrical Characteristics........................................... 4
5.2 Thermal Information.................................................. 4
5.3 Typical MOSFET Characteristics.............................. 5
器件和文档支持........................................................ 8
7
6
4 修订历史记录
日期
修订版本
注释
2016 年 12 月
*
最初发布。
版权 © 2016, Texas Instruments Incorporated
3
CSD18543Q3A
ZHCSFS2 –DECEMBER 2016
www.ti.com.cn
5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage
VGS = 0 V, ID = 250 μA
60
V
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
VGS = 0 V, VDS = 48 V
VDS = 0 V, VGS = 20 V
VDS = VGS, ID = 250 μA
VGS = 4.5 V, ID = 12 A
VGS = 10 V, ID = 12 A
VDS = 6 V, ID = 12 A
1
100
2.7
μA
nA
V
IGSS
VGS(th)
1.5
2.0
12.0
8.1
15.6
9.9
mΩ
mΩ
S
Drain-to-source
on resistance
RDS(on)
gfs
Transconductance
40
DYNAMIC CHARACTERISTICS
Ciss
Coss
Crss
RG
Input capacitance
885
168
4.8
0.5
5.6
11.1
1.7
3.1
2.0
24
1150
218
6.2
pF
pF
pF
Ω
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge total (10 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
VGS = 0 V, VDS = 30 V, ƒ = 1 MHz
1.0
Qg
7.3
nC
Qg
14.5
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
VDS = 30 V, ID = 12 A
VDS = 30 V, VGS = 0 V
nC
nC
nC
nC
ns
Turnon delay time
Rise time
9
18
ns
VDS = 30 V, VGS = 10 V,
IDS = 12 A, RG = 0 Ω
td(off)
tf
Turnoff delay time
Fall time
8
ns
4
ns
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
ISD = 12 A, VGS = 0 V
0.8
37
27
1.0
V
nC
ns
VDS= 30 V, IF = 12 A,
di/dt = 300 A/μs
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-case thermal resistance(1)
Junction-to-ambient thermal resistance(1)(2)
θJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
MIN
TYP
MAX
UNIT
RθJC
RθJA
1.9
55
°C/W
(1)
R
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board
design.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
4
Copyright © 2016, Texas Instruments Incorporated
CSD18543Q3A
www.ti.com.cn
ZHCSFS2 –DECEMBER 2016
GATE
Source
GATE
Source
Max RθJA = 55°C/W
when mounted on 1 in2
(6.45 cm2) of
2-oz (0.071-mm) thick
Cu.
Max RθJA = 160°C/W
when mounted on a
minimum pad area of
2-oz (0.071-mm) thick
Cu.
DRAIN
DRAIN
M0161-02
M0161-01
5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
Figure 1. Transient Thermal Impedance
Copyright © 2016, Texas Instruments Incorporated
5
CSD18543Q3A
ZHCSFS2 –DECEMBER 2016
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Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
160
80
70
60
50
40
30
20
10
0
VGS = 4.5 V
VGS = 6 V
TC = 125°C
TC = 25°C
TC = -55°C
140
VGS = 10 V
120
100
80
60
40
20
0
0
0.5
1
1.5
2
2.5
3
0
1
2
3
4
5
6
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
D002
D003
VDS = 5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
10
9
8
7
6
5
4
3
2
1
0
10000
1000
100
10
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1
0
2
4
6
8
10
12
0
6
12
18
24
30
36
42
48
54
60
Qg - Gate Charge (nC)
VDS - Drain-to-Source Voltage (V)
D004
D005
VDS = 30 V
ID = 12 A
Figure 4. Gate Charge
Figure 5. Capacitance
30
27
24
21
18
15
12
9
2.6
2.4
2.2
2
TC = 25°C, I D = 12 A
TC = 125°C, I D = 12 A
1.8
1.6
1.4
1.2
1
6
3
0
0
-75 -50 -25
0
25
50
75 100 125 150 175
2
4
6
8
10
12
14
16
18
20
TC - Case Temperature (°C)
VGS - Gate-to-Source Voltage (V)
D006
D007
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
6
Copyright © 2016, Texas Instruments Incorporated
CSD18543Q3A
www.ti.com.cn
ZHCSFS2 –DECEMBER 2016
Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
100
10
2
TC = 25èC
TC = 125èC
VGS = 4.5 V
VGS = 10 V
1.8
1.6
1.4
1.2
1
1
0.1
0.01
0.001
0.0001
0.8
0.6
0.4
-75 -50 -25
0
25
50
75 100 125 150 175
0
0.2
0.4
0.6
0.8
1
TC - Case Temperature (èC)
VSD - Source-To-Drain Voltage (V)
D008
D009
ID = 12 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
1000
100
10
1
TC = 25è C
TC = 125è C
100
10
1
DC
10 ms
1 ms
100 µs
0.1
0.1
1
10
100
0.01
0.1
1
VDS - Drain-To-Source Voltage (V)
TAV - Time in Avalanche (ms)
D010
D011
Single pulse, max RθJC = 1.9°C/W
Figure 10. Maximum Safe Operating Area (SOA)
Figure 11. Single Pulse Unclamped Inductive Switching
40
35
30
25
20
15
10
5
0
-50
-25
0
25
50
75
100 125 150 175
TC - Case Temperature (°C)
D012
Max RθJC = 1.9°C/W
Figure 12. Maximum Drain Current vs Temperature
Copyright © 2016, Texas Instruments Incorporated
7
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ZHCSFS2 –DECEMBER 2016
www.ti.com.cn
6 器件和文档支持
6.1 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
6.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.3 商标
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
6.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
8
版权 © 2016, Texas Instruments Incorporated
CSD18543Q3A
www.ti.com.cn
ZHCSFS2 –DECEMBER 2016
7 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。要获得这份数据表的浏览器版本，请查阅左侧的导航栏。
7.1 Q3A 封装尺寸
3.1
2.9
A
B
PIN 1 INDEX AREA
3.25
3.05
2X 0.15 MAX
2X (0.2)
3.5
3.1
TYP
C
0.9 MAX
SEATING PLANE
0.05
0.00
(0.2)
1.74±0.1
0.52
0.32
4X
0.565±0.1
4
(0.15) TYP
EXPOSED THERMAL PAD
NOTE 3
5
9
2X 1.95
2.45±0.1
0.65 TYP
8
1
0.35
8X
0.55
4X
0.25
0.25
0.1
C B
C
A
4X 1.45
0.05
2X
NOTE 4
1. 所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和容限值遵循 ASME Y14.5M。
2. 本图纸如有变更，恕不通知。
3. 必须在印刷电路板上焊接封装散热焊盘，以获得良好的散热和机械性能。
4. 金属化 特性 为供应商选配特性，因此封装上可能不具备。
5. 所有尺寸不包括模具毛边或突出部分。
版权 © 2016, Texas Instruments Incorporated
9
CSD18543Q3A
ZHCSFS2 –DECEMBER 2016
www.ti.com.cn
7.2 Q3A 建议的 PCB 布局
(1.775)
PKG
0.05 MIN
ALL SIDES
(0.635)
TYP
(0.56)
4X (0.3)
4X (0.6)
1
8
4X (0.3)
(R0.05)
TYP
(0.975)
TYP
9
SYMM
(2.45)
3X (0.65)
3X (0.65)
4
5
(
(R0.05) TYP
SOLDER MASK
OPENING
(0.207)
(0.245)
0.2) VIA
TYP
METAL UNDER
SOLDER MASK
(0.905)
TYP
(1.55)
1. 此封装设计用于焊接到电路板的散热焊盘上。更多信息，请参见《QFN/SON
号：SLUA271）。
PCB
连接》（文献编
2. 根据应用决定是否选用过孔，详情请参见器件数据表。如果实现了部分或全部过孔，则会显示建议的过孔位
置。
有关针对
PCB
设计的建议电路布局布线，请参见《通过
PCB
布局布线技巧来减少振铃》（文献编
号：SLPA005）。
10
版权 © 2016, Texas Instruments Incorporated
CSD18543Q3A
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ZHCSFS2 –DECEMBER 2016
7.3 Q3A 建议的模板布局
(0.905)
PKG
8X (0.6)
8X (0.3)
(0.208)
SOLDER MASK EDGE
1
8
(0.663)
SYMM
9
(1.325)
6X (0.65)
4X 1.125
5
4
(R0.05) TYP
METAL
TYP
4X 0.705
(3.1)
1. 具有漏斗形壁和圆角的激光切割窗孔将提供更佳的焊锡膏脱离。IPC-7525 可能提供其他替代性设计建议。
7.4 Q3A 卷带信息
4.00 0.ꢀ0 ꢁ(SS ꢂNoS ꢀ1
8.00 0.ꢀ0
2.00 0.0ꢃ
Ø ꢀ.ꢃ0
+0.ꢀ0
–0.00
3.60
M0ꢀ44-0ꢀ
Notes: 1. 10 个链齿孔的累积容差为 ±0.2。
2. 每 100mm 长度的翘曲不能超过 1mm，在 250mm 长度上不累积。
3. 材料：黑色抗静电聚苯乙烯。
4. 全部尺寸单位为 mm，除非另外注明。
5. 厚度：0.30 ± 0.05mm。
6. MSL1 260°C（红外 (IR) 和传导）PbF 回流焊兼容。
版权 © 2016, Texas Instruments Incorporated
11
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CSD18543Q3A
CSD18543Q3AT
ACTIVE
ACTIVE
VSONP
VSONP
DNH
DNH
8
8
2500 RoHS & Green
250 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
18543
18543
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
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